1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
17 field bits<32> SoftFail = 0;
20 bit PPC64 = 0; // Default value, override with isPPC64
22 let Namespace = "PPC";
23 let Inst{0-5} = opcode;
24 let OutOperandList = OOL;
25 let InOperandList = IOL;
26 let AsmString = asmstr;
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
35 /// these must be reflected there! See comments there for what these are.
36 let TSFlags{0} = PPC970_First;
37 let TSFlags{1} = PPC970_Single;
38 let TSFlags{2} = PPC970_Cracked;
39 let TSFlags{5-3} = PPC970_Unit;
41 /// Indicate that the VSX instruction is to use VSX numbering/encoding.
42 /// Since ISA 3.0, there are scalar instructions that use the upper
43 /// half of the VSX register set only. Rather than adding further complexity
44 /// to the register class set, the VSX registers just include the Altivec
45 /// registers and this flag decides the numbering to be used for them.
46 bits<1> UseVSXReg = 0;
47 let TSFlags{6} = UseVSXReg;
49 // Fields used for relation models.
52 // For cases where multiple instruction definitions really represent the
53 // same underlying instruction but with one definition for 64-bit arguments
54 // and one for 32-bit arguments, this bit breaks the degeneracy between
55 // the two forms and allows TableGen to generate mapping tables.
56 bit Interpretation64Bit = 0;
59 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
60 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
61 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
62 class PPC970_MicroCode;
64 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
65 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
66 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
67 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
68 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
69 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
70 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
71 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
73 class UseVSXReg { bits<1> UseVSXReg = 1; }
75 // Two joined instructions; used to emit two adjacent instructions as one.
76 // The itinerary from the first instruction is used for scheduling and
78 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
82 field bits<64> SoftFail = 0;
85 bit PPC64 = 0; // Default value, override with isPPC64
87 let Namespace = "PPC";
88 let Inst{0-5} = opcode1;
89 let Inst{32-37} = opcode2;
90 let OutOperandList = OOL;
91 let InOperandList = IOL;
92 let AsmString = asmstr;
95 bits<1> PPC970_First = 0;
96 bits<1> PPC970_Single = 0;
97 bits<1> PPC970_Cracked = 0;
98 bits<3> PPC970_Unit = 0;
100 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
101 /// these must be reflected there! See comments there for what these are.
102 let TSFlags{0} = PPC970_First;
103 let TSFlags{1} = PPC970_Single;
104 let TSFlags{2} = PPC970_Cracked;
105 let TSFlags{5-3} = PPC970_Unit;
107 // Fields used for relation models.
108 string BaseName = "";
109 bit Interpretation64Bit = 0;
113 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
114 InstrItinClass itin, list<dag> pattern>
115 : I<opcode, OOL, IOL, asmstr, itin> {
116 let Pattern = pattern;
125 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
126 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
127 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
132 let BI{0-1} = BIBO{5-6};
133 let BI{2-4} = CR{0-2};
135 let Inst{6-10} = BIBO{4-0};
136 let Inst{11-15} = BI;
137 let Inst{16-29} = BD;
142 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
144 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
150 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
151 dag OOL, dag IOL, string asmstr>
152 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
156 let Inst{11-15} = bi;
157 let Inst{16-29} = BD;
162 class BForm_3<bits<6> opcode, bit aa, bit lk,
163 dag OOL, dag IOL, string asmstr>
164 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
170 let Inst{11-15} = BI;
171 let Inst{16-29} = BD;
176 class BForm_3_at<bits<6> opcode, bit aa, bit lk,
177 dag OOL, dag IOL, string asmstr>
178 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
184 let Inst{6-8} = BO{4-2};
186 let Inst{11-15} = BI;
187 let Inst{16-29} = BD;
192 class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
193 dag OOL, dag IOL, string asmstr>
194 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
199 let Inst{11-15} = BI;
200 let Inst{16-29} = BD;
206 class SCForm<bits<6> opcode, bits<1> xo,
207 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
209 : I<opcode, OOL, IOL, asmstr, itin> {
212 let Pattern = pattern;
214 let Inst{20-26} = LEV;
219 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
220 InstrItinClass itin, list<dag> pattern>
221 : I<opcode, OOL, IOL, asmstr, itin> {
226 let Pattern = pattern;
233 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
234 InstrItinClass itin, list<dag> pattern>
235 : I<opcode, OOL, IOL, asmstr, itin> {
239 let Pattern = pattern;
242 let Inst{11-15} = Addr{20-16}; // Base Reg
243 let Inst{16-31} = Addr{15-0}; // Displacement
246 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
247 InstrItinClass itin, list<dag> pattern>
248 : I<opcode, OOL, IOL, asmstr, itin> {
253 let Pattern = pattern;
261 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
262 InstrItinClass itin, list<dag> pattern>
263 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
265 // Even though ADDICo does not really have an RC bit, provide
266 // the declaration of one here so that isDOT has something to set.
270 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
271 InstrItinClass itin, list<dag> pattern>
272 : I<opcode, OOL, IOL, asmstr, itin> {
276 let Pattern = pattern;
283 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
284 InstrItinClass itin, list<dag> pattern>
285 : I<opcode, OOL, IOL, asmstr, itin> {
290 let Pattern = pattern;
297 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
298 InstrItinClass itin, list<dag> pattern>
299 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
304 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
305 string asmstr, InstrItinClass itin,
307 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
313 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
314 dag OOL, dag IOL, string asmstr,
315 InstrItinClass itin, list<dag> pattern>
316 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
320 let Pattern = pattern;
328 let Inst{43-47} = Addr{20-16}; // Base Reg
329 let Inst{48-63} = Addr{15-0}; // Displacement
332 // This is used to emit BL8+NOP.
333 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
334 dag OOL, dag IOL, string asmstr,
335 InstrItinClass itin, list<dag> pattern>
336 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
337 OOL, IOL, asmstr, itin, pattern> {
342 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
344 : I<opcode, OOL, IOL, asmstr, itin> {
353 let Inst{11-15} = RA;
357 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
359 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
363 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
365 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
367 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
369 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
375 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
376 InstrItinClass itin, list<dag> pattern>
377 : I<opcode, OOL, IOL, asmstr, itin> {
381 let Pattern = pattern;
383 let Inst{6-10} = RST;
384 let Inst{11-15} = DS_RA{18-14}; // Register #
385 let Inst{16-29} = DS_RA{13-0}; // Displacement.
386 let Inst{30-31} = xo;
389 // DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO]
390 class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
391 string asmstr, InstrItinClass itin, list<dag> pattern>
392 : I<opcode, OOL, IOL, asmstr, itin> {
396 let Pattern = pattern;
398 let Inst{6-10} = XT{4-0};
399 let Inst{11-15} = DS_RA{16-12}; // Register #
400 let Inst{16-27} = DS_RA{11-0}; // Displacement.
401 let Inst{28} = XT{5};
402 let Inst{29-31} = xo;
406 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
407 InstrItinClass itin, list<dag> pattern>
408 : I<opcode, OOL, IOL, asmstr, itin> {
413 let Pattern = pattern;
415 bit RC = 0; // set by isDOT
417 let Inst{6-10} = RST;
420 let Inst{21-30} = xo;
424 class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr,
425 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> {
429 class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
431 : I<opcode, OOL, IOL, asmstr, itin> {
432 let Inst{21-30} = xo;
435 // This is the same as XForm_base_r3xo, but the first two operands are swapped
436 // when code is emitted.
437 class XForm_base_r3xo_swapped
438 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
440 : I<opcode, OOL, IOL, asmstr, itin> {
445 bit RC = 0; // set by isDOT
447 let Inst{6-10} = RST;
450 let Inst{21-30} = xo;
455 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
456 InstrItinClass itin, list<dag> pattern>
457 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
459 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
460 InstrItinClass itin, list<dag> pattern>
461 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
465 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
466 InstrItinClass itin, list<dag> pattern>
467 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
472 class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
473 InstrItinClass itin, list<dag> pattern>
474 : I<opcode, OOL, IOL, asmstr, itin> {
479 let Pattern = pattern;
481 let Inst{6-10} = RST;
484 let Inst{21-30} = xo;
488 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
489 InstrItinClass itin, list<dag> pattern>
490 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
491 let Pattern = pattern;
494 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
495 InstrItinClass itin, list<dag> pattern>
496 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
498 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
499 InstrItinClass itin, list<dag> pattern>
500 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
501 let Pattern = pattern;
504 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
505 InstrItinClass itin, list<dag> pattern>
506 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
508 let Pattern = pattern;
511 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
513 : I<opcode, OOL, IOL, asmstr, itin> {
522 let Inst{11-15} = RA;
523 let Inst{16-20} = RB;
524 let Inst{21-30} = xo;
528 class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
530 : I<opcode, OOL, IOL, asmstr, itin> {
537 let Inst{11-15} = RA;
538 let Inst{16-20} = RB;
539 let Inst{21-30} = xo;
543 class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
545 : I<opcode, OOL, IOL, asmstr, itin> {
550 let Inst{12-15} = SR;
551 let Inst{21-30} = xo;
554 class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
556 : I<opcode, OOL, IOL, asmstr, itin> {
560 let Inst{21-30} = xo;
563 class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
565 : I<opcode, OOL, IOL, asmstr, itin> {
570 let Inst{16-20} = RB;
571 let Inst{21-30} = xo;
574 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
576 : I<opcode, OOL, IOL, asmstr, itin> {
582 let Inst{21-30} = xo;
585 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
587 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
591 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
593 : I<opcode, OOL, IOL, asmstr, itin> {
600 let Inst{11-15} = FRA;
601 let Inst{16-20} = FRB;
602 let Inst{21-30} = xo;
607 class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
608 InstrItinClass itin, list<dag> pattern>
609 : I<opcode, OOL, IOL, asmstr, itin> {
614 let Pattern = pattern;
616 let Inst{6-10} = FRT;
617 let Inst{11-15} = FRA;
618 let Inst{16-20} = FRB;
619 let Inst{21-30} = xo;
623 class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
624 InstrItinClass itin, list<dag> pattern>
625 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
629 class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr,
630 InstrItinClass itin, list<dag> pattern>
631 : I<opcode, OOL, IOL, asmstr, itin> {
637 let Pattern = pattern;
639 let Inst{6-10} = FRT;
640 let Inst{11-15} = FRA;
641 let Inst{16-20} = FRB;
642 let Inst{21-24} = tttt;
643 let Inst{25-30} = xo;
647 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
648 InstrItinClass itin, list<dag> pattern>
649 : I<opcode, OOL, IOL, asmstr, itin> {
650 let Pattern = pattern;
654 let Inst{21-30} = xo;
658 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
659 string asmstr, InstrItinClass itin, list<dag> pattern>
660 : I<opcode, OOL, IOL, asmstr, itin> {
663 let Pattern = pattern;
668 let Inst{21-30} = xo;
672 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
673 string asmstr, InstrItinClass itin, list<dag> pattern>
674 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
678 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
679 InstrItinClass itin, list<dag> pattern>
680 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
683 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
684 InstrItinClass itin, list<dag> pattern>
685 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
689 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
690 InstrItinClass itin, list<dag> pattern>
691 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
694 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
695 // numbers presumably relates to some document, but I haven't found it.
696 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
697 InstrItinClass itin, list<dag> pattern>
698 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
699 let Pattern = pattern;
701 bit RC = 0; // set by isDOT
703 let Inst{6-10} = RST;
705 let Inst{21-30} = xo;
708 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
709 InstrItinClass itin, list<dag> pattern>
710 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
711 let Pattern = pattern;
714 bit RC = 0; // set by isDOT
718 let Inst{21-30} = xo;
722 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
723 InstrItinClass itin, list<dag> pattern>
724 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
730 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
731 InstrItinClass itin, list<dag> pattern>
732 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
737 class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
738 string asmstr, InstrItinClass itin, list<dag> pattern>
739 : I<opcode, OOL, IOL, asmstr, itin> {
747 let Inst{21-30} = xo;
751 class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
752 string asmstr, InstrItinClass itin, list<dag> pattern>
753 : I<opcode, OOL, IOL, asmstr, itin> {
760 let Inst{21-30} = xo;
764 class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
765 InstrItinClass itin, list<dag> pattern>
766 : I<opcode, OOL, IOL, asmstr, itin> {
769 bit RC = 0; // set by isDOT
774 let Inst{21-30} = xo;
778 class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
779 InstrItinClass itin, list<dag> pattern>
780 : I<opcode, OOL, IOL, asmstr, itin> {
787 let Inst{21-30} = xo;
791 // [PO RT RA RB XO /]
792 class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
793 string asmstr, InstrItinClass itin, list<dag> pattern>
794 : I<opcode, OOL, IOL, asmstr, itin> {
800 let Pattern = pattern;
805 let Inst{11-15} = RA;
806 let Inst{16-20} = RB;
807 let Inst{21-30} = xo;
811 // Same as XForm_17 but with GPR's and new naming convention
812 class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
813 string asmstr, InstrItinClass itin, list<dag> pattern>
814 : I<opcode, OOL, IOL, asmstr, itin> {
819 let Pattern = pattern;
823 let Inst{11-15} = RA;
824 let Inst{16-20} = RB;
825 let Inst{21-30} = xo;
829 // e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO]
830 class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
831 string asmstr, InstrItinClass itin, list<dag> pattern>
832 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
836 class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
837 string asmstr, InstrItinClass itin, list<dag> pattern>
838 : I<opcode, OOL, IOL, asmstr, itin> {
843 let Pattern = pattern;
846 let Inst{9-15} = DCMX;
847 let Inst{16-20} = VB;
848 let Inst{21-30} = xo;
852 class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
853 string asmstr, InstrItinClass itin, list<dag> pattern>
854 : I<opcode, OOL, IOL, asmstr, itin> {
858 let Pattern = pattern;
860 let Inst{6-10} = XT{4-0};
862 let Inst{13-20} = IMM8;
863 let Inst{21-30} = xo;
864 let Inst{31} = XT{5};
867 // XForm_base_r3xo for instructions such as P9 atomics where we don't want
868 // to specify an SDAG pattern for matching.
869 class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
870 string asmstr, InstrItinClass itin>
871 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, []> {
874 class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
876 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> {
881 // [PO /// L RA RB XO /]
882 class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
883 string asmstr, InstrItinClass itin, list<dag> pattern>
884 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
886 let Pattern = pattern;
893 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
894 InstrItinClass itin, list<dag> pattern>
895 : I<opcode, OOL, IOL, asmstr, itin> {
900 let Pattern = pattern;
902 let Inst{6-10} = XT{4-0};
905 let Inst{21-30} = xo;
906 let Inst{31} = XT{5};
909 class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
910 string asmstr, InstrItinClass itin, list<dag> pattern>
911 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
915 class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
916 InstrItinClass itin, list<dag> pattern>
917 : I<opcode, OOL, IOL, asmstr, itin> {
921 let Pattern = pattern;
923 let Inst{6-10} = XT{4-0};
925 let Inst{16-20} = XB{4-0};
926 let Inst{21-29} = xo;
927 let Inst{30} = XB{5};
928 let Inst{31} = XT{5};
931 class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
932 InstrItinClass itin, list<dag> pattern>
933 : I<opcode, OOL, IOL, asmstr, itin> {
937 let Pattern = pattern;
941 let Inst{16-20} = XB{4-0};
942 let Inst{21-29} = xo;
943 let Inst{30} = XB{5};
947 class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
948 InstrItinClass itin, list<dag> pattern>
949 : I<opcode, OOL, IOL, asmstr, itin> {
954 let Pattern = pattern;
956 let Inst{6-10} = XT{4-0};
959 let Inst{16-20} = XB{4-0};
960 let Inst{21-29} = xo;
961 let Inst{30} = XB{5};
962 let Inst{31} = XT{5};
965 class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
966 string asmstr, InstrItinClass itin, list<dag> pattern>
967 : I<opcode, OOL, IOL, asmstr, itin> {
972 let Pattern = pattern;
974 let Inst{6-10} = XT{4-0};
975 let Inst{11-15} = UIM5;
976 let Inst{16-20} = XB{4-0};
977 let Inst{21-29} = xo;
978 let Inst{30} = XB{5};
979 let Inst{31} = XT{5};
982 // [PO T XO B XO BX /]
983 class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
984 string asmstr, InstrItinClass itin, list<dag> pattern>
985 : I<opcode, OOL, IOL, asmstr, itin> {
989 let Pattern = pattern;
992 let Inst{11-15} = xo2;
993 let Inst{16-20} = XB{4-0};
994 let Inst{21-29} = xo;
995 let Inst{30} = XB{5};
999 // [PO T XO B XO BX TX]
1000 class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
1001 string asmstr, InstrItinClass itin, list<dag> pattern>
1002 : I<opcode, OOL, IOL, asmstr, itin> {
1006 let Pattern = pattern;
1008 let Inst{6-10} = XT{4-0};
1009 let Inst{11-15} = xo2;
1010 let Inst{16-20} = XB{4-0};
1011 let Inst{21-29} = xo;
1012 let Inst{30} = XB{5};
1013 let Inst{31} = XT{5};
1016 class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
1017 string asmstr, InstrItinClass itin, list<dag> pattern>
1018 : I<opcode, OOL, IOL, asmstr, itin> {
1023 let Pattern = pattern;
1026 let Inst{9-15} = DCMX;
1027 let Inst{16-20} = XB{4-0};
1028 let Inst{21-29} = xo;
1029 let Inst{30} = XB{5};
1033 class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2,
1034 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
1036 : I<opcode, OOL, IOL, asmstr, itin> {
1041 let Pattern = pattern;
1043 let Inst{6-10} = XT{4-0};
1044 let Inst{11-15} = DCMX{4-0};
1045 let Inst{16-20} = XB{4-0};
1046 let Inst{21-24} = xo1;
1047 let Inst{25} = DCMX{5};
1048 let Inst{26-28} = xo2;
1049 let Inst{29} = DCMX{6};
1050 let Inst{30} = XB{5};
1051 let Inst{31} = XT{5};
1054 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1055 InstrItinClass itin, list<dag> pattern>
1056 : I<opcode, OOL, IOL, asmstr, itin> {
1061 let Pattern = pattern;
1063 let Inst{6-10} = XT{4-0};
1064 let Inst{11-15} = XA{4-0};
1065 let Inst{16-20} = XB{4-0};
1066 let Inst{21-28} = xo;
1067 let Inst{29} = XA{5};
1068 let Inst{30} = XB{5};
1069 let Inst{31} = XT{5};
1072 class XX3Form_Zero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1073 InstrItinClass itin, list<dag> pattern>
1074 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1079 class XX3Form_SetZero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1080 InstrItinClass itin, list<dag> pattern>
1081 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1086 class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1087 InstrItinClass itin, list<dag> pattern>
1088 : I<opcode, OOL, IOL, asmstr, itin> {
1093 let Pattern = pattern;
1097 let Inst{11-15} = XA{4-0};
1098 let Inst{16-20} = XB{4-0};
1099 let Inst{21-28} = xo;
1100 let Inst{29} = XA{5};
1101 let Inst{30} = XB{5};
1105 class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1106 InstrItinClass itin, list<dag> pattern>
1107 : I<opcode, OOL, IOL, asmstr, itin> {
1113 let Pattern = pattern;
1115 let Inst{6-10} = XT{4-0};
1116 let Inst{11-15} = XA{4-0};
1117 let Inst{16-20} = XB{4-0};
1119 let Inst{22-23} = D;
1120 let Inst{24-28} = xo;
1121 let Inst{29} = XA{5};
1122 let Inst{30} = XB{5};
1123 let Inst{31} = XT{5};
1126 class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr,
1127 InstrItinClass itin, list<dag> pattern>
1128 : I<opcode, OOL, IOL, asmstr, itin> {
1133 let Pattern = pattern;
1135 bit RC = 0; // set by isDOT
1137 let Inst{6-10} = XT{4-0};
1138 let Inst{11-15} = XA{4-0};
1139 let Inst{16-20} = XB{4-0};
1141 let Inst{22-28} = xo;
1142 let Inst{29} = XA{5};
1143 let Inst{30} = XB{5};
1144 let Inst{31} = XT{5};
1147 class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
1148 InstrItinClass itin, list<dag> pattern>
1149 : I<opcode, OOL, IOL, asmstr, itin> {
1155 let Pattern = pattern;
1157 let Inst{6-10} = XT{4-0};
1158 let Inst{11-15} = XA{4-0};
1159 let Inst{16-20} = XB{4-0};
1160 let Inst{21-25} = XC{4-0};
1161 let Inst{26-27} = xo;
1162 let Inst{28} = XC{5};
1163 let Inst{29} = XA{5};
1164 let Inst{30} = XB{5};
1165 let Inst{31} = XT{5};
1168 // DCB_Form - Form X instruction, used for dcb* instructions.
1169 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
1170 InstrItinClass itin, list<dag> pattern>
1171 : I<31, OOL, IOL, asmstr, itin> {
1175 let Pattern = pattern;
1177 let Inst{6-10} = immfield;
1178 let Inst{11-15} = A;
1179 let Inst{16-20} = B;
1180 let Inst{21-30} = xo;
1184 class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr,
1185 InstrItinClass itin, list<dag> pattern>
1186 : I<31, OOL, IOL, asmstr, itin> {
1191 let Pattern = pattern;
1193 let Inst{6-10} = TH;
1194 let Inst{11-15} = A;
1195 let Inst{16-20} = B;
1196 let Inst{21-30} = xo;
1200 // DSS_Form - Form X instruction, used for altivec dss* instructions.
1201 class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr,
1202 InstrItinClass itin, list<dag> pattern>
1203 : I<31, OOL, IOL, asmstr, itin> {
1208 let Pattern = pattern;
1212 let Inst{9-10} = STRM;
1213 let Inst{11-15} = A;
1214 let Inst{16-20} = B;
1215 let Inst{21-30} = xo;
1220 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1221 InstrItinClass itin, list<dag> pattern>
1222 : I<opcode, OOL, IOL, asmstr, itin> {
1227 let Pattern = pattern;
1229 let Inst{6-10} = CRD;
1230 let Inst{11-15} = CRA;
1231 let Inst{16-20} = CRB;
1232 let Inst{21-30} = xo;
1236 class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1237 InstrItinClass itin, list<dag> pattern>
1238 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1244 class XLForm_1_gen<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1245 InstrItinClass itin, list<dag> pattern>
1246 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1255 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1256 InstrItinClass itin, list<dag> pattern>
1257 : I<opcode, OOL, IOL, asmstr, itin> {
1260 let Pattern = pattern;
1262 let Inst{6-10} = CRD;
1263 let Inst{11-15} = CRD;
1264 let Inst{16-20} = CRD;
1265 let Inst{21-30} = xo;
1269 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
1270 InstrItinClass itin, list<dag> pattern>
1271 : I<opcode, OOL, IOL, asmstr, itin> {
1276 let Pattern = pattern;
1278 let Inst{6-10} = BO;
1279 let Inst{11-15} = BI;
1280 let Inst{16-18} = 0;
1281 let Inst{19-20} = BH;
1282 let Inst{21-30} = xo;
1286 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
1287 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1288 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1289 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
1293 let BI{0-1} = BIBO{5-6};
1294 let BI{2-4} = CR{0-2};
1298 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
1299 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1300 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1305 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
1306 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1307 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1313 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1314 InstrItinClass itin>
1315 : I<opcode, OOL, IOL, asmstr, itin> {
1321 let Inst{11-13} = BFA;
1322 let Inst{14-15} = 0;
1323 let Inst{16-20} = 0;
1324 let Inst{21-30} = xo;
1328 class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1329 InstrItinClass itin>
1330 : I<opcode, OOL, IOL, asmstr, itin> {
1339 let Inst{11-14} = 0;
1341 let Inst{16-19} = U;
1343 let Inst{21-30} = xo;
1347 class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1348 InstrItinClass itin, list<dag> pattern>
1349 : I<opcode, OOL, IOL, asmstr, itin> {
1352 let Pattern = pattern;
1356 let Inst{21-30} = xo;
1360 class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
1361 bits<6> opcode2, bits<2> xo2,
1362 dag OOL, dag IOL, string asmstr,
1363 InstrItinClass itin, list<dag> pattern>
1364 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
1372 let Pattern = pattern;
1374 let Inst{6-10} = BO;
1375 let Inst{11-15} = BI;
1376 let Inst{16-18} = 0;
1377 let Inst{19-20} = BH;
1378 let Inst{21-30} = xo1;
1381 let Inst{38-42} = RST;
1382 let Inst{43-47} = DS_RA{18-14}; // Register #
1383 let Inst{48-61} = DS_RA{13-0}; // Displacement.
1384 let Inst{62-63} = xo2;
1387 class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
1388 bits<5> bo, bits<5> bi, bit lk,
1389 bits<6> opcode2, bits<2> xo2,
1390 dag OOL, dag IOL, string asmstr,
1391 InstrItinClass itin, list<dag> pattern>
1392 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2,
1393 OOL, IOL, asmstr, itin, pattern> {
1400 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1401 InstrItinClass itin>
1402 : I<opcode, OOL, IOL, asmstr, itin> {
1406 let Inst{6-10} = RT;
1407 let Inst{11} = SPR{4};
1408 let Inst{12} = SPR{3};
1409 let Inst{13} = SPR{2};
1410 let Inst{14} = SPR{1};
1411 let Inst{15} = SPR{0};
1412 let Inst{16} = SPR{9};
1413 let Inst{17} = SPR{8};
1414 let Inst{18} = SPR{7};
1415 let Inst{19} = SPR{6};
1416 let Inst{20} = SPR{5};
1417 let Inst{21-30} = xo;
1421 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1422 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1423 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
1427 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1428 InstrItinClass itin>
1429 : I<opcode, OOL, IOL, asmstr, itin> {
1432 let Inst{6-10} = RT;
1433 let Inst{11-20} = 0;
1434 let Inst{21-30} = xo;
1438 class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1439 InstrItinClass itin, list<dag> pattern>
1440 : I<opcode, OOL, IOL, asmstr, itin> {
1443 let Pattern = pattern;
1445 let Inst{6-10} = RT;
1446 let Inst{11-20} = Entry;
1447 let Inst{21-30} = xo;
1451 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1452 InstrItinClass itin>
1453 : I<opcode, OOL, IOL, asmstr, itin> {
1457 let Inst{6-10} = rS;
1459 let Inst{12-19} = FXM;
1461 let Inst{21-30} = xo;
1465 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1466 InstrItinClass itin>
1467 : I<opcode, OOL, IOL, asmstr, itin> {
1471 let Inst{6-10} = ST;
1473 let Inst{12-19} = FXM;
1475 let Inst{21-30} = xo;
1479 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1480 InstrItinClass itin>
1481 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
1483 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1484 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1485 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
1490 // This is probably 1.7.9, but I don't have the reference that uses this
1491 // numbering scheme...
1492 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1493 InstrItinClass itin, list<dag>pattern>
1494 : I<opcode, OOL, IOL, asmstr, itin> {
1498 bit RC = 0; // set by isDOT
1499 let Pattern = pattern;
1502 let Inst{7-14} = FM;
1504 let Inst{16-20} = rT;
1505 let Inst{21-30} = xo;
1509 class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1510 InstrItinClass itin, list<dag>pattern>
1511 : I<opcode, OOL, IOL, asmstr, itin> {
1517 bit RC = 0; // set by isDOT
1518 let Pattern = pattern;
1521 let Inst{7-14} = FLM;
1523 let Inst{16-20} = FRB;
1524 let Inst{21-30} = xo;
1528 // 1.7.10 XS-Form - SRADI.
1529 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1530 InstrItinClass itin, list<dag> pattern>
1531 : I<opcode, OOL, IOL, asmstr, itin> {
1536 bit RC = 0; // set by isDOT
1537 let Pattern = pattern;
1539 let Inst{6-10} = RS;
1540 let Inst{11-15} = A;
1541 let Inst{16-20} = SH{4,3,2,1,0};
1542 let Inst{21-29} = xo;
1543 let Inst{30} = SH{5};
1548 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
1549 InstrItinClass itin, list<dag> pattern>
1550 : I<opcode, OOL, IOL, asmstr, itin> {
1555 let Pattern = pattern;
1557 bit RC = 0; // set by isDOT
1559 let Inst{6-10} = RT;
1560 let Inst{11-15} = RA;
1561 let Inst{16-20} = RB;
1563 let Inst{22-30} = xo;
1567 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
1568 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1569 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
1574 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1575 InstrItinClass itin, list<dag> pattern>
1576 : I<opcode, OOL, IOL, asmstr, itin> {
1582 let Pattern = pattern;
1584 bit RC = 0; // set by isDOT
1586 let Inst{6-10} = FRT;
1587 let Inst{11-15} = FRA;
1588 let Inst{16-20} = FRB;
1589 let Inst{21-25} = FRC;
1590 let Inst{26-30} = xo;
1594 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1595 InstrItinClass itin, list<dag> pattern>
1596 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1600 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1601 InstrItinClass itin, list<dag> pattern>
1602 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1606 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1607 InstrItinClass itin, list<dag> pattern>
1608 : I<opcode, OOL, IOL, asmstr, itin> {
1614 let Pattern = pattern;
1616 let Inst{6-10} = RT;
1617 let Inst{11-15} = RA;
1618 let Inst{16-20} = RB;
1619 let Inst{21-25} = COND;
1620 let Inst{26-30} = xo;
1625 class AForm_4a<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1626 InstrItinClass itin, list<dag> pattern>
1627 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1633 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1634 InstrItinClass itin, list<dag> pattern>
1635 : I<opcode, OOL, IOL, asmstr, itin> {
1642 let Pattern = pattern;
1644 bit RC = 0; // set by isDOT
1646 let Inst{6-10} = RS;
1647 let Inst{11-15} = RA;
1648 let Inst{16-20} = RB;
1649 let Inst{21-25} = MB;
1650 let Inst{26-30} = ME;
1654 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1655 InstrItinClass itin, list<dag> pattern>
1656 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
1660 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
1661 InstrItinClass itin, list<dag> pattern>
1662 : I<opcode, OOL, IOL, asmstr, itin> {
1668 let Pattern = pattern;
1670 bit RC = 0; // set by isDOT
1672 let Inst{6-10} = RS;
1673 let Inst{11-15} = RA;
1674 let Inst{16-20} = SH{4,3,2,1,0};
1675 let Inst{21-26} = MBE{4,3,2,1,0,5};
1676 let Inst{27-29} = xo;
1677 let Inst{30} = SH{5};
1681 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
1682 InstrItinClass itin, list<dag> pattern>
1683 : I<opcode, OOL, IOL, asmstr, itin> {
1689 let Pattern = pattern;
1691 bit RC = 0; // set by isDOT
1693 let Inst{6-10} = RS;
1694 let Inst{11-15} = RA;
1695 let Inst{16-20} = RB;
1696 let Inst{21-26} = MBE{4,3,2,1,0,5};
1697 let Inst{27-30} = xo;
1704 // VAForm_1 - DACB ordering.
1705 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
1706 InstrItinClass itin, list<dag> pattern>
1707 : I<4, OOL, IOL, asmstr, itin> {
1713 let Pattern = pattern;
1715 let Inst{6-10} = VD;
1716 let Inst{11-15} = VA;
1717 let Inst{16-20} = VB;
1718 let Inst{21-25} = VC;
1719 let Inst{26-31} = xo;
1722 // VAForm_1a - DABC ordering.
1723 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
1724 InstrItinClass itin, list<dag> pattern>
1725 : I<4, OOL, IOL, asmstr, itin> {
1731 let Pattern = pattern;
1733 let Inst{6-10} = VD;
1734 let Inst{11-15} = VA;
1735 let Inst{16-20} = VB;
1736 let Inst{21-25} = VC;
1737 let Inst{26-31} = xo;
1740 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1741 InstrItinClass itin, list<dag> pattern>
1742 : I<4, OOL, IOL, asmstr, itin> {
1748 let Pattern = pattern;
1750 let Inst{6-10} = VD;
1751 let Inst{11-15} = VA;
1752 let Inst{16-20} = VB;
1754 let Inst{22-25} = SH;
1755 let Inst{26-31} = xo;
1759 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1760 InstrItinClass itin, list<dag> pattern>
1761 : I<4, OOL, IOL, asmstr, itin> {
1766 let Pattern = pattern;
1768 let Inst{6-10} = VD;
1769 let Inst{11-15} = VA;
1770 let Inst{16-20} = VB;
1771 let Inst{21-31} = xo;
1774 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1775 InstrItinClass itin, list<dag> pattern>
1776 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1782 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1783 InstrItinClass itin, list<dag> pattern>
1784 : I<4, OOL, IOL, asmstr, itin> {
1788 let Pattern = pattern;
1790 let Inst{6-10} = VD;
1791 let Inst{11-15} = 0;
1792 let Inst{16-20} = VB;
1793 let Inst{21-31} = xo;
1796 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1797 InstrItinClass itin, list<dag> pattern>
1798 : I<4, OOL, IOL, asmstr, itin> {
1802 let Pattern = pattern;
1804 let Inst{6-10} = VD;
1805 let Inst{11-15} = IMM;
1806 let Inst{16-20} = 0;
1807 let Inst{21-31} = xo;
1810 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1811 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1812 InstrItinClass itin, list<dag> pattern>
1813 : I<4, OOL, IOL, asmstr, itin> {
1816 let Pattern = pattern;
1818 let Inst{6-10} = VD;
1819 let Inst{11-15} = 0;
1820 let Inst{16-20} = 0;
1821 let Inst{21-31} = xo;
1824 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1825 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1826 InstrItinClass itin, list<dag> pattern>
1827 : I<4, OOL, IOL, asmstr, itin> {
1830 let Pattern = pattern;
1833 let Inst{11-15} = 0;
1834 let Inst{16-20} = VB;
1835 let Inst{21-31} = xo;
1838 // e.g. [PO VRT EO VRB XO]
1839 class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL,
1840 string asmstr, InstrItinClass itin, list<dag> pattern>
1841 : I<4, OOL, IOL, asmstr, itin> {
1845 let Pattern = pattern;
1847 let Inst{6-10} = RD;
1848 let Inst{11-15} = eo;
1849 let Inst{16-20} = VB;
1850 let Inst{21-31} = xo;
1853 /// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX"
1854 class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr,
1855 InstrItinClass itin, list<dag> pattern>
1856 : I<4, OOL, IOL, asmstr, itin> {
1862 let Pattern = pattern;
1864 let Inst{6-10} = VD;
1865 let Inst{11-15} = VA;
1867 let Inst{17-20} = SIX;
1868 let Inst{21-31} = xo;
1871 /// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox"
1872 class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr,
1873 InstrItinClass itin, list<dag> pattern>
1874 : I<4, OOL, IOL, asmstr, itin> {
1878 let Pattern = pattern;
1880 let Inst{6-10} = VD;
1881 let Inst{11-15} = VA;
1882 let Inst{16-20} = 0;
1883 let Inst{21-31} = xo;
1887 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1888 InstrItinClass itin, list<dag> pattern>
1889 : I<4, OOL, IOL, asmstr, itin> {
1895 let Pattern = pattern;
1897 let Inst{6-10} = VD;
1898 let Inst{11-15} = VA;
1899 let Inst{16-20} = VB;
1901 let Inst{22-31} = xo;
1904 // VX-Form: [PO VRT EO VRB 1 PS XO]
1905 class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo,
1906 dag OOL, dag IOL, string asmstr,
1907 InstrItinClass itin, list<dag> pattern>
1908 : I<4, OOL, IOL, asmstr, itin> {
1913 let Pattern = pattern;
1915 let Inst{6-10} = VD;
1916 let Inst{11-15} = eo;
1917 let Inst{16-20} = VB;
1920 let Inst{23-31} = xo;
1923 // VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO]
1924 class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr,
1925 InstrItinClass itin, list<dag> pattern>
1926 : I<4, OOL, IOL, asmstr, itin> {
1932 let Pattern = pattern;
1934 let Inst{6-10} = VD;
1935 let Inst{11-15} = VA;
1936 let Inst{16-20} = VB;
1939 let Inst{23-31} = xo;
1942 // Z23-Form (used by QPX)
1943 class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1944 InstrItinClass itin, list<dag> pattern>
1945 : I<opcode, OOL, IOL, asmstr, itin> {
1951 let Pattern = pattern;
1953 bit RC = 0; // set by isDOT
1955 let Inst{6-10} = FRT;
1956 let Inst{11-15} = FRA;
1957 let Inst{16-20} = FRB;
1958 let Inst{21-22} = idx;
1959 let Inst{23-30} = xo;
1963 class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1964 InstrItinClass itin, list<dag> pattern>
1965 : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1969 class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1970 InstrItinClass itin, list<dag> pattern>
1971 : I<opcode, OOL, IOL, asmstr, itin> {
1975 let Pattern = pattern;
1977 bit RC = 0; // set by isDOT
1979 let Inst{6-10} = FRT;
1980 let Inst{11-22} = idx;
1981 let Inst{23-30} = xo;
1985 //===----------------------------------------------------------------------===//
1986 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1987 : I<0, OOL, IOL, asmstr, NoItinerary> {
1988 let isCodeGenOnly = 1;
1990 let Pattern = pattern;