1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
17 field bits<32> SoftFail = 0;
20 bit PPC64 = 0; // Default value, override with isPPC64
22 let Namespace = "PPC";
23 let Inst{0-5} = opcode;
24 let OutOperandList = OOL;
25 let InOperandList = IOL;
26 let AsmString = asmstr;
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
35 /// these must be reflected there! See comments there for what these are.
36 let TSFlags{0} = PPC970_First;
37 let TSFlags{1} = PPC970_Single;
38 let TSFlags{2} = PPC970_Cracked;
39 let TSFlags{5-3} = PPC970_Unit;
41 // Fields used for relation models.
44 // For cases where multiple instruction definitions really represent the
45 // same underlying instruction but with one definition for 64-bit arguments
46 // and one for 32-bit arguments, this bit breaks the degeneracy between
47 // the two forms and allows TableGen to generate mapping tables.
48 bit Interpretation64Bit = 0;
51 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
52 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
53 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
54 class PPC970_MicroCode;
56 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
57 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
58 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
59 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
60 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
61 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
62 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
63 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
65 // Two joined instructions; used to emit two adjacent instructions as one.
66 // The itinerary from the first instruction is used for scheduling and
68 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
72 field bits<64> SoftFail = 0;
75 bit PPC64 = 0; // Default value, override with isPPC64
77 let Namespace = "PPC";
78 let Inst{0-5} = opcode1;
79 let Inst{32-37} = opcode2;
80 let OutOperandList = OOL;
81 let InOperandList = IOL;
82 let AsmString = asmstr;
85 bits<1> PPC970_First = 0;
86 bits<1> PPC970_Single = 0;
87 bits<1> PPC970_Cracked = 0;
88 bits<3> PPC970_Unit = 0;
90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
91 /// these must be reflected there! See comments there for what these are.
92 let TSFlags{0} = PPC970_First;
93 let TSFlags{1} = PPC970_Single;
94 let TSFlags{2} = PPC970_Cracked;
95 let TSFlags{5-3} = PPC970_Unit;
97 // Fields used for relation models.
99 bit Interpretation64Bit = 0;
103 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
104 InstrItinClass itin, list<dag> pattern>
105 : I<opcode, OOL, IOL, asmstr, itin> {
106 let Pattern = pattern;
115 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
122 let BI{0-1} = BIBO{5-6};
123 let BI{2-4} = CR{0-2};
125 let Inst{6-10} = BIBO{4-0};
126 let Inst{11-15} = BI;
127 let Inst{16-29} = BD;
132 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
140 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
141 dag OOL, dag IOL, string asmstr>
142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
146 let Inst{11-15} = bi;
147 let Inst{16-29} = BD;
152 class BForm_3<bits<6> opcode, bit aa, bit lk,
153 dag OOL, dag IOL, string asmstr>
154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
160 let Inst{11-15} = BI;
161 let Inst{16-29} = BD;
166 class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
167 dag OOL, dag IOL, string asmstr>
168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
173 let Inst{11-15} = BI;
174 let Inst{16-29} = BD;
180 class SCForm<bits<6> opcode, bits<1> xo,
181 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
183 : I<opcode, OOL, IOL, asmstr, itin> {
186 let Pattern = pattern;
188 let Inst{20-26} = LEV;
193 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
194 InstrItinClass itin, list<dag> pattern>
195 : I<opcode, OOL, IOL, asmstr, itin> {
200 let Pattern = pattern;
207 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
208 InstrItinClass itin, list<dag> pattern>
209 : I<opcode, OOL, IOL, asmstr, itin> {
213 let Pattern = pattern;
216 let Inst{11-15} = Addr{20-16}; // Base Reg
217 let Inst{16-31} = Addr{15-0}; // Displacement
220 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
221 InstrItinClass itin, list<dag> pattern>
222 : I<opcode, OOL, IOL, asmstr, itin> {
227 let Pattern = pattern;
235 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
236 InstrItinClass itin, list<dag> pattern>
237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
239 // Even though ADDICo does not really have an RC bit, provide
240 // the declaration of one here so that isDOT has something to set.
244 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
245 InstrItinClass itin, list<dag> pattern>
246 : I<opcode, OOL, IOL, asmstr, itin> {
250 let Pattern = pattern;
257 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
258 InstrItinClass itin, list<dag> pattern>
259 : I<opcode, OOL, IOL, asmstr, itin> {
264 let Pattern = pattern;
271 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
272 InstrItinClass itin, list<dag> pattern>
273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
278 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
279 string asmstr, InstrItinClass itin,
281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
287 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
288 dag OOL, dag IOL, string asmstr,
289 InstrItinClass itin, list<dag> pattern>
290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
294 let Pattern = pattern;
302 let Inst{43-47} = Addr{20-16}; // Base Reg
303 let Inst{48-63} = Addr{15-0}; // Displacement
306 // This is used to emit BL8+NOP.
307 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
308 dag OOL, dag IOL, string asmstr,
309 InstrItinClass itin, list<dag> pattern>
310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
311 OOL, IOL, asmstr, itin, pattern> {
316 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
318 : I<opcode, OOL, IOL, asmstr, itin> {
327 let Inst{11-15} = RA;
331 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
333 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
337 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
339 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
341 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
343 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
349 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
350 InstrItinClass itin, list<dag> pattern>
351 : I<opcode, OOL, IOL, asmstr, itin> {
355 let Pattern = pattern;
357 let Inst{6-10} = RST;
358 let Inst{11-15} = DS_RA{18-14}; // Register #
359 let Inst{16-29} = DS_RA{13-0}; // Displacement.
360 let Inst{30-31} = xo;
363 // DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO]
364 class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
365 string asmstr, InstrItinClass itin, list<dag> pattern>
366 : I<opcode, OOL, IOL, asmstr, itin> {
370 let Pattern = pattern;
372 let Inst{6-10} = XT{4-0};
373 let Inst{11-15} = DS_RA{16-12}; // Register #
374 let Inst{16-27} = DS_RA{11-0}; // Displacement.
375 let Inst{28} = XT{5};
376 let Inst{29-31} = xo;
380 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
381 InstrItinClass itin, list<dag> pattern>
382 : I<opcode, OOL, IOL, asmstr, itin> {
387 let Pattern = pattern;
389 bit RC = 0; // set by isDOT
391 let Inst{6-10} = RST;
394 let Inst{21-30} = xo;
398 class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr,
399 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> {
403 class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
405 : I<opcode, OOL, IOL, asmstr, itin> {
406 let Inst{21-30} = xo;
409 // This is the same as XForm_base_r3xo, but the first two operands are swapped
410 // when code is emitted.
411 class XForm_base_r3xo_swapped
412 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
414 : I<opcode, OOL, IOL, asmstr, itin> {
419 bit RC = 0; // set by isDOT
421 let Inst{6-10} = RST;
424 let Inst{21-30} = xo;
429 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
430 InstrItinClass itin, list<dag> pattern>
431 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
433 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
434 InstrItinClass itin, list<dag> pattern>
435 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
439 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
440 InstrItinClass itin, list<dag> pattern>
441 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
446 class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
447 InstrItinClass itin, list<dag> pattern>
448 : I<opcode, OOL, IOL, asmstr, itin> {
453 let Pattern = pattern;
455 let Inst{6-10} = RST;
458 let Inst{21-30} = xo;
462 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
463 InstrItinClass itin, list<dag> pattern>
464 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
465 let Pattern = pattern;
468 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
469 InstrItinClass itin, list<dag> pattern>
470 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
472 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
473 InstrItinClass itin, list<dag> pattern>
474 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
475 let Pattern = pattern;
478 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
479 InstrItinClass itin, list<dag> pattern>
480 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
482 let Pattern = pattern;
485 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
487 : I<opcode, OOL, IOL, asmstr, itin> {
496 let Inst{11-15} = RA;
497 let Inst{16-20} = RB;
498 let Inst{21-30} = xo;
502 class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
504 : I<opcode, OOL, IOL, asmstr, itin> {
511 let Inst{11-15} = RA;
512 let Inst{16-20} = RB;
513 let Inst{21-30} = xo;
517 class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
519 : I<opcode, OOL, IOL, asmstr, itin> {
524 let Inst{12-15} = SR;
525 let Inst{21-30} = xo;
528 class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
530 : I<opcode, OOL, IOL, asmstr, itin> {
534 let Inst{21-30} = xo;
537 class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
539 : I<opcode, OOL, IOL, asmstr, itin> {
544 let Inst{16-20} = RB;
545 let Inst{21-30} = xo;
548 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
550 : I<opcode, OOL, IOL, asmstr, itin> {
556 let Inst{21-30} = xo;
559 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
561 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
565 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
567 : I<opcode, OOL, IOL, asmstr, itin> {
574 let Inst{11-15} = FRA;
575 let Inst{16-20} = FRB;
576 let Inst{21-30} = xo;
581 class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
582 InstrItinClass itin, list<dag> pattern>
583 : I<opcode, OOL, IOL, asmstr, itin> {
588 let Pattern = pattern;
590 let Inst{6-10} = FRT;
591 let Inst{11-15} = FRA;
592 let Inst{16-20} = FRB;
593 let Inst{21-30} = xo;
597 class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
598 InstrItinClass itin, list<dag> pattern>
599 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
603 class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr,
604 InstrItinClass itin, list<dag> pattern>
605 : I<opcode, OOL, IOL, asmstr, itin> {
611 let Pattern = pattern;
613 let Inst{6-10} = FRT;
614 let Inst{11-15} = FRA;
615 let Inst{16-20} = FRB;
616 let Inst{21-24} = tttt;
617 let Inst{25-30} = xo;
621 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
622 InstrItinClass itin, list<dag> pattern>
623 : I<opcode, OOL, IOL, asmstr, itin> {
624 let Pattern = pattern;
628 let Inst{21-30} = xo;
632 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
633 string asmstr, InstrItinClass itin, list<dag> pattern>
634 : I<opcode, OOL, IOL, asmstr, itin> {
637 let Pattern = pattern;
642 let Inst{21-30} = xo;
646 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
647 string asmstr, InstrItinClass itin, list<dag> pattern>
648 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
652 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
653 InstrItinClass itin, list<dag> pattern>
654 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
657 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
658 InstrItinClass itin, list<dag> pattern>
659 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
663 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
664 InstrItinClass itin, list<dag> pattern>
665 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
668 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
669 // numbers presumably relates to some document, but I haven't found it.
670 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
671 InstrItinClass itin, list<dag> pattern>
672 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
673 let Pattern = pattern;
675 bit RC = 0; // set by isDOT
677 let Inst{6-10} = RST;
679 let Inst{21-30} = xo;
682 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
683 InstrItinClass itin, list<dag> pattern>
684 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
685 let Pattern = pattern;
688 bit RC = 0; // set by isDOT
692 let Inst{21-30} = xo;
696 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
697 InstrItinClass itin, list<dag> pattern>
698 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
704 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
705 InstrItinClass itin, list<dag> pattern>
706 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
711 class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
712 string asmstr, InstrItinClass itin, list<dag> pattern>
713 : I<opcode, OOL, IOL, asmstr, itin> {
721 let Inst{21-30} = xo;
725 class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
726 string asmstr, InstrItinClass itin, list<dag> pattern>
727 : I<opcode, OOL, IOL, asmstr, itin> {
734 let Inst{21-30} = xo;
738 class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
739 InstrItinClass itin, list<dag> pattern>
740 : I<opcode, OOL, IOL, asmstr, itin> {
743 bit RC = 0; // set by isDOT
748 let Inst{21-30} = xo;
752 class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
753 InstrItinClass itin, list<dag> pattern>
754 : I<opcode, OOL, IOL, asmstr, itin> {
761 let Inst{21-30} = xo;
765 // [PO RT RA RB XO /]
766 class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
767 string asmstr, InstrItinClass itin, list<dag> pattern>
768 : I<opcode, OOL, IOL, asmstr, itin> {
774 let Pattern = pattern;
779 let Inst{11-15} = RA;
780 let Inst{16-20} = RB;
781 let Inst{21-30} = xo;
785 // Same as XForm_17 but with GPR's and new naming convention
786 class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
787 string asmstr, InstrItinClass itin, list<dag> pattern>
788 : I<opcode, OOL, IOL, asmstr, itin> {
793 let Pattern = pattern;
797 let Inst{11-15} = RA;
798 let Inst{16-20} = RB;
799 let Inst{21-30} = xo;
803 // e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO]
804 class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
805 string asmstr, InstrItinClass itin, list<dag> pattern>
806 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
810 class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
811 string asmstr, InstrItinClass itin, list<dag> pattern>
812 : I<opcode, OOL, IOL, asmstr, itin> {
817 let Pattern = pattern;
820 let Inst{9-15} = DCMX;
821 let Inst{16-20} = VB;
822 let Inst{21-30} = xo;
826 class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
827 string asmstr, InstrItinClass itin, list<dag> pattern>
828 : I<opcode, OOL, IOL, asmstr, itin> {
832 let Pattern = pattern;
834 let Inst{6-10} = XT{4-0};
836 let Inst{13-20} = IMM8;
837 let Inst{21-30} = xo;
838 let Inst{31} = XT{5};
841 // XForm_base_r3xo for instructions such as P9 atomics where we don't want
842 // to specify an SDAG pattern for matching.
843 class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
844 string asmstr, InstrItinClass itin>
845 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, []> {
848 class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
850 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> {
855 // [PO /// L RA RB XO /]
856 class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
857 string asmstr, InstrItinClass itin, list<dag> pattern>
858 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
860 let Pattern = pattern;
867 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
868 InstrItinClass itin, list<dag> pattern>
869 : I<opcode, OOL, IOL, asmstr, itin> {
874 let Pattern = pattern;
876 let Inst{6-10} = XT{4-0};
879 let Inst{21-30} = xo;
880 let Inst{31} = XT{5};
883 class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
884 string asmstr, InstrItinClass itin, list<dag> pattern>
885 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
889 class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
890 InstrItinClass itin, list<dag> pattern>
891 : I<opcode, OOL, IOL, asmstr, itin> {
895 let Pattern = pattern;
897 let Inst{6-10} = XT{4-0};
899 let Inst{16-20} = XB{4-0};
900 let Inst{21-29} = xo;
901 let Inst{30} = XB{5};
902 let Inst{31} = XT{5};
905 class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
906 InstrItinClass itin, list<dag> pattern>
907 : I<opcode, OOL, IOL, asmstr, itin> {
911 let Pattern = pattern;
915 let Inst{16-20} = XB{4-0};
916 let Inst{21-29} = xo;
917 let Inst{30} = XB{5};
921 class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
922 InstrItinClass itin, list<dag> pattern>
923 : I<opcode, OOL, IOL, asmstr, itin> {
928 let Pattern = pattern;
930 let Inst{6-10} = XT{4-0};
933 let Inst{16-20} = XB{4-0};
934 let Inst{21-29} = xo;
935 let Inst{30} = XB{5};
936 let Inst{31} = XT{5};
939 class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
940 string asmstr, InstrItinClass itin, list<dag> pattern>
941 : I<opcode, OOL, IOL, asmstr, itin> {
946 let Pattern = pattern;
948 let Inst{6-10} = XT{4-0};
949 let Inst{11-15} = UIM5;
950 let Inst{16-20} = XB{4-0};
951 let Inst{21-29} = xo;
952 let Inst{30} = XB{5};
953 let Inst{31} = XT{5};
956 // [PO T XO B XO BX /]
957 class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
958 string asmstr, InstrItinClass itin, list<dag> pattern>
959 : I<opcode, OOL, IOL, asmstr, itin> {
963 let Pattern = pattern;
966 let Inst{11-15} = xo2;
967 let Inst{16-20} = XB{4-0};
968 let Inst{21-29} = xo;
969 let Inst{30} = XB{5};
973 // [PO T XO B XO BX TX]
974 class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
975 string asmstr, InstrItinClass itin, list<dag> pattern>
976 : I<opcode, OOL, IOL, asmstr, itin> {
980 let Pattern = pattern;
982 let Inst{6-10} = XT{4-0};
983 let Inst{11-15} = xo2;
984 let Inst{16-20} = XB{4-0};
985 let Inst{21-29} = xo;
986 let Inst{30} = XB{5};
987 let Inst{31} = XT{5};
990 class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
991 string asmstr, InstrItinClass itin, list<dag> pattern>
992 : I<opcode, OOL, IOL, asmstr, itin> {
997 let Pattern = pattern;
1000 let Inst{9-15} = DCMX;
1001 let Inst{16-20} = XB{4-0};
1002 let Inst{21-29} = xo;
1003 let Inst{30} = XB{5};
1007 class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2,
1008 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
1010 : I<opcode, OOL, IOL, asmstr, itin> {
1015 let Pattern = pattern;
1017 let Inst{6-10} = XT{4-0};
1018 let Inst{11-15} = DCMX{4-0};
1019 let Inst{16-20} = XB{4-0};
1020 let Inst{21-24} = xo1;
1021 let Inst{25} = DCMX{5};
1022 let Inst{26-28} = xo2;
1023 let Inst{29} = DCMX{6};
1024 let Inst{30} = XB{5};
1025 let Inst{31} = XT{5};
1028 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1029 InstrItinClass itin, list<dag> pattern>
1030 : I<opcode, OOL, IOL, asmstr, itin> {
1035 let Pattern = pattern;
1037 let Inst{6-10} = XT{4-0};
1038 let Inst{11-15} = XA{4-0};
1039 let Inst{16-20} = XB{4-0};
1040 let Inst{21-28} = xo;
1041 let Inst{29} = XA{5};
1042 let Inst{30} = XB{5};
1043 let Inst{31} = XT{5};
1046 class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1047 InstrItinClass itin, list<dag> pattern>
1048 : I<opcode, OOL, IOL, asmstr, itin> {
1053 let Pattern = pattern;
1057 let Inst{11-15} = XA{4-0};
1058 let Inst{16-20} = XB{4-0};
1059 let Inst{21-28} = xo;
1060 let Inst{29} = XA{5};
1061 let Inst{30} = XB{5};
1065 class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1066 InstrItinClass itin, list<dag> pattern>
1067 : I<opcode, OOL, IOL, asmstr, itin> {
1073 let Pattern = pattern;
1075 let Inst{6-10} = XT{4-0};
1076 let Inst{11-15} = XA{4-0};
1077 let Inst{16-20} = XB{4-0};
1079 let Inst{22-23} = D;
1080 let Inst{24-28} = xo;
1081 let Inst{29} = XA{5};
1082 let Inst{30} = XB{5};
1083 let Inst{31} = XT{5};
1086 class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr,
1087 InstrItinClass itin, list<dag> pattern>
1088 : I<opcode, OOL, IOL, asmstr, itin> {
1093 let Pattern = pattern;
1095 bit RC = 0; // set by isDOT
1097 let Inst{6-10} = XT{4-0};
1098 let Inst{11-15} = XA{4-0};
1099 let Inst{16-20} = XB{4-0};
1101 let Inst{22-28} = xo;
1102 let Inst{29} = XA{5};
1103 let Inst{30} = XB{5};
1104 let Inst{31} = XT{5};
1107 class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
1108 InstrItinClass itin, list<dag> pattern>
1109 : I<opcode, OOL, IOL, asmstr, itin> {
1115 let Pattern = pattern;
1117 let Inst{6-10} = XT{4-0};
1118 let Inst{11-15} = XA{4-0};
1119 let Inst{16-20} = XB{4-0};
1120 let Inst{21-25} = XC{4-0};
1121 let Inst{26-27} = xo;
1122 let Inst{28} = XC{5};
1123 let Inst{29} = XA{5};
1124 let Inst{30} = XB{5};
1125 let Inst{31} = XT{5};
1128 // DCB_Form - Form X instruction, used for dcb* instructions.
1129 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
1130 InstrItinClass itin, list<dag> pattern>
1131 : I<31, OOL, IOL, asmstr, itin> {
1135 let Pattern = pattern;
1137 let Inst{6-10} = immfield;
1138 let Inst{11-15} = A;
1139 let Inst{16-20} = B;
1140 let Inst{21-30} = xo;
1144 class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr,
1145 InstrItinClass itin, list<dag> pattern>
1146 : I<31, OOL, IOL, asmstr, itin> {
1151 let Pattern = pattern;
1153 let Inst{6-10} = TH;
1154 let Inst{11-15} = A;
1155 let Inst{16-20} = B;
1156 let Inst{21-30} = xo;
1160 // DSS_Form - Form X instruction, used for altivec dss* instructions.
1161 class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr,
1162 InstrItinClass itin, list<dag> pattern>
1163 : I<31, OOL, IOL, asmstr, itin> {
1168 let Pattern = pattern;
1172 let Inst{9-10} = STRM;
1173 let Inst{11-15} = A;
1174 let Inst{16-20} = B;
1175 let Inst{21-30} = xo;
1180 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1181 InstrItinClass itin, list<dag> pattern>
1182 : I<opcode, OOL, IOL, asmstr, itin> {
1187 let Pattern = pattern;
1189 let Inst{6-10} = CRD;
1190 let Inst{11-15} = CRA;
1191 let Inst{16-20} = CRB;
1192 let Inst{21-30} = xo;
1196 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1197 InstrItinClass itin, list<dag> pattern>
1198 : I<opcode, OOL, IOL, asmstr, itin> {
1201 let Pattern = pattern;
1203 let Inst{6-10} = CRD;
1204 let Inst{11-15} = CRD;
1205 let Inst{16-20} = CRD;
1206 let Inst{21-30} = xo;
1210 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
1211 InstrItinClass itin, list<dag> pattern>
1212 : I<opcode, OOL, IOL, asmstr, itin> {
1217 let Pattern = pattern;
1219 let Inst{6-10} = BO;
1220 let Inst{11-15} = BI;
1221 let Inst{16-18} = 0;
1222 let Inst{19-20} = BH;
1223 let Inst{21-30} = xo;
1227 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
1228 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1229 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1230 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
1234 let BI{0-1} = BIBO{5-6};
1235 let BI{2-4} = CR{0-2};
1239 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
1240 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1241 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1246 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
1247 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1248 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
1254 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1255 InstrItinClass itin>
1256 : I<opcode, OOL, IOL, asmstr, itin> {
1262 let Inst{11-13} = BFA;
1263 let Inst{14-15} = 0;
1264 let Inst{16-20} = 0;
1265 let Inst{21-30} = xo;
1269 class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1270 InstrItinClass itin>
1271 : I<opcode, OOL, IOL, asmstr, itin> {
1280 let Inst{11-14} = 0;
1282 let Inst{16-19} = U;
1284 let Inst{21-30} = xo;
1288 class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1289 InstrItinClass itin, list<dag> pattern>
1290 : I<opcode, OOL, IOL, asmstr, itin> {
1293 let Pattern = pattern;
1297 let Inst{21-30} = xo;
1301 class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
1302 bits<6> opcode2, bits<2> xo2,
1303 dag OOL, dag IOL, string asmstr,
1304 InstrItinClass itin, list<dag> pattern>
1305 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
1313 let Pattern = pattern;
1315 let Inst{6-10} = BO;
1316 let Inst{11-15} = BI;
1317 let Inst{16-18} = 0;
1318 let Inst{19-20} = BH;
1319 let Inst{21-30} = xo1;
1322 let Inst{38-42} = RST;
1323 let Inst{43-47} = DS_RA{18-14}; // Register #
1324 let Inst{48-61} = DS_RA{13-0}; // Displacement.
1325 let Inst{62-63} = xo2;
1328 class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
1329 bits<5> bo, bits<5> bi, bit lk,
1330 bits<6> opcode2, bits<2> xo2,
1331 dag OOL, dag IOL, string asmstr,
1332 InstrItinClass itin, list<dag> pattern>
1333 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2,
1334 OOL, IOL, asmstr, itin, pattern> {
1341 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1342 InstrItinClass itin>
1343 : I<opcode, OOL, IOL, asmstr, itin> {
1347 let Inst{6-10} = RT;
1348 let Inst{11} = SPR{4};
1349 let Inst{12} = SPR{3};
1350 let Inst{13} = SPR{2};
1351 let Inst{14} = SPR{1};
1352 let Inst{15} = SPR{0};
1353 let Inst{16} = SPR{9};
1354 let Inst{17} = SPR{8};
1355 let Inst{18} = SPR{7};
1356 let Inst{19} = SPR{6};
1357 let Inst{20} = SPR{5};
1358 let Inst{21-30} = xo;
1362 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1363 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1364 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
1368 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1369 InstrItinClass itin>
1370 : I<opcode, OOL, IOL, asmstr, itin> {
1373 let Inst{6-10} = RT;
1374 let Inst{11-20} = 0;
1375 let Inst{21-30} = xo;
1379 class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1380 InstrItinClass itin, list<dag> pattern>
1381 : I<opcode, OOL, IOL, asmstr, itin> {
1384 let Pattern = pattern;
1386 let Inst{6-10} = RT;
1387 let Inst{11-20} = Entry;
1388 let Inst{21-30} = xo;
1392 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1393 InstrItinClass itin>
1394 : I<opcode, OOL, IOL, asmstr, itin> {
1398 let Inst{6-10} = rS;
1400 let Inst{12-19} = FXM;
1402 let Inst{21-30} = xo;
1406 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1407 InstrItinClass itin>
1408 : I<opcode, OOL, IOL, asmstr, itin> {
1412 let Inst{6-10} = ST;
1414 let Inst{12-19} = FXM;
1416 let Inst{21-30} = xo;
1420 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1421 InstrItinClass itin>
1422 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
1424 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1425 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
1426 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
1431 // This is probably 1.7.9, but I don't have the reference that uses this
1432 // numbering scheme...
1433 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1434 InstrItinClass itin, list<dag>pattern>
1435 : I<opcode, OOL, IOL, asmstr, itin> {
1439 bit RC = 0; // set by isDOT
1440 let Pattern = pattern;
1443 let Inst{7-14} = FM;
1445 let Inst{16-20} = rT;
1446 let Inst{21-30} = xo;
1450 class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1451 InstrItinClass itin, list<dag>pattern>
1452 : I<opcode, OOL, IOL, asmstr, itin> {
1458 bit RC = 0; // set by isDOT
1459 let Pattern = pattern;
1462 let Inst{7-14} = FLM;
1464 let Inst{16-20} = FRB;
1465 let Inst{21-30} = xo;
1469 // 1.7.10 XS-Form - SRADI.
1470 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1471 InstrItinClass itin, list<dag> pattern>
1472 : I<opcode, OOL, IOL, asmstr, itin> {
1477 bit RC = 0; // set by isDOT
1478 let Pattern = pattern;
1480 let Inst{6-10} = RS;
1481 let Inst{11-15} = A;
1482 let Inst{16-20} = SH{4,3,2,1,0};
1483 let Inst{21-29} = xo;
1484 let Inst{30} = SH{5};
1489 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
1490 InstrItinClass itin, list<dag> pattern>
1491 : I<opcode, OOL, IOL, asmstr, itin> {
1496 let Pattern = pattern;
1498 bit RC = 0; // set by isDOT
1500 let Inst{6-10} = RT;
1501 let Inst{11-15} = RA;
1502 let Inst{16-20} = RB;
1504 let Inst{22-30} = xo;
1508 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
1509 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1510 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
1515 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1516 InstrItinClass itin, list<dag> pattern>
1517 : I<opcode, OOL, IOL, asmstr, itin> {
1523 let Pattern = pattern;
1525 bit RC = 0; // set by isDOT
1527 let Inst{6-10} = FRT;
1528 let Inst{11-15} = FRA;
1529 let Inst{16-20} = FRB;
1530 let Inst{21-25} = FRC;
1531 let Inst{26-30} = xo;
1535 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1536 InstrItinClass itin, list<dag> pattern>
1537 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1541 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1542 InstrItinClass itin, list<dag> pattern>
1543 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1547 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1548 InstrItinClass itin, list<dag> pattern>
1549 : I<opcode, OOL, IOL, asmstr, itin> {
1555 let Pattern = pattern;
1557 let Inst{6-10} = RT;
1558 let Inst{11-15} = RA;
1559 let Inst{16-20} = RB;
1560 let Inst{21-25} = COND;
1561 let Inst{26-30} = xo;
1566 class AForm_4a<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1567 InstrItinClass itin, list<dag> pattern>
1568 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1574 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1575 InstrItinClass itin, list<dag> pattern>
1576 : I<opcode, OOL, IOL, asmstr, itin> {
1583 let Pattern = pattern;
1585 bit RC = 0; // set by isDOT
1587 let Inst{6-10} = RS;
1588 let Inst{11-15} = RA;
1589 let Inst{16-20} = RB;
1590 let Inst{21-25} = MB;
1591 let Inst{26-30} = ME;
1595 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1596 InstrItinClass itin, list<dag> pattern>
1597 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
1601 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
1602 InstrItinClass itin, list<dag> pattern>
1603 : I<opcode, OOL, IOL, asmstr, itin> {
1609 let Pattern = pattern;
1611 bit RC = 0; // set by isDOT
1613 let Inst{6-10} = RS;
1614 let Inst{11-15} = RA;
1615 let Inst{16-20} = SH{4,3,2,1,0};
1616 let Inst{21-26} = MBE{4,3,2,1,0,5};
1617 let Inst{27-29} = xo;
1618 let Inst{30} = SH{5};
1622 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
1623 InstrItinClass itin, list<dag> pattern>
1624 : I<opcode, OOL, IOL, asmstr, itin> {
1630 let Pattern = pattern;
1632 bit RC = 0; // set by isDOT
1634 let Inst{6-10} = RS;
1635 let Inst{11-15} = RA;
1636 let Inst{16-20} = RB;
1637 let Inst{21-26} = MBE{4,3,2,1,0,5};
1638 let Inst{27-30} = xo;
1645 // VAForm_1 - DACB ordering.
1646 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
1647 InstrItinClass itin, list<dag> pattern>
1648 : I<4, OOL, IOL, asmstr, itin> {
1654 let Pattern = pattern;
1656 let Inst{6-10} = VD;
1657 let Inst{11-15} = VA;
1658 let Inst{16-20} = VB;
1659 let Inst{21-25} = VC;
1660 let Inst{26-31} = xo;
1663 // VAForm_1a - DABC ordering.
1664 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
1665 InstrItinClass itin, list<dag> pattern>
1666 : I<4, OOL, IOL, asmstr, itin> {
1672 let Pattern = pattern;
1674 let Inst{6-10} = VD;
1675 let Inst{11-15} = VA;
1676 let Inst{16-20} = VB;
1677 let Inst{21-25} = VC;
1678 let Inst{26-31} = xo;
1681 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1682 InstrItinClass itin, list<dag> pattern>
1683 : I<4, OOL, IOL, asmstr, itin> {
1689 let Pattern = pattern;
1691 let Inst{6-10} = VD;
1692 let Inst{11-15} = VA;
1693 let Inst{16-20} = VB;
1695 let Inst{22-25} = SH;
1696 let Inst{26-31} = xo;
1700 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1701 InstrItinClass itin, list<dag> pattern>
1702 : I<4, OOL, IOL, asmstr, itin> {
1707 let Pattern = pattern;
1709 let Inst{6-10} = VD;
1710 let Inst{11-15} = VA;
1711 let Inst{16-20} = VB;
1712 let Inst{21-31} = xo;
1715 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1716 InstrItinClass itin, list<dag> pattern>
1717 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1723 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1724 InstrItinClass itin, list<dag> pattern>
1725 : I<4, OOL, IOL, asmstr, itin> {
1729 let Pattern = pattern;
1731 let Inst{6-10} = VD;
1732 let Inst{11-15} = 0;
1733 let Inst{16-20} = VB;
1734 let Inst{21-31} = xo;
1737 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1738 InstrItinClass itin, list<dag> pattern>
1739 : I<4, OOL, IOL, asmstr, itin> {
1743 let Pattern = pattern;
1745 let Inst{6-10} = VD;
1746 let Inst{11-15} = IMM;
1747 let Inst{16-20} = 0;
1748 let Inst{21-31} = xo;
1751 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1752 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1753 InstrItinClass itin, list<dag> pattern>
1754 : I<4, OOL, IOL, asmstr, itin> {
1757 let Pattern = pattern;
1759 let Inst{6-10} = VD;
1760 let Inst{11-15} = 0;
1761 let Inst{16-20} = 0;
1762 let Inst{21-31} = xo;
1765 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1766 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1767 InstrItinClass itin, list<dag> pattern>
1768 : I<4, OOL, IOL, asmstr, itin> {
1771 let Pattern = pattern;
1774 let Inst{11-15} = 0;
1775 let Inst{16-20} = VB;
1776 let Inst{21-31} = xo;
1779 // e.g. [PO VRT EO VRB XO]
1780 class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL,
1781 string asmstr, InstrItinClass itin, list<dag> pattern>
1782 : I<4, OOL, IOL, asmstr, itin> {
1786 let Pattern = pattern;
1788 let Inst{6-10} = RD;
1789 let Inst{11-15} = eo;
1790 let Inst{16-20} = VB;
1791 let Inst{21-31} = xo;
1794 /// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX"
1795 class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr,
1796 InstrItinClass itin, list<dag> pattern>
1797 : I<4, OOL, IOL, asmstr, itin> {
1803 let Pattern = pattern;
1805 let Inst{6-10} = VD;
1806 let Inst{11-15} = VA;
1808 let Inst{17-20} = SIX;
1809 let Inst{21-31} = xo;
1812 /// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox"
1813 class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr,
1814 InstrItinClass itin, list<dag> pattern>
1815 : I<4, OOL, IOL, asmstr, itin> {
1819 let Pattern = pattern;
1821 let Inst{6-10} = VD;
1822 let Inst{11-15} = VA;
1823 let Inst{16-20} = 0;
1824 let Inst{21-31} = xo;
1828 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1829 InstrItinClass itin, list<dag> pattern>
1830 : I<4, OOL, IOL, asmstr, itin> {
1836 let Pattern = pattern;
1838 let Inst{6-10} = VD;
1839 let Inst{11-15} = VA;
1840 let Inst{16-20} = VB;
1842 let Inst{22-31} = xo;
1845 // VX-Form: [PO VRT EO VRB 1 PS XO]
1846 class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo,
1847 dag OOL, dag IOL, string asmstr,
1848 InstrItinClass itin, list<dag> pattern>
1849 : I<4, OOL, IOL, asmstr, itin> {
1854 let Pattern = pattern;
1856 let Inst{6-10} = VD;
1857 let Inst{11-15} = eo;
1858 let Inst{16-20} = VB;
1861 let Inst{23-31} = xo;
1864 // VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO]
1865 class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr,
1866 InstrItinClass itin, list<dag> pattern>
1867 : I<4, OOL, IOL, asmstr, itin> {
1873 let Pattern = pattern;
1875 let Inst{6-10} = VD;
1876 let Inst{11-15} = VA;
1877 let Inst{16-20} = VB;
1880 let Inst{23-31} = xo;
1883 // Z23-Form (used by QPX)
1884 class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1885 InstrItinClass itin, list<dag> pattern>
1886 : I<opcode, OOL, IOL, asmstr, itin> {
1892 let Pattern = pattern;
1894 bit RC = 0; // set by isDOT
1896 let Inst{6-10} = FRT;
1897 let Inst{11-15} = FRA;
1898 let Inst{16-20} = FRB;
1899 let Inst{21-22} = idx;
1900 let Inst{23-30} = xo;
1904 class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1905 InstrItinClass itin, list<dag> pattern>
1906 : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1910 class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
1911 InstrItinClass itin, list<dag> pattern>
1912 : I<opcode, OOL, IOL, asmstr, itin> {
1916 let Pattern = pattern;
1918 bit RC = 0; // set by isDOT
1920 let Inst{6-10} = FRT;
1921 let Inst{11-22} = idx;
1922 let Inst{23-30} = xo;
1926 //===----------------------------------------------------------------------===//
1927 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1928 : I<0, OOL, IOL, asmstr, NoItinerary> {
1929 let isCodeGenOnly = 1;
1931 let Pattern = pattern;