lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureX87     : SubtargetFeature<"x87","HasX87", "true",
  35                                       "Enable X87 float instructions">;
  36
  37 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  38                                       "Enable conditional move instructions">;
  39
  40 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  41                                        "Support POPCNT instruction">;
  42
  43 def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
  44                                       "Support fxsave/fxrestore instructions">;
  45
  46 def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
  47                                        "Support xsave instructions">;
  48
  49 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
  50                                        "Support xsaveopt instructions">;
  51
  52 def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
  53                                        "Support xsavec instructions">;
  54
  55 def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
  56                                        "Support xsaves instructions">;
  57
  58 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  59                                       "Enable SSE instructions",
  60                                       // SSE codegen depends on cmovs, and all
  61                                       // SSE1+ processors support them.
  62                                       [FeatureCMOV]>;
  63 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  64                                       "Enable SSE2 instructions",
  65                                       [FeatureSSE1]>;
  66 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  67                                       "Enable SSE3 instructions",
  68                                       [FeatureSSE2]>;
  69 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  70                                       "Enable SSSE3 instructions",
  71                                       [FeatureSSE3]>;
  72 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  73                                       "Enable SSE 4.1 instructions",
  74                                       [FeatureSSSE3]>;
  75 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  76                                       "Enable SSE 4.2 instructions",
  77                                       [FeatureSSE41]>;
  78 // The MMX subtarget feature is separate from the rest of the SSE features
  79 // because it's important (for odd compatibility reasons) to be able to
  80 // turn it off explicitly while allowing SSE+ to be on.
  81 def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
  82                                       "Enable MMX instructions">;
  83 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  84                                       "Enable 3DNow! instructions",
  85                                       [FeatureMMX]>;
  86 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  87                                       "Enable 3DNow! Athlon instructions",
  88                                       [Feature3DNow]>;
  89 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  90 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  91 // without disabling 64-bit mode.
  92 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  93                                       "Support 64-bit instructions",
  94                                       [FeatureCMOV]>;
  95 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  96                                       "64-bit with cmpxchg16b",
  97                                       [Feature64Bit]>;
  98 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  99                                        "Bit testing of memory is slow">;
 100 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
 101                                        "SHLD instruction is slow">;
 102 def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
 103                                         "PMULLD instruction is slow">;
 104 // FIXME: This should not apply to CPUs that do not have SSE.
 105 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
 106                                 "IsUAMem16Slow", "true",
 107                                 "Slow unaligned 16-byte memory access">;
 108 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
 109                                 "IsUAMem32Slow", "true",
 110                                 "Slow unaligned 32-byte memory access">;
 111 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
 112                                       "Support SSE 4a instructions",
 113                                       [FeatureSSE3]>;
 114
 115 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
 116                                       "Enable AVX instructions",
 117                                       [FeatureSSE42]>;
 118 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 119                                       "Enable AVX2 instructions",
 120                                       [FeatureAVX]>;
 121 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 122                                       "Enable AVX-512 instructions",
 123                                       [FeatureAVX2]>;
 124 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 125                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 126                                       [FeatureAVX512]>;
 127 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 128                       "Enable AVX-512 Conflict Detection Instructions",
 129                                       [FeatureAVX512]>;
 130 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 131                       "Enable AVX-512 PreFetch Instructions",
 132                                       [FeatureAVX512]>;
 133 def FeaturePREFETCHWT1  : SubtargetFeature<"prefetchwt1", "HasPFPREFETCHWT1",
 134                                    "true",
 135                                    "Prefetch with Intent to Write and T1 Hint">;
 136 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 137                       "Enable AVX-512 Doubleword and Quadword Instructions",
 138                                       [FeatureAVX512]>;
 139 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 140                       "Enable AVX-512 Byte and Word Instructions",
 141                                       [FeatureAVX512]>;
 142 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 143                       "Enable AVX-512 Vector Length eXtensions",
 144                                       [FeatureAVX512]>;
 145 def FeatureVBMI     : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
 146                       "Enable AVX-512 Vector Byte Manipulation Instructions",
 147                                       [FeatureBWI]>;
 148 def FeatureIFMA     : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
 149                       "Enable AVX-512 Integer Fused Multiple-Add",
 150                                       [FeatureAVX512]>;
 151 def FeaturePKU   : SubtargetFeature<"pku", "HasPKU", "true",
 152                       "Enable protection keys">;
 153 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 154                          "Enable packed carry-less multiplication instructions",
 155                                [FeatureSSE2]>;
 156 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 157                                       "Enable three-operand fused multiple-add",
 158                                       [FeatureAVX]>;
 159 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 160                                       "Enable four-operand fused multiple-add",
 161                                       [FeatureAVX, FeatureSSE4A]>;
 162 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 163                                       "Enable XOP instructions",
 164                                       [FeatureFMA4]>;
 165 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 166                                           "HasSSEUnalignedMem", "true",
 167                       "Allow unaligned memory operands with SSE instructions">;
 168 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 169                                       "Enable AES instructions",
 170                                       [FeatureSSE2]>;
 171 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 172                                       "Enable TBM instructions">;
 173 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 174                                       "Support MOVBE instruction">;
 175 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 176                                       "Support RDRAND instruction">;
 177 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 178                        "Support 16-bit floating point conversion instructions",
 179                        [FeatureAVX]>;
 180 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 181                                        "Support FS/GS Base instructions">;
 182 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 183                                       "Support LZCNT instruction">;
 184 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 185                                       "Support BMI instructions">;
 186 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 187                                       "Support BMI2 instructions">;
 188 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 189                                       "Support RTM instructions">;
 190 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 191                                       "Support HLE">;
 192 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 193                                       "Support ADX instructions">;
 194 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 195                                       "Enable SHA instructions",
 196                                       [FeatureSSE2]>;
 197 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 198                                       "Support PRFCHW instructions">;
 199 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 200                                       "Support RDSEED instruction">;
 201 def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
 202                                        "Support LAHF and SAHF instructions">;
 203 def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
 204                                       "Enable MONITORX/MWAITX timer functionality">;
 205 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
 206                                       "Support MPX instructions">;
 207 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 208                                      "Use LEA for adjusting the stack pointer">;
 209 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 210                                      "HasSlowDivide32", "true",
 211                                      "Use 8-bit divide for positive values less than 256">;
 212 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
 213                                      "HasSlowDivide64", "true",
 214                                      "Use 32-bit divide for positive values less than 2^32">;
 215 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 216                                      "PadShortFunctions", "true",
 217                                      "Pad short functions">;
 218 def FeatureINVPCID : SubtargetFeature<"invpcid", "HasInvPCId", "true",
 219                                       "Invalidate Process-Context Identifier">;
 220 def FeatureVMFUNC  : SubtargetFeature<"vmfunc", "HasVMFUNC", "true",
 221                                       "VM Functions">;
 222 def FeatureSMAP    : SubtargetFeature<"smap", "HasSMAP", "true",
 223                                       "Supervisor Mode Access Protection">;
 224 def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
 225                                       "Enable Software Guard Extensions">;
 226 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
 227                                       "Flush A Cache Line Optimized">;
 228 def FeaturePCOMMIT : SubtargetFeature<"pcommit", "HasPCOMMIT", "true",
 229                                       "Enable Persistent Commit">;
 230 def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
 231                                       "Cache Line Write Back">;
 232 // TODO: This feature ought to be renamed.
 233 // What it really refers to are CPUs for which certain instructions
 234 // (which ones besides the example below?) are microcoded.
 235 // The best examples of this are the memory forms of CALL and PUSH
 236 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
 237 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 238                                      "CallRegIndirect", "true",
 239                                      "Call register indirect">;
 240 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 241                                    "LEA instruction needs inputs at AG stage">;
 242 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 243                                    "LEA instruction with certain arguments is slow">;
 244 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 245                                    "INC and DEC instructions are slower than ADD and SUB">;
 246 def FeatureSoftFloat
 247     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 248                        "Use software floating point features.">;
 249 // On at least some AMD processors, there is no performance hazard to writing
 250 // only the lower parts of a YMM register without clearing the upper part.
 251 def FeatureFastPartialYMMWrite
 252     : SubtargetFeature<"fast-partial-ymm-write", "HasFastPartialYMMWrite",
 253                        "true", "Partial writes to YMM registers are fast">;
 254 // FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
 255 // than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if
 256 // vector FSQRT has higher throughput than the corresponding NR code.
 257 // The idea is that throughput bound code is likely to be vectorized, so for
 258 // vectorized code we should care about the throughput of SQRT operations.
 259 // But if the code is scalar that probably means that the code has some kind of
 260 // dependency and we should care more about reducing the latency.
 261 def FeatureFastScalarFSQRT
 262     : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
 263                        "true", "Scalar SQRT is fast (disable Newton-Raphson)">;
 264 def FeatureFastVectorFSQRT
 265     : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
 266                        "true", "Vector SQRT is fast (disable Newton-Raphson)">;
 267 // If lzcnt has equivalent latency/throughput to most simple integer ops, it can
 268 // be used to replace test/set sequences.
 269 def FeatureFastLZCNT
 270     : SubtargetFeature<
 271           "fast-lzcnt", "HasFastLZCNT", "true",
 272           "LZCNT instructions are as fast as most simple integer ops">;
 273
 274 //===----------------------------------------------------------------------===//
 275 // X86 processors supported.
 276 //===----------------------------------------------------------------------===//
 277
 278 include "X86Schedule.td"
 279
 280 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 281                     "Intel Atom processors">;
 282 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 283                     "Intel Silvermont processors">;
 284
 285 class Proc<string Name, list<SubtargetFeature> Features>
 286  : ProcessorModel<Name, GenericModel, Features>;
 287
 288 def : Proc<"generic",         [FeatureX87, FeatureSlowUAMem16]>;
 289 def : Proc<"i386",            [FeatureX87, FeatureSlowUAMem16]>;
 290 def : Proc<"i486",            [FeatureX87, FeatureSlowUAMem16]>;
 291 def : Proc<"i586",            [FeatureX87, FeatureSlowUAMem16]>;
 292 def : Proc<"pentium",         [FeatureX87, FeatureSlowUAMem16]>;
 293 def : Proc<"pentium-mmx",     [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 294 def : Proc<"i686",            [FeatureX87, FeatureSlowUAMem16]>;
 295 def : Proc<"pentiumpro",      [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
 296 def : Proc<"pentium2",        [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 297                                FeatureCMOV, FeatureFXSR]>;
 298 def : Proc<"pentium3",        [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 299                                FeatureSSE1, FeatureFXSR]>;
 300 def : Proc<"pentium3m",       [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 301                                FeatureSSE1, FeatureFXSR, FeatureSlowBTMem]>;
 302
 303 // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
 304 // The intent is to enable it for pentium4 which is the current default
 305 // processor in a vanilla 32-bit clang compilation when no specific
 306 // architecture is specified.  This generally gives a nice performance
 307 // increase on silvermont, with largely neutral behavior on other
 308 // contemporary large core processors.
 309 // pentium-m, pentium4m, prescott and nocona are included as a preventative
 310 // measure to avoid performance surprises, in case clang's default cpu
 311 // changes slightly.
 312
 313 def : ProcessorModel<"pentium-m", GenericPostRAModel,
 314                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 315                       FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
 316
 317 def : ProcessorModel<"pentium4", GenericPostRAModel,
 318                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 319                       FeatureSSE2, FeatureFXSR]>;
 320
 321 def : ProcessorModel<"pentium4m", GenericPostRAModel,
 322                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 323                       FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
 324
 325 // Intel Quark.
 326 def : Proc<"lakemont",        []>;
 327
 328 // Intel Core Duo.
 329 def : ProcessorModel<"yonah", SandyBridgeModel,
 330                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
 331                       FeatureFXSR, FeatureSlowBTMem]>;
 332
 333 // NetBurst.
 334 def : ProcessorModel<"prescott", GenericPostRAModel,
 335                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
 336                       FeatureFXSR, FeatureSlowBTMem]>;
 337 def : ProcessorModel<"nocona", GenericPostRAModel, [
 338   FeatureX87,
 339   FeatureSlowUAMem16,
 340   FeatureMMX,
 341   FeatureSSE3,
 342   FeatureFXSR,
 343   FeatureCMPXCHG16B,
 344   FeatureSlowBTMem
 345 ]>;
 346
 347 // Intel Core 2 Solo/Duo.
 348 def : ProcessorModel<"core2", SandyBridgeModel, [
 349   FeatureX87,
 350   FeatureSlowUAMem16,
 351   FeatureMMX,
 352   FeatureSSSE3,
 353   FeatureFXSR,
 354   FeatureCMPXCHG16B,
 355   FeatureSlowBTMem,
 356   FeatureLAHFSAHF
 357 ]>;
 358 def : ProcessorModel<"penryn", SandyBridgeModel, [
 359   FeatureX87,
 360   FeatureSlowUAMem16,
 361   FeatureMMX,
 362   FeatureSSE41,
 363   FeatureFXSR,
 364   FeatureCMPXCHG16B,
 365   FeatureSlowBTMem,
 366   FeatureLAHFSAHF
 367 ]>;
 368
 369 // Atom CPUs.
 370 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 371   ProcIntelAtom,
 372   FeatureX87,
 373   FeatureSlowUAMem16,
 374   FeatureMMX,
 375   FeatureSSSE3,
 376   FeatureFXSR,
 377   FeatureCMPXCHG16B,
 378   FeatureMOVBE,
 379   FeatureSlowBTMem,
 380   FeatureLEAForSP,
 381   FeatureSlowDivide32,
 382   FeatureSlowDivide64,
 383   FeatureCallRegIndirect,
 384   FeatureLEAUsesAG,
 385   FeaturePadShortFunctions,
 386   FeatureLAHFSAHF
 387 ]>;
 388 def : BonnellProc<"bonnell">;
 389 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 390
 391 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 392   ProcIntelSLM,
 393   FeatureX87,
 394   FeatureMMX,
 395   FeatureSSE42,
 396   FeatureFXSR,
 397   FeatureCMPXCHG16B,
 398   FeatureMOVBE,
 399   FeaturePOPCNT,
 400   FeaturePCLMUL,
 401   FeatureAES,
 402   FeatureSlowDivide64,
 403   FeatureCallRegIndirect,
 404   FeaturePRFCHW,
 405   FeatureSlowLEA,
 406   FeatureSlowIncDec,
 407   FeatureSlowBTMem,
 408   FeatureSlowPMULLD,
 409   FeatureLAHFSAHF
 410 ]>;
 411 def : SilvermontProc<"silvermont">;
 412 def : SilvermontProc<"slm">; // Legacy alias.
 413
 414 // "Arrandale" along with corei3 and corei5
 415 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 416   FeatureX87,
 417   FeatureMMX,
 418   FeatureSSE42,
 419   FeatureFXSR,
 420   FeatureCMPXCHG16B,
 421   FeatureSlowBTMem,
 422   FeaturePOPCNT,
 423   FeatureLAHFSAHF
 424 ]>;
 425 def : NehalemProc<"nehalem">;
 426 def : NehalemProc<"corei7">;
 427
 428 // Westmere is a similar machine to nehalem with some additional features.
 429 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 430 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 431   FeatureX87,
 432   FeatureMMX,
 433   FeatureSSE42,
 434   FeatureFXSR,
 435   FeatureCMPXCHG16B,
 436   FeatureSlowBTMem,
 437   FeaturePOPCNT,
 438   FeatureAES,
 439   FeaturePCLMUL,
 440   FeatureLAHFSAHF
 441 ]>;
 442 def : WestmereProc<"westmere">;
 443
 444 class ProcessorFeatures<list<SubtargetFeature> Inherited,
 445                         list<SubtargetFeature> NewFeatures> {
 446   list<SubtargetFeature> Value = !listconcat(Inherited, NewFeatures);
 447 }
 448
 449 class ProcModel<string Name, SchedMachineModel Model,
 450                 list<SubtargetFeature> ProcFeatures,
 451                 list<SubtargetFeature> OtherFeatures> :
 452   ProcessorModel<Name, Model, !listconcat(ProcFeatures, OtherFeatures)>;
 453
 454 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 455 // rather than a superset.
 456 def SNBFeatures : ProcessorFeatures<[], [
 457   FeatureX87,
 458   FeatureMMX,
 459   FeatureAVX,
 460   FeatureFXSR,
 461   FeatureCMPXCHG16B,
 462   FeaturePOPCNT,
 463   FeatureAES,
 464   FeatureSlowDivide64,
 465   FeaturePCLMUL,
 466   FeatureXSAVE,
 467   FeatureXSAVEOPT,
 468   FeatureLAHFSAHF,
 469   FeatureFastScalarFSQRT
 470 ]>;
 471
 472 class SandyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
 473                                                SNBFeatures.Value, [
 474   FeatureSlowBTMem,
 475   FeatureSlowUAMem32
 476 ]>;
 477 def : SandyBridgeProc<"sandybridge">;
 478 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 479
 480 def IVBFeatures : ProcessorFeatures<SNBFeatures.Value, [
 481   FeatureRDRAND,
 482   FeatureF16C,
 483   FeatureFSGSBase
 484 ]>;
 485
 486 class IvyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
 487                                              IVBFeatures.Value, [
 488   FeatureSlowBTMem,
 489   FeatureSlowUAMem32
 490 ]>;
 491 def : IvyBridgeProc<"ivybridge">;
 492 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 493
 494 def HSWFeatures : ProcessorFeatures<IVBFeatures.Value, [
 495   FeatureAVX2,
 496   FeatureBMI,
 497   FeatureBMI2,
 498   FeatureFMA,
 499   FeatureLZCNT,
 500   FeatureMOVBE,
 501   FeatureINVPCID,
 502   FeatureVMFUNC,
 503   FeatureRTM,
 504   FeatureHLE,
 505   FeatureSlowIncDec
 506 ]>;
 507
 508 class HaswellProc<string Name> : ProcModel<Name, HaswellModel,
 509                                            HSWFeatures.Value, []>;
 510 def : HaswellProc<"haswell">;
 511 def : HaswellProc<"core-avx2">; // Legacy alias.
 512
 513 def BDWFeatures : ProcessorFeatures<HSWFeatures.Value, [
 514   FeatureADX,
 515   FeatureRDSEED,
 516   FeatureSMAP
 517 ]>;
 518 class BroadwellProc<string Name> : ProcModel<Name, HaswellModel,
 519                                              BDWFeatures.Value, []>;
 520 def : BroadwellProc<"broadwell">;
 521
 522 def SKLFeatures : ProcessorFeatures<BDWFeatures.Value, [
 523   FeatureMPX,
 524   FeatureXSAVEC,
 525   FeatureXSAVES,
 526   FeatureSGX,
 527   FeatureCLFLUSHOPT,
 528   FeatureFastVectorFSQRT
 529 ]>;
 530
 531 // FIXME: define SKL model
 532 class SkylakeClientProc<string Name> : ProcModel<Name, HaswellModel,
 533                                                  SKLFeatures.Value, []>;
 534 def : SkylakeClientProc<"skylake">;
 535
 536 // FIXME: define KNL model
 537 class KnightsLandingProc<string Name> : ProcModel<Name, HaswellModel,
 538                                                   IVBFeatures.Value, [
 539   FeatureAVX512,
 540   FeatureERI,
 541   FeatureCDI,
 542   FeaturePFI,
 543   FeaturePREFETCHWT1,
 544   FeatureADX,
 545   FeatureRDSEED,
 546   FeatureMOVBE,
 547   FeatureLZCNT,
 548   FeatureBMI,
 549   FeatureBMI2,
 550   FeatureFMA
 551 ]>;
 552 def : KnightsLandingProc<"knl">;
 553
 554 def SKXFeatures : ProcessorFeatures<SKLFeatures.Value, [
 555   FeatureAVX512,
 556   FeatureCDI,
 557   FeatureDQI,
 558   FeatureBWI,
 559   FeatureVLX,
 560   FeaturePKU,
 561   FeaturePCOMMIT,
 562   FeatureCLWB
 563 ]>;
 564
 565 // FIXME: define SKX model
 566 class SkylakeServerProc<string Name> : ProcModel<Name, HaswellModel,
 567                                                  SKXFeatures.Value, []>;
 568 def : SkylakeServerProc<"skylake-avx512">;
 569 def : SkylakeServerProc<"skx">; // Legacy alias.
 570
 571 def CNLFeatures : ProcessorFeatures<SKXFeatures.Value, [
 572   FeatureVBMI,
 573   FeatureIFMA,
 574   FeatureSHA
 575 ]>;
 576
 577 class CannonlakeProc<string Name> : ProcModel<Name, HaswellModel,
 578                                               CNLFeatures.Value, []>;
 579 def : CannonlakeProc<"cannonlake">;
 580
 581 // AMD CPUs.
 582
 583 def : Proc<"k6",              [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 584 def : Proc<"k6-2",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 585 def : Proc<"k6-3",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 586 def : Proc<"athlon",          [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
 587                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 588 def : Proc<"athlon-tbird",    [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
 589                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 590 def : Proc<"athlon-4",        [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 591                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 592                                FeatureSlowSHLD]>;
 593 def : Proc<"athlon-xp",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 594                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 595                                FeatureSlowSHLD]>;
 596 def : Proc<"athlon-mp",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 597                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 598                                FeatureSlowSHLD]>;
 599 def : Proc<"k8",              [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 600                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 601                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 602 def : Proc<"opteron",         [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 603                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 604                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 605 def : Proc<"athlon64",        [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 606                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 607                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 608 def : Proc<"athlon-fx",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 609                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 610                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 611 def : Proc<"k8-sse3",         [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 612                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 613                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 614 def : Proc<"opteron-sse3",    [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 615                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 616                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 617 def : Proc<"athlon64-sse3",   [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 618                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 619                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 620 def : Proc<"amdfam10",        [FeatureX87, FeatureSSE4A, Feature3DNowA,
 621                                FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
 622                                FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
 623                                FeatureLAHFSAHF]>;
 624 def : Proc<"barcelona",       [FeatureX87, FeatureSSE4A, Feature3DNowA,
 625                                FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
 626                                FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
 627                                FeatureLAHFSAHF]>;
 628
 629 // Bobcat
 630 def : Proc<"btver1", [
 631   FeatureX87,
 632   FeatureMMX,
 633   FeatureSSSE3,
 634   FeatureSSE4A,
 635   FeatureFXSR,
 636   FeatureCMPXCHG16B,
 637   FeaturePRFCHW,
 638   FeatureLZCNT,
 639   FeaturePOPCNT,
 640   FeatureSlowSHLD,
 641   FeatureLAHFSAHF
 642 ]>;
 643
 644 // Jaguar
 645 def : ProcessorModel<"btver2", BtVer2Model, [
 646   FeatureX87,
 647   FeatureMMX,
 648   FeatureAVX,
 649   FeatureFXSR,
 650   FeatureSSE4A,
 651   FeatureCMPXCHG16B,
 652   FeaturePRFCHW,
 653   FeatureAES,
 654   FeaturePCLMUL,
 655   FeatureBMI,
 656   FeatureF16C,
 657   FeatureMOVBE,
 658   FeatureLZCNT,
 659   FeatureFastLZCNT,
 660   FeaturePOPCNT,
 661   FeatureXSAVE,
 662   FeatureXSAVEOPT,
 663   FeatureSlowSHLD,
 664   FeatureLAHFSAHF,
 665   FeatureFastPartialYMMWrite
 666 ]>;
 667
 668 // Bulldozer
 669 def : Proc<"bdver1", [
 670   FeatureX87,
 671   FeatureXOP,
 672   FeatureFMA4,
 673   FeatureCMPXCHG16B,
 674   FeatureAES,
 675   FeaturePRFCHW,
 676   FeaturePCLMUL,
 677   FeatureMMX,
 678   FeatureAVX,
 679   FeatureFXSR,
 680   FeatureSSE4A,
 681   FeatureLZCNT,
 682   FeaturePOPCNT,
 683   FeatureXSAVE,
 684   FeatureSlowSHLD,
 685   FeatureLAHFSAHF
 686 ]>;
 687 // Piledriver
 688 def : Proc<"bdver2", [
 689   FeatureX87,
 690   FeatureXOP,
 691   FeatureFMA4,
 692   FeatureCMPXCHG16B,
 693   FeatureAES,
 694   FeaturePRFCHW,
 695   FeaturePCLMUL,
 696   FeatureMMX,
 697   FeatureAVX,
 698   FeatureFXSR,
 699   FeatureSSE4A,
 700   FeatureF16C,
 701   FeatureLZCNT,
 702   FeaturePOPCNT,
 703   FeatureXSAVE,
 704   FeatureBMI,
 705   FeatureTBM,
 706   FeatureFMA,
 707   FeatureSlowSHLD,
 708   FeatureLAHFSAHF
 709 ]>;
 710
 711 // Steamroller
 712 def : Proc<"bdver3", [
 713   FeatureX87,
 714   FeatureXOP,
 715   FeatureFMA4,
 716   FeatureCMPXCHG16B,
 717   FeatureAES,
 718   FeaturePRFCHW,
 719   FeaturePCLMUL,
 720   FeatureMMX,
 721   FeatureAVX,
 722   FeatureFXSR,
 723   FeatureSSE4A,
 724   FeatureF16C,
 725   FeatureLZCNT,
 726   FeaturePOPCNT,
 727   FeatureXSAVE,
 728   FeatureBMI,
 729   FeatureTBM,
 730   FeatureFMA,
 731   FeatureXSAVEOPT,
 732   FeatureSlowSHLD,
 733   FeatureFSGSBase,
 734   FeatureLAHFSAHF
 735 ]>;
 736
 737 // Excavator
 738 def : Proc<"bdver4", [
 739   FeatureX87,
 740   FeatureMMX,
 741   FeatureAVX2,
 742   FeatureFXSR,
 743   FeatureXOP,
 744   FeatureFMA4,
 745   FeatureCMPXCHG16B,
 746   FeatureAES,
 747   FeaturePRFCHW,
 748   FeaturePCLMUL,
 749   FeatureF16C,
 750   FeatureLZCNT,
 751   FeaturePOPCNT,
 752   FeatureXSAVE,
 753   FeatureBMI,
 754   FeatureBMI2,
 755   FeatureTBM,
 756   FeatureFMA,
 757   FeatureXSAVEOPT,
 758   FeatureSlowSHLD,
 759   FeatureFSGSBase,
 760   FeatureLAHFSAHF,
 761   FeatureMWAITX
 762 ]>;
 763
 764 // TODO: The scheduler model falls to BTVER2 model.
 765 // The znver1 model has to be put in place.
 766 // Zen
 767 def: ProcessorModel<"znver1", BtVer2Model, [
 768   FeatureADX,
 769   FeatureAES,
 770   FeatureAVX2,
 771   FeatureBMI,
 772   FeatureBMI2,
 773   FeatureCLFLUSHOPT,
 774   FeatureCMPXCHG16B,
 775   FeatureF16C,
 776   FeatureFMA,
 777   FeatureFSGSBase,
 778   FeatureFXSR,
 779   FeatureFastLZCNT,
 780   FeatureLAHFSAHF,
 781   FeatureLZCNT,
 782   FeatureMMX,
 783   FeatureMOVBE,
 784   FeatureMWAITX,
 785   FeaturePCLMUL,
 786   FeaturePOPCNT,
 787   FeaturePRFCHW,
 788   FeatureRDRAND,
 789   FeatureRDSEED,
 790   FeatureSHA,
 791   FeatureSMAP,
 792   FeatureSSE4A,
 793   FeatureSlowSHLD,
 794   FeatureX87,
 795   FeatureXSAVE,
 796   FeatureXSAVEC,
 797   FeatureXSAVEOPT,
 798   FeatureXSAVES]>;
 799
 800 def : Proc<"geode",           [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>;
 801
 802 def : Proc<"winchip-c6",      [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 803 def : Proc<"winchip2",        [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 804 def : Proc<"c3",              [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 805 def : Proc<"c3-2",            [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 806                                FeatureSSE1, FeatureFXSR]>;
 807
 808 // We also provide a generic 64-bit specific x86 processor model which tries to
 809 // be good for modern chips without enabling instruction set encodings past the
 810 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 811 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 812 //
 813 // We currently use the Sandy Bridge model as the default scheduling model as
 814 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 815 // covers a huge swath of x86 processors. If there are specific scheduling
 816 // knobs which need to be tuned differently for AMD chips, we might consider
 817 // forming a common base for them.
 818 def : ProcessorModel<"x86-64", SandyBridgeModel,
 819                      [FeatureX87, FeatureMMX, FeatureSSE2, FeatureFXSR,
 820                       Feature64Bit, FeatureSlowBTMem ]>;
 821
 822 //===----------------------------------------------------------------------===//
 823 // Register File Description
 824 //===----------------------------------------------------------------------===//
 825
 826 include "X86RegisterInfo.td"
 827
 828 //===----------------------------------------------------------------------===//
 829 // Instruction Descriptions
 830 //===----------------------------------------------------------------------===//
 831
 832 include "X86InstrInfo.td"
 833
 834 def X86InstrInfo : InstrInfo;
 835
 836 //===----------------------------------------------------------------------===//
 837 // Calling Conventions
 838 //===----------------------------------------------------------------------===//
 839
 840 include "X86CallingConv.td"
 841
 842
 843 //===----------------------------------------------------------------------===//
 844 // Assembly Parser
 845 //===----------------------------------------------------------------------===//
 846
 847 def ATTAsmParserVariant : AsmParserVariant {
 848   int Variant = 0;
 849
 850   // Variant name.
 851   string Name = "att";
 852
 853   // Discard comments in assembly strings.
 854   string CommentDelimiter = "#";
 855
 856   // Recognize hard coded registers.
 857   string RegisterPrefix = "%";
 858 }
 859
 860 def IntelAsmParserVariant : AsmParserVariant {
 861   int Variant = 1;
 862
 863   // Variant name.
 864   string Name = "intel";
 865
 866   // Discard comments in assembly strings.
 867   string CommentDelimiter = ";";
 868
 869   // Recognize hard coded registers.
 870   string RegisterPrefix = "";
 871 }
 872
 873 //===----------------------------------------------------------------------===//
 874 // Assembly Printers
 875 //===----------------------------------------------------------------------===//
 876
 877 // The X86 target supports two different syntaxes for emitting machine code.
 878 // This is controlled by the -x86-asm-syntax={att|intel}
 879 def ATTAsmWriter : AsmWriter {
 880   string AsmWriterClassName  = "ATTInstPrinter";
 881   int Variant = 0;
 882 }
 883 def IntelAsmWriter : AsmWriter {
 884   string AsmWriterClassName  = "IntelInstPrinter";
 885   int Variant = 1;
 886 }
 887
 888 def X86 : Target {
 889   // Information about the instructions...
 890   let InstructionSet = X86InstrInfo;
 891   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 892   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 893 }