lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureX87     : SubtargetFeature<"x87","HasX87", "true",
  35                                       "Enable X87 float instructions">;
  36
  37 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  38                                       "Enable conditional move instructions">;
  39
  40 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  41                                        "Support POPCNT instruction">;
  42
  43 def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
  44                                       "Support fxsave/fxrestore instructions">;
  45
  46 def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
  47                                        "Support xsave instructions">;
  48
  49 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
  50                                        "Support xsaveopt instructions">;
  51
  52 def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
  53                                        "Support xsavec instructions">;
  54
  55 def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
  56                                        "Support xsaves instructions">;
  57
  58 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  59                                       "Enable SSE instructions",
  60                                       // SSE codegen depends on cmovs, and all
  61                                       // SSE1+ processors support them.
  62                                       [FeatureCMOV]>;
  63 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  64                                       "Enable SSE2 instructions",
  65                                       [FeatureSSE1]>;
  66 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  67                                       "Enable SSE3 instructions",
  68                                       [FeatureSSE2]>;
  69 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  70                                       "Enable SSSE3 instructions",
  71                                       [FeatureSSE3]>;
  72 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  73                                       "Enable SSE 4.1 instructions",
  74                                       [FeatureSSSE3]>;
  75 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  76                                       "Enable SSE 4.2 instructions",
  77                                       [FeatureSSE41]>;
  78 // The MMX subtarget feature is separate from the rest of the SSE features
  79 // because it's important (for odd compatibility reasons) to be able to
  80 // turn it off explicitly while allowing SSE+ to be on.
  81 def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
  82                                       "Enable MMX instructions">;
  83 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  84                                       "Enable 3DNow! instructions",
  85                                       [FeatureMMX]>;
  86 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  87                                       "Enable 3DNow! Athlon instructions",
  88                                       [Feature3DNow]>;
  89 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  90 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  91 // without disabling 64-bit mode.
  92 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  93                                       "Support 64-bit instructions",
  94                                       [FeatureCMOV]>;
  95 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  96                                       "64-bit with cmpxchg16b",
  97                                       [Feature64Bit]>;
  98 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  99                                        "Bit testing of memory is slow">;
 100 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
 101                                        "SHLD instruction is slow">;
 102 def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
 103                                         "PMULLD instruction is slow">;
 104 // FIXME: This should not apply to CPUs that do not have SSE.
 105 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
 106                                 "IsUAMem16Slow", "true",
 107                                 "Slow unaligned 16-byte memory access">;
 108 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
 109                                 "IsUAMem32Slow", "true",
 110                                 "Slow unaligned 32-byte memory access">;
 111 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
 112                                       "Support SSE 4a instructions",
 113                                       [FeatureSSE3]>;
 114
 115 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
 116                                       "Enable AVX instructions",
 117                                       [FeatureSSE42]>;
 118 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 119                                       "Enable AVX2 instructions",
 120                                       [FeatureAVX]>;
 121 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 122                                       "Enable AVX-512 instructions",
 123                                       [FeatureAVX2]>;
 124 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 125                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 126                                       [FeatureAVX512]>;
 127 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 128                       "Enable AVX-512 Conflict Detection Instructions",
 129                                       [FeatureAVX512]>;
 130 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 131                       "Enable AVX-512 PreFetch Instructions",
 132                                       [FeatureAVX512]>;
 133 def FeaturePREFETCHWT1  : SubtargetFeature<"prefetchwt1", "HasPFPREFETCHWT1",
 134                                    "true",
 135                                    "Prefetch with Intent to Write and T1 Hint">;
 136 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 137                       "Enable AVX-512 Doubleword and Quadword Instructions",
 138                                       [FeatureAVX512]>;
 139 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 140                       "Enable AVX-512 Byte and Word Instructions",
 141                                       [FeatureAVX512]>;
 142 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 143                       "Enable AVX-512 Vector Length eXtensions",
 144                                       [FeatureAVX512]>;
 145 def FeatureVBMI     : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
 146                       "Enable AVX-512 Vector Byte Manipulation Instructions",
 147                                       [FeatureBWI]>;
 148 def FeatureIFMA     : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
 149                       "Enable AVX-512 Integer Fused Multiple-Add",
 150                                       [FeatureAVX512]>;
 151 def FeaturePKU   : SubtargetFeature<"pku", "HasPKU", "true",
 152                       "Enable protection keys">;
 153 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 154                          "Enable packed carry-less multiplication instructions",
 155                                [FeatureSSE2]>;
 156 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 157                                       "Enable three-operand fused multiple-add",
 158                                       [FeatureAVX]>;
 159 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 160                                       "Enable four-operand fused multiple-add",
 161                                       [FeatureAVX, FeatureSSE4A]>;
 162 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 163                                       "Enable XOP instructions",
 164                                       [FeatureFMA4]>;
 165 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 166                                           "HasSSEUnalignedMem", "true",
 167                       "Allow unaligned memory operands with SSE instructions">;
 168 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 169                                       "Enable AES instructions",
 170                                       [FeatureSSE2]>;
 171 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 172                                       "Enable TBM instructions">;
 173 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 174                                       "Support MOVBE instruction">;
 175 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 176                                       "Support RDRAND instruction">;
 177 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 178                        "Support 16-bit floating point conversion instructions",
 179                        [FeatureAVX]>;
 180 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 181                                        "Support FS/GS Base instructions">;
 182 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 183                                       "Support LZCNT instruction">;
 184 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 185                                       "Support BMI instructions">;
 186 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 187                                       "Support BMI2 instructions">;
 188 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 189                                       "Support RTM instructions">;
 190 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 191                                       "Support ADX instructions">;
 192 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 193                                       "Enable SHA instructions",
 194                                       [FeatureSSE2]>;
 195 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 196                                       "Support PRFCHW instructions">;
 197 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 198                                       "Support RDSEED instruction">;
 199 def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
 200                                        "Support LAHF and SAHF instructions">;
 201 def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
 202                                       "Enable MONITORX/MWAITX timer functionality">;
 203 def FeatureCLZERO  : SubtargetFeature<"clzero", "HasCLZERO", "true",
 204                                       "Enable Cache Line Zero">;
 205 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
 206                                       "Support MPX instructions">;
 207 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 208                                      "Use LEA for adjusting the stack pointer">;
 209 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 210                                      "HasSlowDivide32", "true",
 211                                      "Use 8-bit divide for positive values less than 256">;
 212 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
 213                                      "HasSlowDivide64", "true",
 214                                      "Use 32-bit divide for positive values less than 2^32">;
 215 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 216                                      "PadShortFunctions", "true",
 217                                      "Pad short functions">;
 218 def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
 219                                       "Enable Software Guard Extensions">;
 220 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
 221                                       "Flush A Cache Line Optimized">;
 222 def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
 223                                       "Cache Line Write Back">;
 224 // TODO: This feature ought to be renamed.
 225 // What it really refers to are CPUs for which certain instructions
 226 // (which ones besides the example below?) are microcoded.
 227 // The best examples of this are the memory forms of CALL and PUSH
 228 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
 229 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 230                                      "CallRegIndirect", "true",
 231                                      "Call register indirect">;
 232 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 233                                    "LEA instruction needs inputs at AG stage">;
 234 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 235                                    "LEA instruction with certain arguments is slow">;
 236 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 237                                    "INC and DEC instructions are slower than ADD and SUB">;
 238 def FeatureSoftFloat
 239     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 240                        "Use software floating point features.">;
 241 // On some X86 processors, there is no performance hazard to writing only the
 242 // lower parts of a YMM or ZMM register without clearing the upper part.
 243 def FeatureFastPartialYMMorZMMWrite
 244     : SubtargetFeature<"fast-partial-ymm-or-zmm-write",
 245                        "HasFastPartialYMMorZMMWrite",
 246                        "true", "Partial writes to YMM/ZMM registers are fast">;
 247 // FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
 248 // than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if
 249 // vector FSQRT has higher throughput than the corresponding NR code.
 250 // The idea is that throughput bound code is likely to be vectorized, so for
 251 // vectorized code we should care about the throughput of SQRT operations.
 252 // But if the code is scalar that probably means that the code has some kind of
 253 // dependency and we should care more about reducing the latency.
 254 def FeatureFastScalarFSQRT
 255     : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
 256                        "true", "Scalar SQRT is fast (disable Newton-Raphson)">;
 257 def FeatureFastVectorFSQRT
 258     : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
 259                        "true", "Vector SQRT is fast (disable Newton-Raphson)">;
 260 // If lzcnt has equivalent latency/throughput to most simple integer ops, it can
 261 // be used to replace test/set sequences.
 262 def FeatureFastLZCNT
 263     : SubtargetFeature<
 264           "fast-lzcnt", "HasFastLZCNT", "true",
 265           "LZCNT instructions are as fast as most simple integer ops">;
 266
 267
 268 // Sandy Bridge and newer processors can use SHLD with the same source on both
 269 // inputs to implement rotate to avoid the partial flag update of the normal
 270 // rotate instructions.
 271 def FeatureFastSHLDRotate
 272     : SubtargetFeature<
 273           "fast-shld-rotate", "HasFastSHLDRotate", "true",
 274           "SHLD can be used as a faster rotate">;
 275
 276 // Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
 277 // "string operations"). See "REP String Enhancement" in the Intel Software
 278 // Development Manual. This feature essentially means that REP MOVSB will copy
 279 // using the largest available size instead of copying bytes one by one, making
 280 // it at least as fast as REPMOVS{W,D,Q}.
 281 def FeatureERMSB
 282     : SubtargetFeature<
 283           "ermsb", "HasERMSB", "true",
 284           "REP MOVS/STOS are fast">;
 285
 286 //===----------------------------------------------------------------------===//
 287 // X86 processors supported.
 288 //===----------------------------------------------------------------------===//
 289
 290 include "X86Schedule.td"
 291
 292 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 293                     "Intel Atom processors">;
 294 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 295                     "Intel Silvermont processors">;
 296
 297 class Proc<string Name, list<SubtargetFeature> Features>
 298  : ProcessorModel<Name, GenericModel, Features>;
 299
 300 def : Proc<"generic",         [FeatureX87, FeatureSlowUAMem16]>;
 301 def : Proc<"i386",            [FeatureX87, FeatureSlowUAMem16]>;
 302 def : Proc<"i486",            [FeatureX87, FeatureSlowUAMem16]>;
 303 def : Proc<"i586",            [FeatureX87, FeatureSlowUAMem16]>;
 304 def : Proc<"pentium",         [FeatureX87, FeatureSlowUAMem16]>;
 305 def : Proc<"pentium-mmx",     [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 306 def : Proc<"i686",            [FeatureX87, FeatureSlowUAMem16]>;
 307 def : Proc<"pentiumpro",      [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
 308 def : Proc<"pentium2",        [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 309                                FeatureCMOV, FeatureFXSR]>;
 310 def : Proc<"pentium3",        [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 311                                FeatureSSE1, FeatureFXSR]>;
 312 def : Proc<"pentium3m",       [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 313                                FeatureSSE1, FeatureFXSR, FeatureSlowBTMem]>;
 314
 315 // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
 316 // The intent is to enable it for pentium4 which is the current default
 317 // processor in a vanilla 32-bit clang compilation when no specific
 318 // architecture is specified.  This generally gives a nice performance
 319 // increase on silvermont, with largely neutral behavior on other
 320 // contemporary large core processors.
 321 // pentium-m, pentium4m, prescott and nocona are included as a preventative
 322 // measure to avoid performance surprises, in case clang's default cpu
 323 // changes slightly.
 324
 325 def : ProcessorModel<"pentium-m", GenericPostRAModel,
 326                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 327                       FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
 328
 329 def : ProcessorModel<"pentium4", GenericPostRAModel,
 330                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 331                       FeatureSSE2, FeatureFXSR]>;
 332
 333 def : ProcessorModel<"pentium4m", GenericPostRAModel,
 334                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 335                       FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
 336
 337 // Intel Quark.
 338 def : Proc<"lakemont",        []>;
 339
 340 // Intel Core Duo.
 341 def : ProcessorModel<"yonah", SandyBridgeModel,
 342                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
 343                       FeatureFXSR, FeatureSlowBTMem]>;
 344
 345 // NetBurst.
 346 def : ProcessorModel<"prescott", GenericPostRAModel,
 347                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
 348                       FeatureFXSR, FeatureSlowBTMem]>;
 349 def : ProcessorModel<"nocona", GenericPostRAModel, [
 350   FeatureX87,
 351   FeatureSlowUAMem16,
 352   FeatureMMX,
 353   FeatureSSE3,
 354   FeatureFXSR,
 355   FeatureCMPXCHG16B,
 356   FeatureSlowBTMem
 357 ]>;
 358
 359 // Intel Core 2 Solo/Duo.
 360 def : ProcessorModel<"core2", SandyBridgeModel, [
 361   FeatureX87,
 362   FeatureSlowUAMem16,
 363   FeatureMMX,
 364   FeatureSSSE3,
 365   FeatureFXSR,
 366   FeatureCMPXCHG16B,
 367   FeatureSlowBTMem,
 368   FeatureLAHFSAHF
 369 ]>;
 370 def : ProcessorModel<"penryn", SandyBridgeModel, [
 371   FeatureX87,
 372   FeatureSlowUAMem16,
 373   FeatureMMX,
 374   FeatureSSE41,
 375   FeatureFXSR,
 376   FeatureCMPXCHG16B,
 377   FeatureSlowBTMem,
 378   FeatureLAHFSAHF
 379 ]>;
 380
 381 // Atom CPUs.
 382 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 383   ProcIntelAtom,
 384   FeatureX87,
 385   FeatureSlowUAMem16,
 386   FeatureMMX,
 387   FeatureSSSE3,
 388   FeatureFXSR,
 389   FeatureCMPXCHG16B,
 390   FeatureMOVBE,
 391   FeatureSlowBTMem,
 392   FeatureLEAForSP,
 393   FeatureSlowDivide32,
 394   FeatureSlowDivide64,
 395   FeatureCallRegIndirect,
 396   FeatureLEAUsesAG,
 397   FeaturePadShortFunctions,
 398   FeatureLAHFSAHF
 399 ]>;
 400 def : BonnellProc<"bonnell">;
 401 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 402
 403 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 404   ProcIntelSLM,
 405   FeatureX87,
 406   FeatureMMX,
 407   FeatureSSE42,
 408   FeatureFXSR,
 409   FeatureCMPXCHG16B,
 410   FeatureMOVBE,
 411   FeaturePOPCNT,
 412   FeaturePCLMUL,
 413   FeatureAES,
 414   FeatureSlowDivide64,
 415   FeatureCallRegIndirect,
 416   FeaturePRFCHW,
 417   FeatureSlowLEA,
 418   FeatureSlowIncDec,
 419   FeatureSlowBTMem,
 420   FeatureSlowPMULLD,
 421   FeatureLAHFSAHF
 422 ]>;
 423 def : SilvermontProc<"silvermont">;
 424 def : SilvermontProc<"slm">; // Legacy alias.
 425
 426 // "Arrandale" along with corei3 and corei5
 427 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 428   FeatureX87,
 429   FeatureMMX,
 430   FeatureSSE42,
 431   FeatureFXSR,
 432   FeatureCMPXCHG16B,
 433   FeatureSlowBTMem,
 434   FeaturePOPCNT,
 435   FeatureLAHFSAHF
 436 ]>;
 437 def : NehalemProc<"nehalem">;
 438 def : NehalemProc<"corei7">;
 439
 440 // Westmere is a similar machine to nehalem with some additional features.
 441 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 442 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 443   FeatureX87,
 444   FeatureMMX,
 445   FeatureSSE42,
 446   FeatureFXSR,
 447   FeatureCMPXCHG16B,
 448   FeatureSlowBTMem,
 449   FeaturePOPCNT,
 450   FeatureAES,
 451   FeaturePCLMUL,
 452   FeatureLAHFSAHF
 453 ]>;
 454 def : WestmereProc<"westmere">;
 455
 456 class ProcessorFeatures<list<SubtargetFeature> Inherited,
 457                         list<SubtargetFeature> NewFeatures> {
 458   list<SubtargetFeature> Value = !listconcat(Inherited, NewFeatures);
 459 }
 460
 461 class ProcModel<string Name, SchedMachineModel Model,
 462                 list<SubtargetFeature> ProcFeatures,
 463                 list<SubtargetFeature> OtherFeatures> :
 464   ProcessorModel<Name, Model, !listconcat(ProcFeatures, OtherFeatures)>;
 465
 466 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 467 // rather than a superset.
 468 def SNBFeatures : ProcessorFeatures<[], [
 469   FeatureX87,
 470   FeatureMMX,
 471   FeatureAVX,
 472   FeatureFXSR,
 473   FeatureCMPXCHG16B,
 474   FeaturePOPCNT,
 475   FeatureAES,
 476   FeatureSlowDivide64,
 477   FeaturePCLMUL,
 478   FeatureXSAVE,
 479   FeatureXSAVEOPT,
 480   FeatureLAHFSAHF,
 481   FeatureFastScalarFSQRT,
 482   FeatureFastSHLDRotate
 483 ]>;
 484
 485 class SandyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
 486                                                SNBFeatures.Value, [
 487   FeatureSlowBTMem,
 488   FeatureSlowUAMem32
 489 ]>;
 490 def : SandyBridgeProc<"sandybridge">;
 491 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 492
 493 def IVBFeatures : ProcessorFeatures<SNBFeatures.Value, [
 494   FeatureRDRAND,
 495   FeatureF16C,
 496   FeatureFSGSBase
 497 ]>;
 498
 499 class IvyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
 500                                              IVBFeatures.Value, [
 501   FeatureSlowBTMem,
 502   FeatureSlowUAMem32
 503 ]>;
 504 def : IvyBridgeProc<"ivybridge">;
 505 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 506
 507 def HSWFeatures : ProcessorFeatures<IVBFeatures.Value, [
 508   FeatureAVX2,
 509   FeatureBMI,
 510   FeatureBMI2,
 511   FeatureERMSB,
 512   FeatureFMA,
 513   FeatureLZCNT,
 514   FeatureMOVBE,
 515   FeatureSlowIncDec
 516 ]>;
 517
 518 class HaswellProc<string Name> : ProcModel<Name, HaswellModel,
 519                                            HSWFeatures.Value, []>;
 520 def : HaswellProc<"haswell">;
 521 def : HaswellProc<"core-avx2">; // Legacy alias.
 522
 523 def BDWFeatures : ProcessorFeatures<HSWFeatures.Value, [
 524   FeatureADX,
 525   FeatureRDSEED
 526 ]>;
 527 class BroadwellProc<string Name> : ProcModel<Name, HaswellModel,
 528                                              BDWFeatures.Value, []>;
 529 def : BroadwellProc<"broadwell">;
 530
 531 def SKLFeatures : ProcessorFeatures<BDWFeatures.Value, [
 532   FeatureMPX,
 533   FeatureRTM,
 534   FeatureXSAVEC,
 535   FeatureXSAVES,
 536   FeatureSGX,
 537   FeatureCLFLUSHOPT,
 538   FeatureFastVectorFSQRT
 539 ]>;
 540
 541 // FIXME: define SKL model
 542 class SkylakeClientProc<string Name> : ProcModel<Name, HaswellModel,
 543                                                  SKLFeatures.Value, []>;
 544 def : SkylakeClientProc<"skylake">;
 545
 546 // FIXME: define KNL model
 547 class KnightsLandingProc<string Name> : ProcModel<Name, HaswellModel,
 548                                                   IVBFeatures.Value, [
 549   FeatureAVX512,
 550   FeatureERI,
 551   FeatureCDI,
 552   FeaturePFI,
 553   FeaturePREFETCHWT1,
 554   FeatureADX,
 555   FeatureRDSEED,
 556   FeatureMOVBE,
 557   FeatureLZCNT,
 558   FeatureBMI,
 559   FeatureBMI2,
 560   FeatureFMA,
 561   FeatureFastPartialYMMorZMMWrite
 562 ]>;
 563 def : KnightsLandingProc<"knl">;
 564
 565 def SKXFeatures : ProcessorFeatures<SKLFeatures.Value, [
 566   FeatureAVX512,
 567   FeatureCDI,
 568   FeatureDQI,
 569   FeatureBWI,
 570   FeatureVLX,
 571   FeaturePKU,
 572   FeatureCLWB
 573 ]>;
 574
 575 // FIXME: define SKX model
 576 class SkylakeServerProc<string Name> : ProcModel<Name, HaswellModel,
 577                                                  SKXFeatures.Value, []>;
 578 def : SkylakeServerProc<"skylake-avx512">;
 579 def : SkylakeServerProc<"skx">; // Legacy alias.
 580
 581 def CNLFeatures : ProcessorFeatures<SKXFeatures.Value, [
 582   FeatureVBMI,
 583   FeatureIFMA,
 584   FeatureSHA
 585 ]>;
 586
 587 class CannonlakeProc<string Name> : ProcModel<Name, HaswellModel,
 588                                               CNLFeatures.Value, []>;
 589 def : CannonlakeProc<"cannonlake">;
 590
 591 // AMD CPUs.
 592
 593 def : Proc<"k6",              [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 594 def : Proc<"k6-2",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 595 def : Proc<"k6-3",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 596 def : Proc<"athlon",          [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
 597                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 598 def : Proc<"athlon-tbird",    [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
 599                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 600 def : Proc<"athlon-4",        [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 601                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 602                                FeatureSlowSHLD]>;
 603 def : Proc<"athlon-xp",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 604                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 605                                FeatureSlowSHLD]>;
 606 def : Proc<"athlon-mp",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
 607                                Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
 608                                FeatureSlowSHLD]>;
 609 def : Proc<"k8",              [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 610                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 611                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 612 def : Proc<"opteron",         [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 613                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 614                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 615 def : Proc<"athlon64",        [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 616                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 617                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 618 def : Proc<"athlon-fx",       [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
 619                                Feature3DNowA, FeatureFXSR, Feature64Bit,
 620                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 621 def : Proc<"k8-sse3",         [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 622                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 623                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 624 def : Proc<"opteron-sse3",    [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 625                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 626                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 627 def : Proc<"athlon64-sse3",   [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
 628                                Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
 629                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 630 def : Proc<"amdfam10",        [FeatureX87, FeatureSSE4A, Feature3DNowA,
 631                                FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
 632                                FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
 633                                FeatureLAHFSAHF]>;
 634 def : Proc<"barcelona",       [FeatureX87, FeatureSSE4A, Feature3DNowA,
 635                                FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
 636                                FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
 637                                FeatureLAHFSAHF]>;
 638
 639 // Bobcat
 640 def : Proc<"btver1", [
 641   FeatureX87,
 642   FeatureMMX,
 643   FeatureSSSE3,
 644   FeatureSSE4A,
 645   FeatureFXSR,
 646   FeatureCMPXCHG16B,
 647   FeaturePRFCHW,
 648   FeatureLZCNT,
 649   FeaturePOPCNT,
 650   FeatureSlowSHLD,
 651   FeatureLAHFSAHF
 652 ]>;
 653
 654 // Jaguar
 655 def : ProcessorModel<"btver2", BtVer2Model, [
 656   FeatureX87,
 657   FeatureMMX,
 658   FeatureAVX,
 659   FeatureFXSR,
 660   FeatureSSE4A,
 661   FeatureCMPXCHG16B,
 662   FeaturePRFCHW,
 663   FeatureAES,
 664   FeaturePCLMUL,
 665   FeatureBMI,
 666   FeatureF16C,
 667   FeatureMOVBE,
 668   FeatureLZCNT,
 669   FeatureFastLZCNT,
 670   FeaturePOPCNT,
 671   FeatureXSAVE,
 672   FeatureXSAVEOPT,
 673   FeatureSlowSHLD,
 674   FeatureLAHFSAHF,
 675   FeatureFastPartialYMMorZMMWrite
 676 ]>;
 677
 678 // Bulldozer
 679 def : Proc<"bdver1", [
 680   FeatureX87,
 681   FeatureXOP,
 682   FeatureFMA4,
 683   FeatureCMPXCHG16B,
 684   FeatureAES,
 685   FeaturePRFCHW,
 686   FeaturePCLMUL,
 687   FeatureMMX,
 688   FeatureAVX,
 689   FeatureFXSR,
 690   FeatureSSE4A,
 691   FeatureLZCNT,
 692   FeaturePOPCNT,
 693   FeatureXSAVE,
 694   FeatureSlowSHLD,
 695   FeatureLAHFSAHF
 696 ]>;
 697 // Piledriver
 698 def : Proc<"bdver2", [
 699   FeatureX87,
 700   FeatureXOP,
 701   FeatureFMA4,
 702   FeatureCMPXCHG16B,
 703   FeatureAES,
 704   FeaturePRFCHW,
 705   FeaturePCLMUL,
 706   FeatureMMX,
 707   FeatureAVX,
 708   FeatureFXSR,
 709   FeatureSSE4A,
 710   FeatureF16C,
 711   FeatureLZCNT,
 712   FeaturePOPCNT,
 713   FeatureXSAVE,
 714   FeatureBMI,
 715   FeatureTBM,
 716   FeatureFMA,
 717   FeatureSlowSHLD,
 718   FeatureLAHFSAHF
 719 ]>;
 720
 721 // Steamroller
 722 def : Proc<"bdver3", [
 723   FeatureX87,
 724   FeatureXOP,
 725   FeatureFMA4,
 726   FeatureCMPXCHG16B,
 727   FeatureAES,
 728   FeaturePRFCHW,
 729   FeaturePCLMUL,
 730   FeatureMMX,
 731   FeatureAVX,
 732   FeatureFXSR,
 733   FeatureSSE4A,
 734   FeatureF16C,
 735   FeatureLZCNT,
 736   FeaturePOPCNT,
 737   FeatureXSAVE,
 738   FeatureBMI,
 739   FeatureTBM,
 740   FeatureFMA,
 741   FeatureXSAVEOPT,
 742   FeatureSlowSHLD,
 743   FeatureFSGSBase,
 744   FeatureLAHFSAHF
 745 ]>;
 746
 747 // Excavator
 748 def : Proc<"bdver4", [
 749   FeatureX87,
 750   FeatureMMX,
 751   FeatureAVX2,
 752   FeatureFXSR,
 753   FeatureXOP,
 754   FeatureFMA4,
 755   FeatureCMPXCHG16B,
 756   FeatureAES,
 757   FeaturePRFCHW,
 758   FeaturePCLMUL,
 759   FeatureF16C,
 760   FeatureLZCNT,
 761   FeaturePOPCNT,
 762   FeatureXSAVE,
 763   FeatureBMI,
 764   FeatureBMI2,
 765   FeatureTBM,
 766   FeatureFMA,
 767   FeatureXSAVEOPT,
 768   FeatureSlowSHLD,
 769   FeatureFSGSBase,
 770   FeatureLAHFSAHF,
 771   FeatureMWAITX
 772 ]>;
 773
 774 // TODO: The scheduler model falls to BTVER2 model.
 775 // The znver1 model has to be put in place.
 776 // Zen
 777 def: ProcessorModel<"znver1", BtVer2Model, [
 778   FeatureADX,
 779   FeatureAES,
 780   FeatureAVX2,
 781   FeatureBMI,
 782   FeatureBMI2,
 783   FeatureCLFLUSHOPT,
 784   FeatureCLZERO,
 785   FeatureCMPXCHG16B,
 786   FeatureF16C,
 787   FeatureFMA,
 788   FeatureFSGSBase,
 789   FeatureFXSR,
 790   FeatureFastLZCNT,
 791   FeatureLAHFSAHF,
 792   FeatureLZCNT,
 793   FeatureMMX,
 794   FeatureMOVBE,
 795   FeatureMWAITX,
 796   FeaturePCLMUL,
 797   FeaturePOPCNT,
 798   FeaturePRFCHW,
 799   FeatureRDRAND,
 800   FeatureRDSEED,
 801   FeatureSHA,
 802   FeatureSSE4A,
 803   FeatureSlowSHLD,
 804   FeatureX87,
 805   FeatureXSAVE,
 806   FeatureXSAVEC,
 807   FeatureXSAVEOPT,
 808   FeatureXSAVES]>;
 809
 810 def : Proc<"geode",           [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>;
 811
 812 def : Proc<"winchip-c6",      [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 813 def : Proc<"winchip2",        [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 814 def : Proc<"c3",              [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 815 def : Proc<"c3-2",            [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 816                                FeatureSSE1, FeatureFXSR]>;
 817
 818 // We also provide a generic 64-bit specific x86 processor model which tries to
 819 // be good for modern chips without enabling instruction set encodings past the
 820 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 821 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 822 //
 823 // We currently use the Sandy Bridge model as the default scheduling model as
 824 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 825 // covers a huge swath of x86 processors. If there are specific scheduling
 826 // knobs which need to be tuned differently for AMD chips, we might consider
 827 // forming a common base for them.
 828 def : ProcessorModel<"x86-64", SandyBridgeModel,
 829                      [FeatureX87, FeatureMMX, FeatureSSE2, FeatureFXSR,
 830                       Feature64Bit, FeatureSlowBTMem ]>;
 831
 832 //===----------------------------------------------------------------------===//
 833 // Register File Description
 834 //===----------------------------------------------------------------------===//
 835
 836 include "X86RegisterInfo.td"
 837 include "X86RegisterBanks.td"
 838
 839 //===----------------------------------------------------------------------===//
 840 // Instruction Descriptions
 841 //===----------------------------------------------------------------------===//
 842
 843 include "X86InstrInfo.td"
 844
 845 def X86InstrInfo : InstrInfo;
 846
 847 //===----------------------------------------------------------------------===//
 848 // Calling Conventions
 849 //===----------------------------------------------------------------------===//
 850
 851 include "X86CallingConv.td"
 852
 853
 854 //===----------------------------------------------------------------------===//
 855 // Assembly Parser
 856 //===----------------------------------------------------------------------===//
 857
 858 def ATTAsmParserVariant : AsmParserVariant {
 859   int Variant = 0;
 860
 861   // Variant name.
 862   string Name = "att";
 863
 864   // Discard comments in assembly strings.
 865   string CommentDelimiter = "#";
 866
 867   // Recognize hard coded registers.
 868   string RegisterPrefix = "%";
 869 }
 870
 871 def IntelAsmParserVariant : AsmParserVariant {
 872   int Variant = 1;
 873
 874   // Variant name.
 875   string Name = "intel";
 876
 877   // Discard comments in assembly strings.
 878   string CommentDelimiter = ";";
 879
 880   // Recognize hard coded registers.
 881   string RegisterPrefix = "";
 882 }
 883
 884 //===----------------------------------------------------------------------===//
 885 // Assembly Printers
 886 //===----------------------------------------------------------------------===//
 887
 888 // The X86 target supports two different syntaxes for emitting machine code.
 889 // This is controlled by the -x86-asm-syntax={att|intel}
 890 def ATTAsmWriter : AsmWriter {
 891   string AsmWriterClassName  = "ATTInstPrinter";
 892   int Variant = 0;
 893 }
 894 def IntelAsmWriter : AsmWriter {
 895   string AsmWriterClassName  = "IntelInstPrinter";
 896   int Variant = 1;
 897 }
 898
 899 def X86 : Target {
 900   // Information about the instructions...
 901   let InstructionSet = X86InstrInfo;
 902   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 903   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 904 }