lib/Target/X86/X86.td

   1 //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, refered to
  11 // here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget features.
  21 //===----------------------------------------------------------------------===//
  22
  23 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  24                                       "Enable MMX instructions">;
  25 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  26                                       "Enable SSE instructions",
  27                                       [FeatureMMX]>;
  28 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  29                                       "Enable SSE2 instructions",
  30                                       [FeatureSSE1]>;
  31 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  32                                       "Enable SSE3 instructions",
  33                                       [FeatureSSE2]>;
  34 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  35                                       "Enable SSSE3 instructions",
  36                                       [FeatureSSE3]>;
  37 def FeatureSSE41   : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
  38                                       "Enable SSE 4.1 instructions",
  39                                       [FeatureSSSE3]>;
  40 def FeatureSSE42   : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
  41                                       "Enable SSE 4.2 instructions",
  42                                       [FeatureSSE41]>;
  43 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  44                                       "Enable 3DNow! instructions">;
  45 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  46                                       "Enable 3DNow! Athlon instructions",
  47                                       [Feature3DNow]>;
  48 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  49 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  50 // without disabling 64-bit mode.
  51 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  52                                       "Support 64-bit instructions">;
  53 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  54                                        "Bit testing of memory is slow">;
  55 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  56                                       "Support SSE 4a instructions">;
  57
  58 def FeatureAVX     : SubtargetFeature<"avx", "HasAVX", "true",
  59                                       "Enable AVX instructions">;
  60 def FeatureFMA3    : SubtargetFeature<"fma3", "HasFMA3", "true",
  61                                       "Enable three-operand fused multiple-add">;
  62 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
  63                                       "Enable four-operand fused multiple-add">;
  64
  65 //===----------------------------------------------------------------------===//
  66 // X86 processors supported.
  67 //===----------------------------------------------------------------------===//
  68
  69 class Proc<string Name, list<SubtargetFeature> Features>
  70  : Processor<Name, NoItineraries, Features>;
  71
  72 def : Proc<"generic",         []>;
  73 def : Proc<"i386",            []>;
  74 def : Proc<"i486",            []>;
  75 def : Proc<"i586",            []>;
  76 def : Proc<"pentium",         []>;
  77 def : Proc<"pentium-mmx",     [FeatureMMX]>;
  78 def : Proc<"i686",            []>;
  79 def : Proc<"pentiumpro",      []>;
  80 def : Proc<"pentium2",        [FeatureMMX]>;
  81 def : Proc<"pentium3",        [FeatureSSE1]>;
  82 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
  83 def : Proc<"pentium4",        [FeatureSSE2]>;
  84 def : Proc<"x86-64",          [FeatureSSE2,   Feature64Bit, FeatureSlowBTMem]>;
  85 def : Proc<"yonah",           [FeatureSSE3, FeatureSlowBTMem]>;
  86 def : Proc<"prescott",        [FeatureSSE3, FeatureSlowBTMem]>;
  87 def : Proc<"nocona",          [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
  88 def : Proc<"core2",           [FeatureSSSE3,  Feature64Bit, FeatureSlowBTMem]>;
  89 def : Proc<"penryn",          [FeatureSSE41,  Feature64Bit, FeatureSlowBTMem]>;
  90 def : Proc<"atom",            [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
  91 def : Proc<"corei7",          [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem]>;
  92 def : Proc<"nehalem",         [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem]>;
  93 // Sandy Bridge does not have FMA
  94 def : Proc<"sandybridge",     [FeatureSSE42,  FeatureAVX,   Feature64Bit]>;
  95
  96 def : Proc<"k6",              [FeatureMMX]>;
  97 def : Proc<"k6-2",            [FeatureMMX,    Feature3DNow]>;
  98 def : Proc<"k6-3",            [FeatureMMX,    Feature3DNow]>;
  99 def : Proc<"athlon",          [FeatureMMX,    Feature3DNowA, FeatureSlowBTMem]>;
 100 def : Proc<"athlon-tbird",    [FeatureMMX,    Feature3DNowA, FeatureSlowBTMem]>;
 101 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 102 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 103 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 104 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 105                                FeatureSlowBTMem]>;
 106 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 107                                FeatureSlowBTMem]>;
 108 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 109                                FeatureSlowBTMem]>;
 110 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 111                                FeatureSlowBTMem]>;
 112 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, Feature64Bit,
 113                                FeatureSlowBTMem]>;
 114 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, Feature64Bit,
 115                                FeatureSlowBTMem]>;
 116 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, Feature64Bit,
 117                                FeatureSlowBTMem]>;
 118 def : Proc<"amdfam10",        [FeatureSSE3,   FeatureSSE4A,
 119                                Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
 120 def : Proc<"barcelona",       [FeatureSSE3,   FeatureSSE4A,
 121                                Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
 122
 123 def : Proc<"winchip-c6",      [FeatureMMX]>;
 124 def : Proc<"winchip2",        [FeatureMMX, Feature3DNow]>;
 125 def : Proc<"c3",              [FeatureMMX, Feature3DNow]>;
 126 def : Proc<"c3-2",            [FeatureSSE1]>;
 127
 128 //===----------------------------------------------------------------------===//
 129 // Register File Description
 130 //===----------------------------------------------------------------------===//
 131
 132 include "X86RegisterInfo.td"
 133
 134 //===----------------------------------------------------------------------===//
 135 // Instruction Descriptions
 136 //===----------------------------------------------------------------------===//
 137
 138 include "X86InstrInfo.td"
 139
 140 def X86InstrInfo : InstrInfo {
 141
 142   // Define how we want to layout our TargetSpecific information field... This
 143   // should be kept up-to-date with the fields in the X86InstrInfo.h file.
 144   let TSFlagsFields = ["FormBits",
 145                        "hasOpSizePrefix",
 146                        "hasAdSizePrefix",
 147                        "Prefix",
 148                        "hasREX_WPrefix",
 149                        "ImmTypeBits",
 150                        "FPFormBits",
 151                        "hasLockPrefix",
 152                        "SegOvrBits",
 153                        "Opcode"];
 154   let TSFlagsShifts = [0,
 155                        6,
 156                        7,
 157                        8,
 158                        12,
 159                        13,
 160                        16,
 161                        19,
 162                        20,
 163                        24];
 164 }
 165
 166 //===----------------------------------------------------------------------===//
 167 // Calling Conventions
 168 //===----------------------------------------------------------------------===//
 169
 170 include "X86CallingConv.td"
 171
 172
 173 //===----------------------------------------------------------------------===//
 174 // Assembly Printers
 175 //===----------------------------------------------------------------------===//
 176
 177 // The X86 target supports two different syntaxes for emitting machine code.
 178 // This is controlled by the -x86-asm-syntax={att|intel}
 179 def ATTAsmWriter : AsmWriter {
 180   string AsmWriterClassName  = "ATTAsmPrinter";
 181   int Variant = 0;
 182 }
 183 def IntelAsmWriter : AsmWriter {
 184   string AsmWriterClassName  = "IntelAsmPrinter";
 185   int Variant = 1;
 186 }
 187
 188
 189 def X86 : Target {
 190   // Information about the instructions...
 191   let InstructionSet = X86InstrInfo;
 192
 193   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 194 }