1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/GlobalAlias.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Function.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/LLVMContext.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCExpr.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/ADT/BitVector.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/Dwarf.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Support/raw_ostream.h"
53 using namespace dwarf;
55 STATISTIC(NumTailCalls, "Number of tail calls");
58 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
60 // Forward declarations.
61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
64 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
65 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
66 default: llvm_unreachable("unknown subtarget type");
67 case X86Subtarget::isDarwin:
68 if (TM.getSubtarget<X86Subtarget>().is64Bit())
69 return new X8664_MachoTargetObjectFile();
70 return new TargetLoweringObjectFileMachO();
71 case X86Subtarget::isELF:
72 if (TM.getSubtarget<X86Subtarget>().is64Bit())
73 return new X8664_ELFTargetObjectFile(TM);
74 return new X8632_ELFTargetObjectFile(TM);
75 case X86Subtarget::isMingw:
76 case X86Subtarget::isCygwin:
77 case X86Subtarget::isWindows:
78 return new TargetLoweringObjectFileCOFF();
82 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
83 : TargetLowering(TM, createTLOF(TM)) {
84 Subtarget = &TM.getSubtarget<X86Subtarget>();
85 X86ScalarSSEf64 = Subtarget->hasSSE2();
86 X86ScalarSSEf32 = Subtarget->hasSSE1();
87 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
89 RegInfo = TM.getRegisterInfo();
92 // Set up the TargetLowering object.
94 // X86 is weird, it always uses i8 for shift amounts and setcc results.
95 setShiftAmountType(MVT::i8);
96 setBooleanContents(ZeroOrOneBooleanContent);
97 setSchedulingPreference(Sched::RegPressure);
98 setStackPointerRegisterToSaveRestore(X86StackPtr);
100 if (Subtarget->isTargetDarwin()) {
101 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
102 setUseUnderscoreSetJmp(false);
103 setUseUnderscoreLongJmp(false);
104 } else if (Subtarget->isTargetMingw()) {
105 // MS runtime is weird: it exports _setjmp, but longjmp!
106 setUseUnderscoreSetJmp(true);
107 setUseUnderscoreLongJmp(false);
109 setUseUnderscoreSetJmp(true);
110 setUseUnderscoreLongJmp(true);
113 // Set up the register classes.
114 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
115 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
116 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
117 if (Subtarget->is64Bit())
118 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
120 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
122 // We don't accept any truncstore of integer registers.
123 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
124 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
125 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
126 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
127 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
128 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
130 // SETOEQ and SETUNE require checking two conditions.
131 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
132 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
133 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
135 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
136 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
138 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
140 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
141 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
142 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
144 if (Subtarget->is64Bit()) {
145 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
146 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
147 } else if (!UseSoftFloat) {
148 // We have an algorithm for SSE2->double, and we turn this into a
149 // 64-bit FILD followed by conditional FADD for other targets.
150 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
151 // We have an algorithm for SSE2, and we turn this into a 64-bit
152 // FILD for other targets.
153 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
156 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
158 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
159 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
162 // SSE has no i16 to fp conversion, only i32
163 if (X86ScalarSSEf32) {
164 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
165 // f32 and f64 cases are Legal, f80 case is not
166 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
168 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
169 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
172 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
173 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
176 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
177 // are Legal, f80 is custom lowered.
178 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
179 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
181 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
183 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
184 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
186 if (X86ScalarSSEf32) {
187 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
188 // f32 and f64 cases are Legal, f80 case is not
189 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
191 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
192 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
195 // Handle FP_TO_UINT by promoting the destination to a larger signed
197 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
198 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
199 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
201 if (Subtarget->is64Bit()) {
202 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
203 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
204 } else if (!UseSoftFloat) {
205 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
206 // Expand FP_TO_UINT into a select.
207 // FIXME: We would like to use a Custom expander here eventually to do
208 // the optimal thing for SSE vs. the default expansion in the legalizer.
209 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
211 // With SSE3 we can use fisttpll to convert to a signed i64; without
212 // SSE, we're stuck with a fistpll.
213 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
216 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
217 if (!X86ScalarSSEf64) {
218 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
219 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
220 if (Subtarget->is64Bit()) {
221 setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand);
222 // Without SSE, i64->f64 goes through memory; i64->MMX is Legal.
223 if (Subtarget->hasMMX() && !DisableMMX)
224 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Custom);
226 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand);
230 // Scalar integer divide and remainder are lowered to use operations that
231 // produce two results, to match the available instructions. This exposes
232 // the two-result form to trivial CSE, which is able to combine x/y and x%y
233 // into a single instruction.
235 // Scalar integer multiply-high is also lowered to use two-result
236 // operations, to match the available instructions. However, plain multiply
237 // (low) operations are left as Legal, as there are single-result
238 // instructions for this in x86. Using the two-result multiply instructions
239 // when both high and low results are needed must be arranged by dagcombine.
240 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
241 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
242 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
243 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
244 setOperationAction(ISD::SREM , MVT::i8 , Expand);
245 setOperationAction(ISD::UREM , MVT::i8 , Expand);
246 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
247 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
248 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
249 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
250 setOperationAction(ISD::SREM , MVT::i16 , Expand);
251 setOperationAction(ISD::UREM , MVT::i16 , Expand);
252 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
253 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
254 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
255 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
256 setOperationAction(ISD::SREM , MVT::i32 , Expand);
257 setOperationAction(ISD::UREM , MVT::i32 , Expand);
258 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
259 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
260 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
261 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
262 setOperationAction(ISD::SREM , MVT::i64 , Expand);
263 setOperationAction(ISD::UREM , MVT::i64 , Expand);
265 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
266 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
267 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
268 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
269 if (Subtarget->is64Bit())
270 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
272 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
273 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
274 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
275 setOperationAction(ISD::FREM , MVT::f32 , Expand);
276 setOperationAction(ISD::FREM , MVT::f64 , Expand);
277 setOperationAction(ISD::FREM , MVT::f80 , Expand);
278 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
280 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
281 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
282 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
283 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
284 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
285 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
286 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
287 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
288 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
289 if (Subtarget->is64Bit()) {
290 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
291 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
292 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
295 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
296 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
298 // These should be promoted to a larger select which is supported.
299 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
300 // X86 wants to expand cmov itself.
301 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
302 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
303 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
304 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
305 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
306 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
307 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
308 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
309 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
310 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
311 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
312 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
313 if (Subtarget->is64Bit()) {
314 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
315 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
317 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
320 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
321 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
322 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
323 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
324 if (Subtarget->is64Bit())
325 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
326 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
327 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
328 if (Subtarget->is64Bit()) {
329 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
330 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
331 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
332 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
333 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
335 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
336 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
337 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
338 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
339 if (Subtarget->is64Bit()) {
340 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
341 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
342 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
345 if (Subtarget->hasSSE1())
346 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
348 if (!Subtarget->hasSSE2())
349 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
351 // Expand certain atomics
352 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
353 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
354 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
355 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
357 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
358 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
359 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
360 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
362 if (!Subtarget->is64Bit()) {
363 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
365 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
366 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
367 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
368 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
369 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
372 // FIXME - use subtarget debug flags
373 if (!Subtarget->isTargetDarwin() &&
374 !Subtarget->isTargetELF() &&
375 !Subtarget->isTargetCygMing()) {
376 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
379 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
380 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
381 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
382 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
383 if (Subtarget->is64Bit()) {
384 setExceptionPointerRegister(X86::RAX);
385 setExceptionSelectorRegister(X86::RDX);
387 setExceptionPointerRegister(X86::EAX);
388 setExceptionSelectorRegister(X86::EDX);
390 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
391 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
393 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
395 setOperationAction(ISD::TRAP, MVT::Other, Legal);
397 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
398 setOperationAction(ISD::VASTART , MVT::Other, Custom);
399 setOperationAction(ISD::VAEND , MVT::Other, Expand);
400 if (Subtarget->is64Bit()) {
401 setOperationAction(ISD::VAARG , MVT::Other, Custom);
402 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
404 setOperationAction(ISD::VAARG , MVT::Other, Expand);
405 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
408 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
409 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
410 if (Subtarget->is64Bit())
411 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
412 if (Subtarget->isTargetCygMing())
413 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
415 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
417 if (!UseSoftFloat && X86ScalarSSEf64) {
418 // f32 and f64 use SSE.
419 // Set up the FP register classes.
420 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
421 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
423 // Use ANDPD to simulate FABS.
424 setOperationAction(ISD::FABS , MVT::f64, Custom);
425 setOperationAction(ISD::FABS , MVT::f32, Custom);
427 // Use XORP to simulate FNEG.
428 setOperationAction(ISD::FNEG , MVT::f64, Custom);
429 setOperationAction(ISD::FNEG , MVT::f32, Custom);
431 // Use ANDPD and ORPD to simulate FCOPYSIGN.
432 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
433 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
435 // We don't support sin/cos/fmod
436 setOperationAction(ISD::FSIN , MVT::f64, Expand);
437 setOperationAction(ISD::FCOS , MVT::f64, Expand);
438 setOperationAction(ISD::FSIN , MVT::f32, Expand);
439 setOperationAction(ISD::FCOS , MVT::f32, Expand);
441 // Expand FP immediates into loads from the stack, except for the special
443 addLegalFPImmediate(APFloat(+0.0)); // xorpd
444 addLegalFPImmediate(APFloat(+0.0f)); // xorps
445 } else if (!UseSoftFloat && X86ScalarSSEf32) {
446 // Use SSE for f32, x87 for f64.
447 // Set up the FP register classes.
448 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
449 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
451 // Use ANDPS to simulate FABS.
452 setOperationAction(ISD::FABS , MVT::f32, Custom);
454 // Use XORP to simulate FNEG.
455 setOperationAction(ISD::FNEG , MVT::f32, Custom);
457 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
459 // Use ANDPS and ORPS to simulate FCOPYSIGN.
460 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
461 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
463 // We don't support sin/cos/fmod
464 setOperationAction(ISD::FSIN , MVT::f32, Expand);
465 setOperationAction(ISD::FCOS , MVT::f32, Expand);
467 // Special cases we handle for FP constants.
468 addLegalFPImmediate(APFloat(+0.0f)); // xorps
469 addLegalFPImmediate(APFloat(+0.0)); // FLD0
470 addLegalFPImmediate(APFloat(+1.0)); // FLD1
471 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
472 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
475 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
476 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
478 } else if (!UseSoftFloat) {
479 // f32 and f64 in x87.
480 // Set up the FP register classes.
481 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
482 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
484 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
485 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
486 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
487 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
490 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
491 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
493 addLegalFPImmediate(APFloat(+0.0)); // FLD0
494 addLegalFPImmediate(APFloat(+1.0)); // FLD1
495 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
496 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
497 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
498 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
499 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
500 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
503 // Long double always uses X87.
505 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
506 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
507 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
510 APFloat TmpFlt(+0.0);
511 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
513 addLegalFPImmediate(TmpFlt); // FLD0
515 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
516 APFloat TmpFlt2(+1.0);
517 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
519 addLegalFPImmediate(TmpFlt2); // FLD1
520 TmpFlt2.changeSign();
521 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
525 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
526 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
530 // Always use a library call for pow.
531 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
532 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
533 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
535 setOperationAction(ISD::FLOG, MVT::f80, Expand);
536 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
537 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
538 setOperationAction(ISD::FEXP, MVT::f80, Expand);
539 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
541 // First set operation action for all vector types to either promote
542 // (for widening) or expand (for scalarization). Then we will selectively
543 // turn on ones that can be effectively codegen'd.
544 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
545 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
546 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
561 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
562 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
595 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
599 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
600 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
601 setTruncStoreAction((MVT::SimpleValueType)VT,
602 (MVT::SimpleValueType)InnerVT, Expand);
603 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
604 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
605 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
608 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
609 // with -msoft-float, disable use of MMX as well.
610 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
611 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass, false);
612 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false);
613 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false);
614 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass, false);
615 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false);
617 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
618 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
619 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
620 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
622 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
623 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
624 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
625 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
627 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
628 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
630 setOperationAction(ISD::AND, MVT::v8i8, Promote);
631 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
632 setOperationAction(ISD::AND, MVT::v4i16, Promote);
633 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
634 setOperationAction(ISD::AND, MVT::v2i32, Promote);
635 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
636 setOperationAction(ISD::AND, MVT::v1i64, Legal);
638 setOperationAction(ISD::OR, MVT::v8i8, Promote);
639 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
640 setOperationAction(ISD::OR, MVT::v4i16, Promote);
641 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
642 setOperationAction(ISD::OR, MVT::v2i32, Promote);
643 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
644 setOperationAction(ISD::OR, MVT::v1i64, Legal);
646 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
647 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
648 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
649 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
650 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
651 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
652 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
654 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
655 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
656 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
657 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
658 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
659 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
660 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
661 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
662 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
664 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
665 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
666 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
667 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
668 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
670 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
671 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
672 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
675 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
676 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
677 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
678 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
680 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
682 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
683 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
684 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
685 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
686 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
687 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
688 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
690 if (!X86ScalarSSEf64 && Subtarget->is64Bit()) {
691 setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Custom);
692 setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Custom);
693 setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Custom);
694 setOperationAction(ISD::BIT_CONVERT, MVT::v2f32, Custom);
695 setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Custom);
699 if (!UseSoftFloat && Subtarget->hasSSE1()) {
700 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
702 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
703 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
704 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
705 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
706 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
707 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
708 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
709 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
710 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
711 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
712 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
713 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
716 if (!UseSoftFloat && Subtarget->hasSSE2()) {
717 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
719 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
720 // registers cannot be used even for integer operations.
721 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
722 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
723 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
724 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
726 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
727 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
728 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
729 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
730 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
731 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
732 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
733 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
734 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
735 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
736 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
737 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
738 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
739 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
740 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
741 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
743 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
744 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
745 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
746 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
748 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
749 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
750 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
751 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
752 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
754 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
755 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
756 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
757 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
758 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
760 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
761 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
762 EVT VT = (MVT::SimpleValueType)i;
763 // Do not attempt to custom lower non-power-of-2 vectors
764 if (!isPowerOf2_32(VT.getVectorNumElements()))
766 // Do not attempt to custom lower non-128-bit vectors
767 if (!VT.is128BitVector())
769 setOperationAction(ISD::BUILD_VECTOR,
770 VT.getSimpleVT().SimpleTy, Custom);
771 setOperationAction(ISD::VECTOR_SHUFFLE,
772 VT.getSimpleVT().SimpleTy, Custom);
773 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
774 VT.getSimpleVT().SimpleTy, Custom);
777 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
778 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
779 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
780 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
781 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
782 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
784 if (Subtarget->is64Bit()) {
785 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
789 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
790 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
791 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
794 // Do not attempt to promote non-128-bit vectors
795 if (!VT.is128BitVector()) {
799 setOperationAction(ISD::AND, SVT, Promote);
800 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
801 setOperationAction(ISD::OR, SVT, Promote);
802 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
803 setOperationAction(ISD::XOR, SVT, Promote);
804 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
805 setOperationAction(ISD::LOAD, SVT, Promote);
806 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
807 setOperationAction(ISD::SELECT, SVT, Promote);
808 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
811 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
813 // Custom lower v2i64 and v2f64 selects.
814 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
815 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
816 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
817 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
819 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
820 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
821 if (!DisableMMX && Subtarget->hasMMX()) {
822 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
823 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
827 if (Subtarget->hasSSE41()) {
828 // FIXME: Do we need to handle scalar-to-vector here?
829 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
831 // i8 and i16 vectors are custom , because the source register and source
832 // source memory operand types are not the same width. f32 vectors are
833 // custom since the immediate controlling the insert encodes additional
835 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
837 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
838 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
840 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
841 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
842 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
843 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
845 if (Subtarget->is64Bit()) {
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
847 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
851 if (Subtarget->hasSSE42()) {
852 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
855 if (!UseSoftFloat && Subtarget->hasAVX()) {
856 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
857 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
858 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
859 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
861 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
862 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
863 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
864 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
865 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
866 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
867 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
868 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
869 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
870 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
871 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
872 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
873 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
874 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
875 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
877 // Operations to consider commented out -v16i16 v32i8
878 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
879 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
880 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
881 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
882 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
883 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
884 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
885 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
886 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
887 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
888 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
889 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
890 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
891 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
893 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
894 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
895 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
896 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
898 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
899 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
900 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
902 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
904 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
905 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
906 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
907 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
908 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
909 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
912 // Not sure we want to do this since there are no 256-bit integer
915 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
916 // This includes 256-bit vectors
917 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
918 EVT VT = (MVT::SimpleValueType)i;
920 // Do not attempt to custom lower non-power-of-2 vectors
921 if (!isPowerOf2_32(VT.getVectorNumElements()))
924 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
925 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
926 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
929 if (Subtarget->is64Bit()) {
930 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
931 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
936 // Not sure we want to do this since there are no 256-bit integer
939 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
940 // Including 256-bit vectors
941 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
942 EVT VT = (MVT::SimpleValueType)i;
944 if (!VT.is256BitVector()) {
947 setOperationAction(ISD::AND, VT, Promote);
948 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
949 setOperationAction(ISD::OR, VT, Promote);
950 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
951 setOperationAction(ISD::XOR, VT, Promote);
952 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
953 setOperationAction(ISD::LOAD, VT, Promote);
954 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
955 setOperationAction(ISD::SELECT, VT, Promote);
956 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
959 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
963 // We want to custom lower some of our intrinsics.
964 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
966 // Add/Sub/Mul with overflow operations are custom lowered.
967 setOperationAction(ISD::SADDO, MVT::i32, Custom);
968 setOperationAction(ISD::SADDO, MVT::i64, Custom);
969 setOperationAction(ISD::UADDO, MVT::i32, Custom);
970 setOperationAction(ISD::UADDO, MVT::i64, Custom);
971 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
972 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
973 setOperationAction(ISD::USUBO, MVT::i32, Custom);
974 setOperationAction(ISD::USUBO, MVT::i64, Custom);
975 setOperationAction(ISD::SMULO, MVT::i32, Custom);
976 setOperationAction(ISD::SMULO, MVT::i64, Custom);
978 if (!Subtarget->is64Bit()) {
979 // These libcalls are not available in 32-bit.
980 setLibcallName(RTLIB::SHL_I128, 0);
981 setLibcallName(RTLIB::SRL_I128, 0);
982 setLibcallName(RTLIB::SRA_I128, 0);
985 // We have target-specific dag combine patterns for the following nodes:
986 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
987 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
988 setTargetDAGCombine(ISD::BUILD_VECTOR);
989 setTargetDAGCombine(ISD::SELECT);
990 setTargetDAGCombine(ISD::SHL);
991 setTargetDAGCombine(ISD::SRA);
992 setTargetDAGCombine(ISD::SRL);
993 setTargetDAGCombine(ISD::OR);
994 setTargetDAGCombine(ISD::STORE);
995 setTargetDAGCombine(ISD::MEMBARRIER);
996 setTargetDAGCombine(ISD::ZERO_EXTEND);
997 if (Subtarget->is64Bit())
998 setTargetDAGCombine(ISD::MUL);
1000 computeRegisterProperties();
1002 // FIXME: These should be based on subtarget info. Plus, the values should
1003 // be smaller when we are in optimizing for size mode.
1004 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1005 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1006 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1007 setPrefLoopAlignment(16);
1008 benefitFromCodePlacementOpt = true;
1012 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1017 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1018 /// the desired ByVal argument alignment.
1019 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1022 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1023 if (VTy->getBitWidth() == 128)
1025 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1026 unsigned EltAlign = 0;
1027 getMaxByValAlign(ATy->getElementType(), EltAlign);
1028 if (EltAlign > MaxAlign)
1029 MaxAlign = EltAlign;
1030 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1031 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1032 unsigned EltAlign = 0;
1033 getMaxByValAlign(STy->getElementType(i), EltAlign);
1034 if (EltAlign > MaxAlign)
1035 MaxAlign = EltAlign;
1043 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1044 /// function arguments in the caller parameter area. For X86, aggregates
1045 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1046 /// are at 4-byte boundaries.
1047 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1048 if (Subtarget->is64Bit()) {
1049 // Max of 8 and alignment of type.
1050 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1057 if (Subtarget->hasSSE1())
1058 getMaxByValAlign(Ty, Align);
1062 /// getOptimalMemOpType - Returns the target specific optimal type for load
1063 /// and store operations as a result of memset, memcpy, and memmove
1064 /// lowering. If DstAlign is zero that means it's safe to destination
1065 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1066 /// means there isn't a need to check it against alignment requirement,
1067 /// probably because the source does not need to be loaded. If
1068 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1069 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1070 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1071 /// constant so it does not need to be loaded.
1072 /// It returns EVT::Other if the type should be determined using generic
1073 /// target-independent logic.
1075 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1076 unsigned DstAlign, unsigned SrcAlign,
1077 bool NonScalarIntSafe,
1079 MachineFunction &MF) const {
1080 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1081 // linux. This is because the stack realignment code can't handle certain
1082 // cases like PR2962. This should be removed when PR2962 is fixed.
1083 const Function *F = MF.getFunction();
1084 if (NonScalarIntSafe &&
1085 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1087 (Subtarget->isUnalignedMemAccessFast() ||
1088 ((DstAlign == 0 || DstAlign >= 16) &&
1089 (SrcAlign == 0 || SrcAlign >= 16))) &&
1090 Subtarget->getStackAlignment() >= 16) {
1091 if (Subtarget->hasSSE2())
1093 if (Subtarget->hasSSE1())
1095 } else if (!MemcpyStrSrc && Size >= 8 &&
1096 !Subtarget->is64Bit() &&
1097 Subtarget->getStackAlignment() >= 8 &&
1098 Subtarget->hasSSE2()) {
1099 // Do not use f64 to lower memcpy if source is string constant. It's
1100 // better to use i32 to avoid the loads.
1104 if (Subtarget->is64Bit() && Size >= 8)
1109 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1110 /// current function. The returned value is a member of the
1111 /// MachineJumpTableInfo::JTEntryKind enum.
1112 unsigned X86TargetLowering::getJumpTableEncoding() const {
1113 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1115 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1116 Subtarget->isPICStyleGOT())
1117 return MachineJumpTableInfo::EK_Custom32;
1119 // Otherwise, use the normal jump table encoding heuristics.
1120 return TargetLowering::getJumpTableEncoding();
1123 /// getPICBaseSymbol - Return the X86-32 PIC base.
1125 X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1126 MCContext &Ctx) const {
1127 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1128 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+
1129 Twine(MF->getFunctionNumber())+"$pb");
1134 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1135 const MachineBasicBlock *MBB,
1136 unsigned uid,MCContext &Ctx) const{
1137 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1138 Subtarget->isPICStyleGOT());
1139 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1141 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1142 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1145 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1147 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1148 SelectionDAG &DAG) const {
1149 if (!Subtarget->is64Bit())
1150 // This doesn't have DebugLoc associated with it, but is not really the
1151 // same as a Register.
1152 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1156 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1157 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1159 const MCExpr *X86TargetLowering::
1160 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1161 MCContext &Ctx) const {
1162 // X86-64 uses RIP relative addressing based on the jump table label.
1163 if (Subtarget->isPICStyleRIPRel())
1164 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1166 // Otherwise, the reference is relative to the PIC base.
1167 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1170 /// getFunctionAlignment - Return the Log2 alignment of this function.
1171 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1172 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1175 //===----------------------------------------------------------------------===//
1176 // Return Value Calling Convention Implementation
1177 //===----------------------------------------------------------------------===//
1179 #include "X86GenCallingConv.inc"
1182 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1183 const SmallVectorImpl<EVT> &OutTys,
1184 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1185 SelectionDAG &DAG) const {
1186 SmallVector<CCValAssign, 16> RVLocs;
1187 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1188 RVLocs, *DAG.getContext());
1189 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
1193 X86TargetLowering::LowerReturn(SDValue Chain,
1194 CallingConv::ID CallConv, bool isVarArg,
1195 const SmallVectorImpl<ISD::OutputArg> &Outs,
1196 DebugLoc dl, SelectionDAG &DAG) const {
1197 MachineFunction &MF = DAG.getMachineFunction();
1198 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1200 SmallVector<CCValAssign, 16> RVLocs;
1201 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1202 RVLocs, *DAG.getContext());
1203 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1205 // Add the regs to the liveout set for the function.
1206 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1207 for (unsigned i = 0; i != RVLocs.size(); ++i)
1208 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1209 MRI.addLiveOut(RVLocs[i].getLocReg());
1213 SmallVector<SDValue, 6> RetOps;
1214 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1215 // Operand #1 = Bytes To Pop
1216 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1219 // Copy the result values into the output registers.
1220 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1221 CCValAssign &VA = RVLocs[i];
1222 assert(VA.isRegLoc() && "Can only return in registers!");
1223 SDValue ValToCopy = Outs[i].Val;
1225 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1226 // the RET instruction and handled by the FP Stackifier.
1227 if (VA.getLocReg() == X86::ST0 ||
1228 VA.getLocReg() == X86::ST1) {
1229 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1230 // change the value to the FP stack register class.
1231 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1232 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1233 RetOps.push_back(ValToCopy);
1234 // Don't emit a copytoreg.
1238 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1239 // which is returned in RAX / RDX.
1240 if (Subtarget->is64Bit()) {
1241 EVT ValVT = ValToCopy.getValueType();
1242 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1243 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1244 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1245 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1249 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1250 Flag = Chain.getValue(1);
1253 // The x86-64 ABI for returning structs by value requires that we copy
1254 // the sret argument into %rax for the return. We saved the argument into
1255 // a virtual register in the entry block, so now we copy the value out
1257 if (Subtarget->is64Bit() &&
1258 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1259 MachineFunction &MF = DAG.getMachineFunction();
1260 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1261 unsigned Reg = FuncInfo->getSRetReturnReg();
1263 "SRetReturnReg should have been set in LowerFormalArguments().");
1264 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1266 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1267 Flag = Chain.getValue(1);
1269 // RAX now acts like a return value.
1270 MRI.addLiveOut(X86::RAX);
1273 RetOps[0] = Chain; // Update chain.
1275 // Add the flag if we have it.
1277 RetOps.push_back(Flag);
1279 return DAG.getNode(X86ISD::RET_FLAG, dl,
1280 MVT::Other, &RetOps[0], RetOps.size());
1283 /// LowerCallResult - Lower the result values of a call into the
1284 /// appropriate copies out of appropriate physical registers.
1287 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1288 CallingConv::ID CallConv, bool isVarArg,
1289 const SmallVectorImpl<ISD::InputArg> &Ins,
1290 DebugLoc dl, SelectionDAG &DAG,
1291 SmallVectorImpl<SDValue> &InVals) const {
1293 // Assign locations to each value returned by this call.
1294 SmallVector<CCValAssign, 16> RVLocs;
1295 bool Is64Bit = Subtarget->is64Bit();
1296 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1297 RVLocs, *DAG.getContext());
1298 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1300 // Copy all of the result registers out of their specified physreg.
1301 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1302 CCValAssign &VA = RVLocs[i];
1303 EVT CopyVT = VA.getValVT();
1305 // If this is x86-64, and we disabled SSE, we can't return FP values
1306 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1307 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1308 report_fatal_error("SSE register return with SSE disabled");
1311 // If this is a call to a function that returns an fp value on the floating
1312 // point stack, but where we prefer to use the value in xmm registers, copy
1313 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1314 if ((VA.getLocReg() == X86::ST0 ||
1315 VA.getLocReg() == X86::ST1) &&
1316 isScalarFPTypeInSSEReg(VA.getValVT())) {
1321 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1322 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1323 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1324 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1325 MVT::v2i64, InFlag).getValue(1);
1326 Val = Chain.getValue(0);
1327 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1328 Val, DAG.getConstant(0, MVT::i64));
1330 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1331 MVT::i64, InFlag).getValue(1);
1332 Val = Chain.getValue(0);
1334 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1336 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1337 CopyVT, InFlag).getValue(1);
1338 Val = Chain.getValue(0);
1340 InFlag = Chain.getValue(2);
1342 if (CopyVT != VA.getValVT()) {
1343 // Round the F80 the right size, which also moves to the appropriate xmm
1345 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1346 // This truncation won't change the value.
1347 DAG.getIntPtrConstant(1));
1350 InVals.push_back(Val);
1357 //===----------------------------------------------------------------------===//
1358 // C & StdCall & Fast Calling Convention implementation
1359 //===----------------------------------------------------------------------===//
1360 // StdCall calling convention seems to be standard for many Windows' API
1361 // routines and around. It differs from C calling convention just a little:
1362 // callee should clean up the stack, not caller. Symbols should be also
1363 // decorated in some fancy way :) It doesn't support any vector arguments.
1364 // For info on fast calling convention see Fast Calling Convention (tail call)
1365 // implementation LowerX86_32FastCCCallTo.
1367 /// CallIsStructReturn - Determines whether a call uses struct return
1369 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1373 return Outs[0].Flags.isSRet();
1376 /// ArgsAreStructReturn - Determines whether a function uses struct
1377 /// return semantics.
1379 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1383 return Ins[0].Flags.isSRet();
1386 /// IsCalleePop - Determines whether the callee is required to pop its
1387 /// own arguments. Callee pop is necessary to support tail calls.
1388 bool X86TargetLowering::IsCalleePop(bool IsVarArg,
1389 CallingConv::ID CallingConv) const {
1393 switch (CallingConv) {
1396 case CallingConv::X86_StdCall:
1397 return !Subtarget->is64Bit();
1398 case CallingConv::X86_FastCall:
1399 return !Subtarget->is64Bit();
1400 case CallingConv::X86_ThisCall:
1401 return !Subtarget->is64Bit();
1402 case CallingConv::Fast:
1403 return GuaranteedTailCallOpt;
1404 case CallingConv::GHC:
1405 return GuaranteedTailCallOpt;
1409 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1410 /// given CallingConvention value.
1411 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1412 if (Subtarget->is64Bit()) {
1413 if (CC == CallingConv::GHC)
1414 return CC_X86_64_GHC;
1415 else if (Subtarget->isTargetWin64())
1416 return CC_X86_Win64_C;
1421 if (CC == CallingConv::X86_FastCall)
1422 return CC_X86_32_FastCall;
1423 else if (CC == CallingConv::X86_ThisCall)
1424 return CC_X86_32_ThisCall;
1425 else if (CC == CallingConv::Fast)
1426 return CC_X86_32_FastCC;
1427 else if (CC == CallingConv::GHC)
1428 return CC_X86_32_GHC;
1433 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1434 /// by "Src" to address "Dst" with size and alignment information specified by
1435 /// the specific parameter attribute. The copy will be passed as a byval
1436 /// function parameter.
1438 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1439 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1441 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1442 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1443 /*isVolatile*/false, /*AlwaysInline=*/true,
1447 /// IsTailCallConvention - Return true if the calling convention is one that
1448 /// supports tail call optimization.
1449 static bool IsTailCallConvention(CallingConv::ID CC) {
1450 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1453 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1454 /// a tailcall target by changing its ABI.
1455 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1456 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1460 X86TargetLowering::LowerMemArgument(SDValue Chain,
1461 CallingConv::ID CallConv,
1462 const SmallVectorImpl<ISD::InputArg> &Ins,
1463 DebugLoc dl, SelectionDAG &DAG,
1464 const CCValAssign &VA,
1465 MachineFrameInfo *MFI,
1467 // Create the nodes corresponding to a load from this parameter slot.
1468 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1469 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1470 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1473 // If value is passed by pointer we have address passed instead of the value
1475 if (VA.getLocInfo() == CCValAssign::Indirect)
1476 ValVT = VA.getLocVT();
1478 ValVT = VA.getValVT();
1480 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1481 // changed with more analysis.
1482 // In case of tail call optimization mark all arguments mutable. Since they
1483 // could be overwritten by lowering of arguments in case of a tail call.
1484 if (Flags.isByVal()) {
1485 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1486 VA.getLocMemOffset(), isImmutable, false);
1487 return DAG.getFrameIndex(FI, getPointerTy());
1489 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1490 VA.getLocMemOffset(), isImmutable, false);
1491 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1492 return DAG.getLoad(ValVT, dl, Chain, FIN,
1493 PseudoSourceValue::getFixedStack(FI), 0,
1499 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1500 CallingConv::ID CallConv,
1502 const SmallVectorImpl<ISD::InputArg> &Ins,
1505 SmallVectorImpl<SDValue> &InVals)
1507 MachineFunction &MF = DAG.getMachineFunction();
1508 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1510 const Function* Fn = MF.getFunction();
1511 if (Fn->hasExternalLinkage() &&
1512 Subtarget->isTargetCygMing() &&
1513 Fn->getName() == "main")
1514 FuncInfo->setForceFramePointer(true);
1516 MachineFrameInfo *MFI = MF.getFrameInfo();
1517 bool Is64Bit = Subtarget->is64Bit();
1518 bool IsWin64 = Subtarget->isTargetWin64();
1520 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1521 "Var args not supported with calling convention fastcc or ghc");
1523 // Assign locations to all of the incoming arguments.
1524 SmallVector<CCValAssign, 16> ArgLocs;
1525 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1526 ArgLocs, *DAG.getContext());
1527 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1529 unsigned LastVal = ~0U;
1531 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1532 CCValAssign &VA = ArgLocs[i];
1533 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1535 assert(VA.getValNo() != LastVal &&
1536 "Don't support value assigned to multiple locs yet");
1537 LastVal = VA.getValNo();
1539 if (VA.isRegLoc()) {
1540 EVT RegVT = VA.getLocVT();
1541 TargetRegisterClass *RC = NULL;
1542 if (RegVT == MVT::i32)
1543 RC = X86::GR32RegisterClass;
1544 else if (Is64Bit && RegVT == MVT::i64)
1545 RC = X86::GR64RegisterClass;
1546 else if (RegVT == MVT::f32)
1547 RC = X86::FR32RegisterClass;
1548 else if (RegVT == MVT::f64)
1549 RC = X86::FR64RegisterClass;
1550 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1551 RC = X86::VR128RegisterClass;
1552 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1553 RC = X86::VR64RegisterClass;
1555 llvm_unreachable("Unknown argument type!");
1557 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1558 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1560 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1561 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1563 if (VA.getLocInfo() == CCValAssign::SExt)
1564 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1565 DAG.getValueType(VA.getValVT()));
1566 else if (VA.getLocInfo() == CCValAssign::ZExt)
1567 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1568 DAG.getValueType(VA.getValVT()));
1569 else if (VA.getLocInfo() == CCValAssign::BCvt)
1570 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1572 if (VA.isExtInLoc()) {
1573 // Handle MMX values passed in XMM regs.
1574 if (RegVT.isVector()) {
1575 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1576 ArgValue, DAG.getConstant(0, MVT::i64));
1577 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1579 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1582 assert(VA.isMemLoc());
1583 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1586 // If value is passed via pointer - do a load.
1587 if (VA.getLocInfo() == CCValAssign::Indirect)
1588 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0,
1591 InVals.push_back(ArgValue);
1594 // The x86-64 ABI for returning structs by value requires that we copy
1595 // the sret argument into %rax for the return. Save the argument into
1596 // a virtual register so that we can access it from the return points.
1597 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1598 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1599 unsigned Reg = FuncInfo->getSRetReturnReg();
1601 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1602 FuncInfo->setSRetReturnReg(Reg);
1604 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1605 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1608 unsigned StackSize = CCInfo.getNextStackOffset();
1609 // Align stack specially for tail calls.
1610 if (FuncIsMadeTailCallSafe(CallConv))
1611 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1613 // If the function takes variable number of arguments, make a frame index for
1614 // the start of the first vararg value... for expansion of llvm.va_start.
1616 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1617 CallConv != CallingConv::X86_ThisCall)) {
1618 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,
1622 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1624 // FIXME: We should really autogenerate these arrays
1625 static const unsigned GPR64ArgRegsWin64[] = {
1626 X86::RCX, X86::RDX, X86::R8, X86::R9
1628 static const unsigned XMMArgRegsWin64[] = {
1629 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1631 static const unsigned GPR64ArgRegs64Bit[] = {
1632 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1634 static const unsigned XMMArgRegs64Bit[] = {
1635 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1636 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1638 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1641 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1642 GPR64ArgRegs = GPR64ArgRegsWin64;
1643 XMMArgRegs = XMMArgRegsWin64;
1645 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1646 GPR64ArgRegs = GPR64ArgRegs64Bit;
1647 XMMArgRegs = XMMArgRegs64Bit;
1649 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1651 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1654 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1655 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1656 "SSE register cannot be used when SSE is disabled!");
1657 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1658 "SSE register cannot be used when SSE is disabled!");
1659 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1660 // Kernel mode asks for SSE to be disabled, so don't push them
1662 TotalNumXMMRegs = 0;
1664 // For X86-64, if there are vararg parameters that are passed via
1665 // registers, then we must store them to their spots on the stack so they
1666 // may be loaded by deferencing the result of va_next.
1667 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1668 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1669 FuncInfo->setRegSaveFrameIndex(
1670 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1673 // Store the integer parameter registers.
1674 SmallVector<SDValue, 8> MemOps;
1675 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1677 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1678 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1679 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1680 DAG.getIntPtrConstant(Offset));
1681 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1682 X86::GR64RegisterClass);
1683 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1685 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1686 PseudoSourceValue::getFixedStack(
1687 FuncInfo->getRegSaveFrameIndex()),
1688 Offset, false, false, 0);
1689 MemOps.push_back(Store);
1693 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1694 // Now store the XMM (fp + vector) parameter registers.
1695 SmallVector<SDValue, 11> SaveXMMOps;
1696 SaveXMMOps.push_back(Chain);
1698 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1699 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1700 SaveXMMOps.push_back(ALVal);
1702 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1703 FuncInfo->getRegSaveFrameIndex()));
1704 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1705 FuncInfo->getVarArgsFPOffset()));
1707 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1708 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1709 X86::VR128RegisterClass);
1710 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1711 SaveXMMOps.push_back(Val);
1713 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1715 &SaveXMMOps[0], SaveXMMOps.size()));
1718 if (!MemOps.empty())
1719 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1720 &MemOps[0], MemOps.size());
1724 // Some CCs need callee pop.
1725 if (IsCalleePop(isVarArg, CallConv)) {
1726 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1728 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1729 // If this is an sret function, the return should pop the hidden pointer.
1730 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1731 FuncInfo->setBytesToPopOnReturn(4);
1735 // RegSaveFrameIndex is X86-64 only.
1736 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1737 if (CallConv == CallingConv::X86_FastCall ||
1738 CallConv == CallingConv::X86_ThisCall)
1739 // fastcc functions can't have varargs.
1740 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1747 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1748 SDValue StackPtr, SDValue Arg,
1749 DebugLoc dl, SelectionDAG &DAG,
1750 const CCValAssign &VA,
1751 ISD::ArgFlagsTy Flags) const {
1752 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1753 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1754 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1755 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1756 if (Flags.isByVal()) {
1757 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1759 return DAG.getStore(Chain, dl, Arg, PtrOff,
1760 PseudoSourceValue::getStack(), LocMemOffset,
1764 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1765 /// optimization is performed and it is required.
1767 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1768 SDValue &OutRetAddr, SDValue Chain,
1769 bool IsTailCall, bool Is64Bit,
1770 int FPDiff, DebugLoc dl) const {
1771 // Adjust the Return address stack slot.
1772 EVT VT = getPointerTy();
1773 OutRetAddr = getReturnAddressFrameIndex(DAG);
1775 // Load the "old" Return address.
1776 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0);
1777 return SDValue(OutRetAddr.getNode(), 1);
1780 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1781 /// optimization is performed and it is required (FPDiff!=0).
1783 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1784 SDValue Chain, SDValue RetAddrFrIdx,
1785 bool Is64Bit, int FPDiff, DebugLoc dl) {
1786 // Store the return address to the appropriate stack slot.
1787 if (!FPDiff) return Chain;
1788 // Calculate the new stack slot for the return address.
1789 int SlotSize = Is64Bit ? 8 : 4;
1790 int NewReturnAddrFI =
1791 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false, false);
1792 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1793 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1794 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1795 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0,
1801 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1802 CallingConv::ID CallConv, bool isVarArg,
1804 const SmallVectorImpl<ISD::OutputArg> &Outs,
1805 const SmallVectorImpl<ISD::InputArg> &Ins,
1806 DebugLoc dl, SelectionDAG &DAG,
1807 SmallVectorImpl<SDValue> &InVals) const {
1808 MachineFunction &MF = DAG.getMachineFunction();
1809 bool Is64Bit = Subtarget->is64Bit();
1810 bool IsStructRet = CallIsStructReturn(Outs);
1811 bool IsSibcall = false;
1814 // Check if it's really possible to do a tail call.
1815 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1816 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1819 // Sibcalls are automatically detected tailcalls which do not require
1821 if (!GuaranteedTailCallOpt && isTailCall)
1828 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1829 "Var args not supported with calling convention fastcc or ghc");
1831 // Analyze operands of the call, assigning locations to each operand.
1832 SmallVector<CCValAssign, 16> ArgLocs;
1833 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1834 ArgLocs, *DAG.getContext());
1835 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1837 // Get a count of how many bytes are to be pushed on the stack.
1838 unsigned NumBytes = CCInfo.getNextStackOffset();
1840 // This is a sibcall. The memory operands are available in caller's
1841 // own caller's stack.
1843 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1844 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1847 if (isTailCall && !IsSibcall) {
1848 // Lower arguments at fp - stackoffset + fpdiff.
1849 unsigned NumBytesCallerPushed =
1850 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1851 FPDiff = NumBytesCallerPushed - NumBytes;
1853 // Set the delta of movement of the returnaddr stackslot.
1854 // But only set if delta is greater than previous delta.
1855 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1856 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1860 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1862 SDValue RetAddrFrIdx;
1863 // Load return adress for tail calls.
1864 if (isTailCall && FPDiff)
1865 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1866 Is64Bit, FPDiff, dl);
1868 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1869 SmallVector<SDValue, 8> MemOpChains;
1872 // Walk the register/memloc assignments, inserting copies/loads. In the case
1873 // of tail call optimization arguments are handle later.
1874 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1875 CCValAssign &VA = ArgLocs[i];
1876 EVT RegVT = VA.getLocVT();
1877 SDValue Arg = Outs[i].Val;
1878 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1879 bool isByVal = Flags.isByVal();
1881 // Promote the value if needed.
1882 switch (VA.getLocInfo()) {
1883 default: llvm_unreachable("Unknown loc info!");
1884 case CCValAssign::Full: break;
1885 case CCValAssign::SExt:
1886 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1888 case CCValAssign::ZExt:
1889 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1891 case CCValAssign::AExt:
1892 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1893 // Special case: passing MMX values in XMM registers.
1894 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1895 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1896 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1898 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1900 case CCValAssign::BCvt:
1901 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1903 case CCValAssign::Indirect: {
1904 // Store the argument.
1905 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1906 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1907 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1908 PseudoSourceValue::getFixedStack(FI), 0,
1915 if (VA.isRegLoc()) {
1916 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1917 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1918 assert(VA.isMemLoc());
1919 if (StackPtr.getNode() == 0)
1920 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1921 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1922 dl, DAG, VA, Flags));
1926 if (!MemOpChains.empty())
1927 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1928 &MemOpChains[0], MemOpChains.size());
1930 // Build a sequence of copy-to-reg nodes chained together with token chain
1931 // and flag operands which copy the outgoing args into registers.
1933 // Tail call byval lowering might overwrite argument registers so in case of
1934 // tail call optimization the copies to registers are lowered later.
1936 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1937 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1938 RegsToPass[i].second, InFlag);
1939 InFlag = Chain.getValue(1);
1942 if (Subtarget->isPICStyleGOT()) {
1943 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1946 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1947 DAG.getNode(X86ISD::GlobalBaseReg,
1948 DebugLoc(), getPointerTy()),
1950 InFlag = Chain.getValue(1);
1952 // If we are tail calling and generating PIC/GOT style code load the
1953 // address of the callee into ECX. The value in ecx is used as target of
1954 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1955 // for tail calls on PIC/GOT architectures. Normally we would just put the
1956 // address of GOT into ebx and then call target@PLT. But for tail calls
1957 // ebx would be restored (since ebx is callee saved) before jumping to the
1960 // Note: The actual moving to ECX is done further down.
1961 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1962 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1963 !G->getGlobal()->hasProtectedVisibility())
1964 Callee = LowerGlobalAddress(Callee, DAG);
1965 else if (isa<ExternalSymbolSDNode>(Callee))
1966 Callee = LowerExternalSymbol(Callee, DAG);
1970 if (Is64Bit && isVarArg) {
1971 // From AMD64 ABI document:
1972 // For calls that may call functions that use varargs or stdargs
1973 // (prototype-less calls or calls to functions containing ellipsis (...) in
1974 // the declaration) %al is used as hidden argument to specify the number
1975 // of SSE registers used. The contents of %al do not need to match exactly
1976 // the number of registers, but must be an ubound on the number of SSE
1977 // registers used and is in the range 0 - 8 inclusive.
1979 // FIXME: Verify this on Win64
1980 // Count the number of XMM registers allocated.
1981 static const unsigned XMMArgRegs[] = {
1982 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1983 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1985 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1986 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1987 && "SSE registers cannot be used when SSE is disabled");
1989 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1990 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1991 InFlag = Chain.getValue(1);
1995 // For tail calls lower the arguments to the 'real' stack slot.
1997 // Force all the incoming stack arguments to be loaded from the stack
1998 // before any new outgoing arguments are stored to the stack, because the
1999 // outgoing stack slots may alias the incoming argument stack slots, and
2000 // the alias isn't otherwise explicit. This is slightly more conservative
2001 // than necessary, because it means that each store effectively depends
2002 // on every argument instead of just those arguments it would clobber.
2003 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2005 SmallVector<SDValue, 8> MemOpChains2;
2008 // Do not flag preceeding copytoreg stuff together with the following stuff.
2010 if (GuaranteedTailCallOpt) {
2011 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2012 CCValAssign &VA = ArgLocs[i];
2015 assert(VA.isMemLoc());
2016 SDValue Arg = Outs[i].Val;
2017 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2018 // Create frame index.
2019 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2020 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2021 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false);
2022 FIN = DAG.getFrameIndex(FI, getPointerTy());
2024 if (Flags.isByVal()) {
2025 // Copy relative to framepointer.
2026 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2027 if (StackPtr.getNode() == 0)
2028 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2030 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2032 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2036 // Store relative to framepointer.
2037 MemOpChains2.push_back(
2038 DAG.getStore(ArgChain, dl, Arg, FIN,
2039 PseudoSourceValue::getFixedStack(FI), 0,
2045 if (!MemOpChains2.empty())
2046 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2047 &MemOpChains2[0], MemOpChains2.size());
2049 // Copy arguments to their registers.
2050 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2051 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2052 RegsToPass[i].second, InFlag);
2053 InFlag = Chain.getValue(1);
2057 // Store the return address to the appropriate stack slot.
2058 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2062 bool WasGlobalOrExternal = false;
2063 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2064 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2065 // In the 64-bit large code model, we have to make all calls
2066 // through a register, since the call instruction's 32-bit
2067 // pc-relative offset may not be large enough to hold the whole
2069 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2070 WasGlobalOrExternal = true;
2071 // If the callee is a GlobalAddress node (quite common, every direct call
2072 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2075 // We should use extra load for direct calls to dllimported functions in
2077 const GlobalValue *GV = G->getGlobal();
2078 if (!GV->hasDLLImportLinkage()) {
2079 unsigned char OpFlags = 0;
2081 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2082 // external symbols most go through the PLT in PIC mode. If the symbol
2083 // has hidden or protected visibility, or if it is static or local, then
2084 // we don't need to use the PLT - we can directly call it.
2085 if (Subtarget->isTargetELF() &&
2086 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2087 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2088 OpFlags = X86II::MO_PLT;
2089 } else if (Subtarget->isPICStyleStubAny() &&
2090 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2091 Subtarget->getDarwinVers() < 9) {
2092 // PC-relative references to external symbols should go through $stub,
2093 // unless we're building with the leopard linker or later, which
2094 // automatically synthesizes these stubs.
2095 OpFlags = X86II::MO_DARWIN_STUB;
2098 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
2099 G->getOffset(), OpFlags);
2101 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2102 WasGlobalOrExternal = true;
2103 unsigned char OpFlags = 0;
2105 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2106 // symbols should go through the PLT.
2107 if (Subtarget->isTargetELF() &&
2108 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2109 OpFlags = X86II::MO_PLT;
2110 } else if (Subtarget->isPICStyleStubAny() &&
2111 Subtarget->getDarwinVers() < 9) {
2112 // PC-relative references to external symbols should go through $stub,
2113 // unless we're building with the leopard linker or later, which
2114 // automatically synthesizes these stubs.
2115 OpFlags = X86II::MO_DARWIN_STUB;
2118 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2122 // Returns a chain & a flag for retval copy to use.
2123 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2124 SmallVector<SDValue, 8> Ops;
2126 if (!IsSibcall && isTailCall) {
2127 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2128 DAG.getIntPtrConstant(0, true), InFlag);
2129 InFlag = Chain.getValue(1);
2132 Ops.push_back(Chain);
2133 Ops.push_back(Callee);
2136 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2138 // Add argument registers to the end of the list so that they are known live
2140 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2141 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2142 RegsToPass[i].second.getValueType()));
2144 // Add an implicit use GOT pointer in EBX.
2145 if (!isTailCall && Subtarget->isPICStyleGOT())
2146 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2148 // Add an implicit use of AL for x86 vararg functions.
2149 if (Is64Bit && isVarArg)
2150 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2152 if (InFlag.getNode())
2153 Ops.push_back(InFlag);
2156 // If this is the first return lowered for this function, add the regs
2157 // to the liveout set for the function.
2158 if (MF.getRegInfo().liveout_empty()) {
2159 SmallVector<CCValAssign, 16> RVLocs;
2160 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2163 for (unsigned i = 0; i != RVLocs.size(); ++i)
2164 if (RVLocs[i].isRegLoc())
2165 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2167 return DAG.getNode(X86ISD::TC_RETURN, dl,
2168 NodeTys, &Ops[0], Ops.size());
2171 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2172 InFlag = Chain.getValue(1);
2174 // Create the CALLSEQ_END node.
2175 unsigned NumBytesForCalleeToPush;
2176 if (IsCalleePop(isVarArg, CallConv))
2177 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2178 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2179 // If this is a call to a struct-return function, the callee
2180 // pops the hidden struct pointer, so we have to push it back.
2181 // This is common for Darwin/X86, Linux & Mingw32 targets.
2182 NumBytesForCalleeToPush = 4;
2184 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2186 // Returns a flag for retval copy to use.
2188 Chain = DAG.getCALLSEQ_END(Chain,
2189 DAG.getIntPtrConstant(NumBytes, true),
2190 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2193 InFlag = Chain.getValue(1);
2196 // Handle result values, copying them out of physregs into vregs that we
2198 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2199 Ins, dl, DAG, InVals);
2203 //===----------------------------------------------------------------------===//
2204 // Fast Calling Convention (tail call) implementation
2205 //===----------------------------------------------------------------------===//
2207 // Like std call, callee cleans arguments, convention except that ECX is
2208 // reserved for storing the tail called function address. Only 2 registers are
2209 // free for argument passing (inreg). Tail call optimization is performed
2211 // * tailcallopt is enabled
2212 // * caller/callee are fastcc
2213 // On X86_64 architecture with GOT-style position independent code only local
2214 // (within module) calls are supported at the moment.
2215 // To keep the stack aligned according to platform abi the function
2216 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2217 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2218 // If a tail called function callee has more arguments than the caller the
2219 // caller needs to make sure that there is room to move the RETADDR to. This is
2220 // achieved by reserving an area the size of the argument delta right after the
2221 // original REtADDR, but before the saved framepointer or the spilled registers
2222 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2234 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2235 /// for a 16 byte align requirement.
2237 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2238 SelectionDAG& DAG) const {
2239 MachineFunction &MF = DAG.getMachineFunction();
2240 const TargetMachine &TM = MF.getTarget();
2241 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2242 unsigned StackAlignment = TFI.getStackAlignment();
2243 uint64_t AlignMask = StackAlignment - 1;
2244 int64_t Offset = StackSize;
2245 uint64_t SlotSize = TD->getPointerSize();
2246 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2247 // Number smaller than 12 so just add the difference.
2248 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2250 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2251 Offset = ((~AlignMask) & Offset) + StackAlignment +
2252 (StackAlignment-SlotSize);
2257 /// MatchingStackOffset - Return true if the given stack call argument is
2258 /// already available in the same position (relatively) of the caller's
2259 /// incoming argument stack.
2261 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2262 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2263 const X86InstrInfo *TII) {
2264 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2266 if (Arg.getOpcode() == ISD::CopyFromReg) {
2267 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2268 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2270 MachineInstr *Def = MRI->getVRegDef(VR);
2273 if (!Flags.isByVal()) {
2274 if (!TII->isLoadFromStackSlot(Def, FI))
2277 unsigned Opcode = Def->getOpcode();
2278 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2279 Def->getOperand(1).isFI()) {
2280 FI = Def->getOperand(1).getIndex();
2281 Bytes = Flags.getByValSize();
2285 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2286 if (Flags.isByVal())
2287 // ByVal argument is passed in as a pointer but it's now being
2288 // dereferenced. e.g.
2289 // define @foo(%struct.X* %A) {
2290 // tail call @bar(%struct.X* byval %A)
2293 SDValue Ptr = Ld->getBasePtr();
2294 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2297 FI = FINode->getIndex();
2301 assert(FI != INT_MAX);
2302 if (!MFI->isFixedObjectIndex(FI))
2304 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2307 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2308 /// for tail call optimization. Targets which want to do tail call
2309 /// optimization should implement this function.
2311 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2312 CallingConv::ID CalleeCC,
2314 bool isCalleeStructRet,
2315 bool isCallerStructRet,
2316 const SmallVectorImpl<ISD::OutputArg> &Outs,
2317 const SmallVectorImpl<ISD::InputArg> &Ins,
2318 SelectionDAG& DAG) const {
2319 if (!IsTailCallConvention(CalleeCC) &&
2320 CalleeCC != CallingConv::C)
2323 // If -tailcallopt is specified, make fastcc functions tail-callable.
2324 const MachineFunction &MF = DAG.getMachineFunction();
2325 const Function *CallerF = DAG.getMachineFunction().getFunction();
2326 CallingConv::ID CallerCC = CallerF->getCallingConv();
2327 bool CCMatch = CallerCC == CalleeCC;
2329 if (GuaranteedTailCallOpt) {
2330 if (IsTailCallConvention(CalleeCC) && CCMatch)
2335 // Look for obvious safe cases to perform tail call optimization that does not
2336 // requite ABI changes. This is what gcc calls sibcall.
2338 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2339 // emit a special epilogue.
2340 if (RegInfo->needsStackRealignment(MF))
2343 // Do not sibcall optimize vararg calls unless the call site is not passing any
2345 if (isVarArg && !Outs.empty())
2348 // Also avoid sibcall optimization if either caller or callee uses struct
2349 // return semantics.
2350 if (isCalleeStructRet || isCallerStructRet)
2353 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2354 // Therefore if it's not used by the call it is not safe to optimize this into
2356 bool Unused = false;
2357 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2364 SmallVector<CCValAssign, 16> RVLocs;
2365 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2366 RVLocs, *DAG.getContext());
2367 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2368 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2369 CCValAssign &VA = RVLocs[i];
2370 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2375 // If the calling conventions do not match, then we'd better make sure the
2376 // results are returned in the same way as what the caller expects.
2378 SmallVector<CCValAssign, 16> RVLocs1;
2379 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2380 RVLocs1, *DAG.getContext());
2381 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2383 SmallVector<CCValAssign, 16> RVLocs2;
2384 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2385 RVLocs2, *DAG.getContext());
2386 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2388 if (RVLocs1.size() != RVLocs2.size())
2390 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2391 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2393 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2395 if (RVLocs1[i].isRegLoc()) {
2396 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2399 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2405 // If the callee takes no arguments then go on to check the results of the
2407 if (!Outs.empty()) {
2408 // Check if stack adjustment is needed. For now, do not do this if any
2409 // argument is passed on the stack.
2410 SmallVector<CCValAssign, 16> ArgLocs;
2411 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2412 ArgLocs, *DAG.getContext());
2413 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2414 if (CCInfo.getNextStackOffset()) {
2415 MachineFunction &MF = DAG.getMachineFunction();
2416 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2418 if (Subtarget->isTargetWin64())
2419 // Win64 ABI has additional complications.
2422 // Check if the arguments are already laid out in the right way as
2423 // the caller's fixed stack objects.
2424 MachineFrameInfo *MFI = MF.getFrameInfo();
2425 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2426 const X86InstrInfo *TII =
2427 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2428 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2429 CCValAssign &VA = ArgLocs[i];
2430 EVT RegVT = VA.getLocVT();
2431 SDValue Arg = Outs[i].Val;
2432 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2433 if (VA.getLocInfo() == CCValAssign::Indirect)
2435 if (!VA.isRegLoc()) {
2436 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2448 X86TargetLowering::createFastISel(MachineFunction &mf,
2449 DenseMap<const Value *, unsigned> &vm,
2450 DenseMap<const BasicBlock*, MachineBasicBlock*> &bm,
2451 DenseMap<const AllocaInst *, int> &am,
2452 std::vector<std::pair<MachineInstr*, unsigned> > &pn
2454 , SmallSet<const Instruction *, 8> &cil
2457 return X86::createFastISel(mf, vm, bm, am, pn
2465 //===----------------------------------------------------------------------===//
2466 // Other Lowering Hooks
2467 //===----------------------------------------------------------------------===//
2470 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2471 MachineFunction &MF = DAG.getMachineFunction();
2472 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2473 int ReturnAddrIndex = FuncInfo->getRAIndex();
2475 if (ReturnAddrIndex == 0) {
2476 // Set up a frame object for the return address.
2477 uint64_t SlotSize = TD->getPointerSize();
2478 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2480 FuncInfo->setRAIndex(ReturnAddrIndex);
2483 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2487 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2488 bool hasSymbolicDisplacement) {
2489 // Offset should fit into 32 bit immediate field.
2490 if (!isInt<32>(Offset))
2493 // If we don't have a symbolic displacement - we don't have any extra
2495 if (!hasSymbolicDisplacement)
2498 // FIXME: Some tweaks might be needed for medium code model.
2499 if (M != CodeModel::Small && M != CodeModel::Kernel)
2502 // For small code model we assume that latest object is 16MB before end of 31
2503 // bits boundary. We may also accept pretty large negative constants knowing
2504 // that all objects are in the positive half of address space.
2505 if (M == CodeModel::Small && Offset < 16*1024*1024)
2508 // For kernel code model we know that all object resist in the negative half
2509 // of 32bits address space. We may not accept negative offsets, since they may
2510 // be just off and we may accept pretty large positive ones.
2511 if (M == CodeModel::Kernel && Offset > 0)
2517 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2518 /// specific condition code, returning the condition code and the LHS/RHS of the
2519 /// comparison to make.
2520 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2521 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2523 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2524 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2525 // X > -1 -> X == 0, jump !sign.
2526 RHS = DAG.getConstant(0, RHS.getValueType());
2527 return X86::COND_NS;
2528 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2529 // X < 0 -> X == 0, jump on sign.
2531 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2533 RHS = DAG.getConstant(0, RHS.getValueType());
2534 return X86::COND_LE;
2538 switch (SetCCOpcode) {
2539 default: llvm_unreachable("Invalid integer condition!");
2540 case ISD::SETEQ: return X86::COND_E;
2541 case ISD::SETGT: return X86::COND_G;
2542 case ISD::SETGE: return X86::COND_GE;
2543 case ISD::SETLT: return X86::COND_L;
2544 case ISD::SETLE: return X86::COND_LE;
2545 case ISD::SETNE: return X86::COND_NE;
2546 case ISD::SETULT: return X86::COND_B;
2547 case ISD::SETUGT: return X86::COND_A;
2548 case ISD::SETULE: return X86::COND_BE;
2549 case ISD::SETUGE: return X86::COND_AE;
2553 // First determine if it is required or is profitable to flip the operands.
2555 // If LHS is a foldable load, but RHS is not, flip the condition.
2556 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2557 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2558 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2559 std::swap(LHS, RHS);
2562 switch (SetCCOpcode) {
2568 std::swap(LHS, RHS);
2572 // On a floating point condition, the flags are set as follows:
2574 // 0 | 0 | 0 | X > Y
2575 // 0 | 0 | 1 | X < Y
2576 // 1 | 0 | 0 | X == Y
2577 // 1 | 1 | 1 | unordered
2578 switch (SetCCOpcode) {
2579 default: llvm_unreachable("Condcode should be pre-legalized away");
2581 case ISD::SETEQ: return X86::COND_E;
2582 case ISD::SETOLT: // flipped
2584 case ISD::SETGT: return X86::COND_A;
2585 case ISD::SETOLE: // flipped
2587 case ISD::SETGE: return X86::COND_AE;
2588 case ISD::SETUGT: // flipped
2590 case ISD::SETLT: return X86::COND_B;
2591 case ISD::SETUGE: // flipped
2593 case ISD::SETLE: return X86::COND_BE;
2595 case ISD::SETNE: return X86::COND_NE;
2596 case ISD::SETUO: return X86::COND_P;
2597 case ISD::SETO: return X86::COND_NP;
2599 case ISD::SETUNE: return X86::COND_INVALID;
2603 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2604 /// code. Current x86 isa includes the following FP cmov instructions:
2605 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2606 static bool hasFPCMov(unsigned X86CC) {
2622 /// isFPImmLegal - Returns true if the target can instruction select the
2623 /// specified FP immediate natively. If false, the legalizer will
2624 /// materialize the FP immediate as a load from a constant pool.
2625 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2626 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2627 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2633 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2634 /// the specified range (L, H].
2635 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2636 return (Val < 0) || (Val >= Low && Val < Hi);
2639 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2640 /// specified value.
2641 static bool isUndefOrEqual(int Val, int CmpVal) {
2642 if (Val < 0 || Val == CmpVal)
2647 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2648 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2649 /// the second operand.
2650 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2651 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2652 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2653 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2654 return (Mask[0] < 2 && Mask[1] < 2);
2658 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2659 SmallVector<int, 8> M;
2661 return ::isPSHUFDMask(M, N->getValueType(0));
2664 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2665 /// is suitable for input to PSHUFHW.
2666 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2667 if (VT != MVT::v8i16)
2670 // Lower quadword copied in order or undef.
2671 for (int i = 0; i != 4; ++i)
2672 if (Mask[i] >= 0 && Mask[i] != i)
2675 // Upper quadword shuffled.
2676 for (int i = 4; i != 8; ++i)
2677 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2683 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2684 SmallVector<int, 8> M;
2686 return ::isPSHUFHWMask(M, N->getValueType(0));
2689 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2690 /// is suitable for input to PSHUFLW.
2691 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2692 if (VT != MVT::v8i16)
2695 // Upper quadword copied in order.
2696 for (int i = 4; i != 8; ++i)
2697 if (Mask[i] >= 0 && Mask[i] != i)
2700 // Lower quadword shuffled.
2701 for (int i = 0; i != 4; ++i)
2708 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2709 SmallVector<int, 8> M;
2711 return ::isPSHUFLWMask(M, N->getValueType(0));
2714 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2715 /// is suitable for input to PALIGNR.
2716 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2718 int i, e = VT.getVectorNumElements();
2720 // Do not handle v2i64 / v2f64 shuffles with palignr.
2721 if (e < 4 || !hasSSSE3)
2724 for (i = 0; i != e; ++i)
2728 // All undef, not a palignr.
2732 // Determine if it's ok to perform a palignr with only the LHS, since we
2733 // don't have access to the actual shuffle elements to see if RHS is undef.
2734 bool Unary = Mask[i] < (int)e;
2735 bool NeedsUnary = false;
2737 int s = Mask[i] - i;
2739 // Check the rest of the elements to see if they are consecutive.
2740 for (++i; i != e; ++i) {
2745 Unary = Unary && (m < (int)e);
2746 NeedsUnary = NeedsUnary || (m < s);
2748 if (NeedsUnary && !Unary)
2750 if (Unary && m != ((s+i) & (e-1)))
2752 if (!Unary && m != (s+i))
2758 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2759 SmallVector<int, 8> M;
2761 return ::isPALIGNRMask(M, N->getValueType(0), true);
2764 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2765 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2766 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2767 int NumElems = VT.getVectorNumElements();
2768 if (NumElems != 2 && NumElems != 4)
2771 int Half = NumElems / 2;
2772 for (int i = 0; i < Half; ++i)
2773 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2775 for (int i = Half; i < NumElems; ++i)
2776 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2782 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2783 SmallVector<int, 8> M;
2785 return ::isSHUFPMask(M, N->getValueType(0));
2788 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2789 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2790 /// half elements to come from vector 1 (which would equal the dest.) and
2791 /// the upper half to come from vector 2.
2792 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2793 int NumElems = VT.getVectorNumElements();
2795 if (NumElems != 2 && NumElems != 4)
2798 int Half = NumElems / 2;
2799 for (int i = 0; i < Half; ++i)
2800 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2802 for (int i = Half; i < NumElems; ++i)
2803 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2808 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2809 SmallVector<int, 8> M;
2811 return isCommutedSHUFPMask(M, N->getValueType(0));
2814 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2815 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2816 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2817 if (N->getValueType(0).getVectorNumElements() != 4)
2820 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2821 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2822 isUndefOrEqual(N->getMaskElt(1), 7) &&
2823 isUndefOrEqual(N->getMaskElt(2), 2) &&
2824 isUndefOrEqual(N->getMaskElt(3), 3);
2827 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2828 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2830 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2831 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2836 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2837 isUndefOrEqual(N->getMaskElt(1), 3) &&
2838 isUndefOrEqual(N->getMaskElt(2), 2) &&
2839 isUndefOrEqual(N->getMaskElt(3), 3);
2842 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2843 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2844 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2845 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2847 if (NumElems != 2 && NumElems != 4)
2850 for (unsigned i = 0; i < NumElems/2; ++i)
2851 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2854 for (unsigned i = NumElems/2; i < NumElems; ++i)
2855 if (!isUndefOrEqual(N->getMaskElt(i), i))
2861 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2862 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2863 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2864 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2866 if (NumElems != 2 && NumElems != 4)
2869 for (unsigned i = 0; i < NumElems/2; ++i)
2870 if (!isUndefOrEqual(N->getMaskElt(i), i))
2873 for (unsigned i = 0; i < NumElems/2; ++i)
2874 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2880 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2881 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2882 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2883 bool V2IsSplat = false) {
2884 int NumElts = VT.getVectorNumElements();
2885 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2888 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2890 int BitI1 = Mask[i+1];
2891 if (!isUndefOrEqual(BitI, j))
2894 if (!isUndefOrEqual(BitI1, NumElts))
2897 if (!isUndefOrEqual(BitI1, j + NumElts))
2904 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2905 SmallVector<int, 8> M;
2907 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2910 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2911 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2912 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2913 bool V2IsSplat = false) {
2914 int NumElts = VT.getVectorNumElements();
2915 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2918 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2920 int BitI1 = Mask[i+1];
2921 if (!isUndefOrEqual(BitI, j + NumElts/2))
2924 if (isUndefOrEqual(BitI1, NumElts))
2927 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2934 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2935 SmallVector<int, 8> M;
2937 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2940 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2941 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2943 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2944 int NumElems = VT.getVectorNumElements();
2945 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2948 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2950 int BitI1 = Mask[i+1];
2951 if (!isUndefOrEqual(BitI, j))
2953 if (!isUndefOrEqual(BitI1, j))
2959 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2960 SmallVector<int, 8> M;
2962 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2965 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2966 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2968 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2969 int NumElems = VT.getVectorNumElements();
2970 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2973 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2975 int BitI1 = Mask[i+1];
2976 if (!isUndefOrEqual(BitI, j))
2978 if (!isUndefOrEqual(BitI1, j))
2984 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2985 SmallVector<int, 8> M;
2987 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2990 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2991 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2992 /// MOVSD, and MOVD, i.e. setting the lowest element.
2993 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2994 if (VT.getVectorElementType().getSizeInBits() < 32)
2997 int NumElts = VT.getVectorNumElements();
2999 if (!isUndefOrEqual(Mask[0], NumElts))
3002 for (int i = 1; i < NumElts; ++i)
3003 if (!isUndefOrEqual(Mask[i], i))
3009 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3010 SmallVector<int, 8> M;
3012 return ::isMOVLMask(M, N->getValueType(0));
3015 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3016 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3017 /// element of vector 2 and the other elements to come from vector 1 in order.
3018 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3019 bool V2IsSplat = false, bool V2IsUndef = false) {
3020 int NumOps = VT.getVectorNumElements();
3021 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3024 if (!isUndefOrEqual(Mask[0], 0))
3027 for (int i = 1; i < NumOps; ++i)
3028 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3029 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3030 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3036 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3037 bool V2IsUndef = false) {
3038 SmallVector<int, 8> M;
3040 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3043 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3044 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3045 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3046 if (N->getValueType(0).getVectorNumElements() != 4)
3049 // Expect 1, 1, 3, 3
3050 for (unsigned i = 0; i < 2; ++i) {
3051 int Elt = N->getMaskElt(i);
3052 if (Elt >= 0 && Elt != 1)
3057 for (unsigned i = 2; i < 4; ++i) {
3058 int Elt = N->getMaskElt(i);
3059 if (Elt >= 0 && Elt != 3)
3064 // Don't use movshdup if it can be done with a shufps.
3065 // FIXME: verify that matching u, u, 3, 3 is what we want.
3069 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3070 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3071 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3072 if (N->getValueType(0).getVectorNumElements() != 4)
3075 // Expect 0, 0, 2, 2
3076 for (unsigned i = 0; i < 2; ++i)
3077 if (N->getMaskElt(i) > 0)
3081 for (unsigned i = 2; i < 4; ++i) {
3082 int Elt = N->getMaskElt(i);
3083 if (Elt >= 0 && Elt != 2)
3088 // Don't use movsldup if it can be done with a shufps.
3092 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3093 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3094 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3095 int e = N->getValueType(0).getVectorNumElements() / 2;
3097 for (int i = 0; i < e; ++i)
3098 if (!isUndefOrEqual(N->getMaskElt(i), i))
3100 for (int i = 0; i < e; ++i)
3101 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3106 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3107 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3108 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3109 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3110 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3112 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3114 for (int i = 0; i < NumOperands; ++i) {
3115 int Val = SVOp->getMaskElt(NumOperands-i-1);
3116 if (Val < 0) Val = 0;
3117 if (Val >= NumOperands) Val -= NumOperands;
3119 if (i != NumOperands - 1)
3125 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3126 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3127 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3128 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3130 // 8 nodes, but we only care about the last 4.
3131 for (unsigned i = 7; i >= 4; --i) {
3132 int Val = SVOp->getMaskElt(i);
3141 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3142 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3143 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3144 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3146 // 8 nodes, but we only care about the first 4.
3147 for (int i = 3; i >= 0; --i) {
3148 int Val = SVOp->getMaskElt(i);
3157 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3158 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3159 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3160 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3161 EVT VVT = N->getValueType(0);
3162 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3166 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3167 Val = SVOp->getMaskElt(i);
3171 return (Val - i) * EltSize;
3174 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3176 bool X86::isZeroNode(SDValue Elt) {
3177 return ((isa<ConstantSDNode>(Elt) &&
3178 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
3179 (isa<ConstantFPSDNode>(Elt) &&
3180 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3183 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3184 /// their permute mask.
3185 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3186 SelectionDAG &DAG) {
3187 EVT VT = SVOp->getValueType(0);
3188 unsigned NumElems = VT.getVectorNumElements();
3189 SmallVector<int, 8> MaskVec;
3191 for (unsigned i = 0; i != NumElems; ++i) {
3192 int idx = SVOp->getMaskElt(i);
3194 MaskVec.push_back(idx);
3195 else if (idx < (int)NumElems)
3196 MaskVec.push_back(idx + NumElems);
3198 MaskVec.push_back(idx - NumElems);
3200 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3201 SVOp->getOperand(0), &MaskVec[0]);
3204 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3205 /// the two vector operands have swapped position.
3206 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3207 unsigned NumElems = VT.getVectorNumElements();
3208 for (unsigned i = 0; i != NumElems; ++i) {
3212 else if (idx < (int)NumElems)
3213 Mask[i] = idx + NumElems;
3215 Mask[i] = idx - NumElems;
3219 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3220 /// match movhlps. The lower half elements should come from upper half of
3221 /// V1 (and in order), and the upper half elements should come from the upper
3222 /// half of V2 (and in order).
3223 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3224 if (Op->getValueType(0).getVectorNumElements() != 4)
3226 for (unsigned i = 0, e = 2; i != e; ++i)
3227 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3229 for (unsigned i = 2; i != 4; ++i)
3230 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3235 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3236 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3238 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3239 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3241 N = N->getOperand(0).getNode();
3242 if (!ISD::isNON_EXTLoad(N))
3245 *LD = cast<LoadSDNode>(N);
3249 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3250 /// match movlp{s|d}. The lower half elements should come from lower half of
3251 /// V1 (and in order), and the upper half elements should come from the upper
3252 /// half of V2 (and in order). And since V1 will become the source of the
3253 /// MOVLP, it must be either a vector load or a scalar load to vector.
3254 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3255 ShuffleVectorSDNode *Op) {
3256 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3258 // Is V2 is a vector load, don't do this transformation. We will try to use
3259 // load folding shufps op.
3260 if (ISD::isNON_EXTLoad(V2))
3263 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3265 if (NumElems != 2 && NumElems != 4)
3267 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3268 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3270 for (unsigned i = NumElems/2; i != NumElems; ++i)
3271 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3276 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3278 static bool isSplatVector(SDNode *N) {
3279 if (N->getOpcode() != ISD::BUILD_VECTOR)
3282 SDValue SplatValue = N->getOperand(0);
3283 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3284 if (N->getOperand(i) != SplatValue)
3289 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3290 /// to an zero vector.
3291 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3292 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3293 SDValue V1 = N->getOperand(0);
3294 SDValue V2 = N->getOperand(1);
3295 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3296 for (unsigned i = 0; i != NumElems; ++i) {
3297 int Idx = N->getMaskElt(i);
3298 if (Idx >= (int)NumElems) {
3299 unsigned Opc = V2.getOpcode();
3300 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3302 if (Opc != ISD::BUILD_VECTOR ||
3303 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3305 } else if (Idx >= 0) {
3306 unsigned Opc = V1.getOpcode();
3307 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3309 if (Opc != ISD::BUILD_VECTOR ||
3310 !X86::isZeroNode(V1.getOperand(Idx)))
3317 /// getZeroVector - Returns a vector of specified type with all zero elements.
3319 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3321 assert(VT.isVector() && "Expected a vector type");
3323 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3324 // type. This ensures they get CSE'd.
3326 if (VT.getSizeInBits() == 64) { // MMX
3327 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3328 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3329 } else if (HasSSE2) { // SSE2
3330 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3331 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3333 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3334 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3336 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3339 /// getOnesVector - Returns a vector of specified type with all bits set.
3341 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3342 assert(VT.isVector() && "Expected a vector type");
3344 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3345 // type. This ensures they get CSE'd.
3346 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3348 if (VT.getSizeInBits() == 64) // MMX
3349 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3351 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3352 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3356 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3357 /// that point to V2 points to its first element.
3358 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3359 EVT VT = SVOp->getValueType(0);
3360 unsigned NumElems = VT.getVectorNumElements();
3362 bool Changed = false;
3363 SmallVector<int, 8> MaskVec;
3364 SVOp->getMask(MaskVec);
3366 for (unsigned i = 0; i != NumElems; ++i) {
3367 if (MaskVec[i] > (int)NumElems) {
3368 MaskVec[i] = NumElems;
3373 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3374 SVOp->getOperand(1), &MaskVec[0]);
3375 return SDValue(SVOp, 0);
3378 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3379 /// operation of specified width.
3380 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3382 unsigned NumElems = VT.getVectorNumElements();
3383 SmallVector<int, 8> Mask;
3384 Mask.push_back(NumElems);
3385 for (unsigned i = 1; i != NumElems; ++i)
3387 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3390 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3391 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3393 unsigned NumElems = VT.getVectorNumElements();
3394 SmallVector<int, 8> Mask;
3395 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3397 Mask.push_back(i + NumElems);
3399 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3402 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3403 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3405 unsigned NumElems = VT.getVectorNumElements();
3406 unsigned Half = NumElems/2;
3407 SmallVector<int, 8> Mask;
3408 for (unsigned i = 0; i != Half; ++i) {
3409 Mask.push_back(i + Half);
3410 Mask.push_back(i + NumElems + Half);
3412 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3415 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3416 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3418 if (SV->getValueType(0).getVectorNumElements() <= 4)
3419 return SDValue(SV, 0);
3421 EVT PVT = MVT::v4f32;
3422 EVT VT = SV->getValueType(0);
3423 DebugLoc dl = SV->getDebugLoc();
3424 SDValue V1 = SV->getOperand(0);
3425 int NumElems = VT.getVectorNumElements();
3426 int EltNo = SV->getSplatIndex();
3428 // unpack elements to the correct location
3429 while (NumElems > 4) {
3430 if (EltNo < NumElems/2) {
3431 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3433 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3434 EltNo -= NumElems/2;
3439 // Perform the splat.
3440 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3441 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3442 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3443 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3446 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3447 /// vector of zero or undef vector. This produces a shuffle where the low
3448 /// element of V2 is swizzled into the zero/undef vector, landing at element
3449 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3450 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3451 bool isZero, bool HasSSE2,
3452 SelectionDAG &DAG) {
3453 EVT VT = V2.getValueType();
3455 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3456 unsigned NumElems = VT.getVectorNumElements();
3457 SmallVector<int, 16> MaskVec;
3458 for (unsigned i = 0; i != NumElems; ++i)
3459 // If this is the insertion idx, put the low elt of V2 here.
3460 MaskVec.push_back(i == Idx ? NumElems : i);
3461 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3464 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3465 /// a shuffle that is zero.
3467 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3468 bool Low, SelectionDAG &DAG) {
3469 unsigned NumZeros = 0;
3470 for (int i = 0; i < NumElems; ++i) {
3471 unsigned Index = Low ? i : NumElems-i-1;
3472 int Idx = SVOp->getMaskElt(Index);
3477 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3478 if (Elt.getNode() && X86::isZeroNode(Elt))
3486 /// isVectorShift - Returns true if the shuffle can be implemented as a
3487 /// logical left or right shift of a vector.
3488 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3489 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3490 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3491 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3494 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3497 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3501 bool SeenV1 = false;
3502 bool SeenV2 = false;
3503 for (unsigned i = NumZeros; i < NumElems; ++i) {
3504 unsigned Val = isLeft ? (i - NumZeros) : i;
3505 int Idx_ = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3508 unsigned Idx = (unsigned) Idx_;
3518 if (SeenV1 && SeenV2)
3521 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3527 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3529 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3530 unsigned NumNonZero, unsigned NumZero,
3532 const TargetLowering &TLI) {
3536 DebugLoc dl = Op.getDebugLoc();
3539 for (unsigned i = 0; i < 16; ++i) {
3540 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3541 if (ThisIsNonZero && First) {
3543 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3545 V = DAG.getUNDEF(MVT::v8i16);
3550 SDValue ThisElt(0, 0), LastElt(0, 0);
3551 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3552 if (LastIsNonZero) {
3553 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3554 MVT::i16, Op.getOperand(i-1));
3556 if (ThisIsNonZero) {
3557 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3558 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3559 ThisElt, DAG.getConstant(8, MVT::i8));
3561 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3565 if (ThisElt.getNode())
3566 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3567 DAG.getIntPtrConstant(i/2));
3571 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3574 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3576 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3577 unsigned NumNonZero, unsigned NumZero,
3579 const TargetLowering &TLI) {
3583 DebugLoc dl = Op.getDebugLoc();
3586 for (unsigned i = 0; i < 8; ++i) {
3587 bool isNonZero = (NonZeros & (1 << i)) != 0;
3591 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3593 V = DAG.getUNDEF(MVT::v8i16);
3596 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3597 MVT::v8i16, V, Op.getOperand(i),
3598 DAG.getIntPtrConstant(i));
3605 /// getVShift - Return a vector logical shift node.
3607 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3608 unsigned NumBits, SelectionDAG &DAG,
3609 const TargetLowering &TLI, DebugLoc dl) {
3610 bool isMMX = VT.getSizeInBits() == 64;
3611 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3612 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3613 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3614 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3615 DAG.getNode(Opc, dl, ShVT, SrcOp,
3616 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3620 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3621 SelectionDAG &DAG) const {
3623 // Check if the scalar load can be widened into a vector load. And if
3624 // the address is "base + cst" see if the cst can be "absorbed" into
3625 // the shuffle mask.
3626 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3627 SDValue Ptr = LD->getBasePtr();
3628 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3630 EVT PVT = LD->getValueType(0);
3631 if (PVT != MVT::i32 && PVT != MVT::f32)
3636 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3637 FI = FINode->getIndex();
3639 } else if (Ptr.getOpcode() == ISD::ADD &&
3640 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3641 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3642 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3643 Offset = Ptr.getConstantOperandVal(1);
3644 Ptr = Ptr.getOperand(0);
3649 SDValue Chain = LD->getChain();
3650 // Make sure the stack object alignment is at least 16.
3651 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3652 if (DAG.InferPtrAlignment(Ptr) < 16) {
3653 if (MFI->isFixedObjectIndex(FI)) {
3654 // Can't change the alignment. FIXME: It's possible to compute
3655 // the exact stack offset and reference FI + adjust offset instead.
3656 // If someone *really* cares about this. That's the way to implement it.
3659 MFI->setObjectAlignment(FI, 16);
3663 // (Offset % 16) must be multiple of 4. Then address is then
3664 // Ptr + (Offset & ~15).
3667 if ((Offset % 16) & 3)
3669 int64_t StartOffset = Offset & ~15;
3671 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3672 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3674 int EltNo = (Offset - StartOffset) >> 2;
3675 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3676 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3677 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0,
3679 // Canonicalize it to a v4i32 shuffle.
3680 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3681 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3682 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3683 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3689 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
3690 /// vector of type 'VT', see if the elements can be replaced by a single large
3691 /// load which has the same value as a build_vector whose operands are 'elts'.
3693 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
3695 /// FIXME: we'd also like to handle the case where the last elements are zero
3696 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
3697 /// There's even a handy isZeroNode for that purpose.
3698 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
3699 DebugLoc &dl, SelectionDAG &DAG) {
3700 EVT EltVT = VT.getVectorElementType();
3701 unsigned NumElems = Elts.size();
3703 LoadSDNode *LDBase = NULL;
3704 unsigned LastLoadedElt = -1U;
3706 // For each element in the initializer, see if we've found a load or an undef.
3707 // If we don't find an initial load element, or later load elements are
3708 // non-consecutive, bail out.
3709 for (unsigned i = 0; i < NumElems; ++i) {
3710 SDValue Elt = Elts[i];
3712 if (!Elt.getNode() ||
3713 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
3716 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
3718 LDBase = cast<LoadSDNode>(Elt.getNode());
3722 if (Elt.getOpcode() == ISD::UNDEF)
3725 LoadSDNode *LD = cast<LoadSDNode>(Elt);
3726 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
3731 // If we have found an entire vector of loads and undefs, then return a large
3732 // load of the entire vector width starting at the base pointer. If we found
3733 // consecutive loads for the low half, generate a vzext_load node.
3734 if (LastLoadedElt == NumElems - 1) {
3735 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
3736 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
3737 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
3738 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
3739 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
3740 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
3741 LDBase->isVolatile(), LDBase->isNonTemporal(),
3742 LDBase->getAlignment());
3743 } else if (NumElems == 4 && LastLoadedElt == 1) {
3744 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
3745 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
3746 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
3747 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
3753 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
3754 DebugLoc dl = Op.getDebugLoc();
3755 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3756 if (ISD::isBuildVectorAllZeros(Op.getNode())
3757 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3758 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3759 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3760 // eliminated on x86-32 hosts.
3761 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3764 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3765 return getOnesVector(Op.getValueType(), DAG, dl);
3766 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3769 EVT VT = Op.getValueType();
3770 EVT ExtVT = VT.getVectorElementType();
3771 unsigned EVTBits = ExtVT.getSizeInBits();
3773 unsigned NumElems = Op.getNumOperands();
3774 unsigned NumZero = 0;
3775 unsigned NumNonZero = 0;
3776 unsigned NonZeros = 0;
3777 bool IsAllConstants = true;
3778 SmallSet<SDValue, 8> Values;
3779 for (unsigned i = 0; i < NumElems; ++i) {
3780 SDValue Elt = Op.getOperand(i);
3781 if (Elt.getOpcode() == ISD::UNDEF)
3784 if (Elt.getOpcode() != ISD::Constant &&
3785 Elt.getOpcode() != ISD::ConstantFP)
3786 IsAllConstants = false;
3787 if (X86::isZeroNode(Elt))
3790 NonZeros |= (1 << i);
3795 if (NumNonZero == 0) {
3796 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3797 return DAG.getUNDEF(VT);
3800 // Special case for single non-zero, non-undef, element.
3801 if (NumNonZero == 1) {
3802 unsigned Idx = CountTrailingZeros_32(NonZeros);
3803 SDValue Item = Op.getOperand(Idx);
3805 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3806 // the value are obviously zero, truncate the value to i32 and do the
3807 // insertion that way. Only do this if the value is non-constant or if the
3808 // value is a constant being inserted into element 0. It is cheaper to do
3809 // a constant pool load than it is to do a movd + shuffle.
3810 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3811 (!IsAllConstants || Idx == 0)) {
3812 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3813 // Handle MMX and SSE both.
3814 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3815 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3817 // Truncate the value (which may itself be a constant) to i32, and
3818 // convert it to a vector with movd (S2V+shuffle to zero extend).
3819 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3820 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3821 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3822 Subtarget->hasSSE2(), DAG);
3824 // Now we have our 32-bit value zero extended in the low element of
3825 // a vector. If Idx != 0, swizzle it into place.
3827 SmallVector<int, 4> Mask;
3828 Mask.push_back(Idx);
3829 for (unsigned i = 1; i != VecElts; ++i)
3831 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3832 DAG.getUNDEF(Item.getValueType()),
3835 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3839 // If we have a constant or non-constant insertion into the low element of
3840 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3841 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3842 // depending on what the source datatype is.
3845 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3846 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3847 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3848 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3849 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3850 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3852 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3853 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3854 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3855 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3856 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3857 Subtarget->hasSSE2(), DAG);
3858 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3862 // Is it a vector logical left shift?
3863 if (NumElems == 2 && Idx == 1 &&
3864 X86::isZeroNode(Op.getOperand(0)) &&
3865 !X86::isZeroNode(Op.getOperand(1))) {
3866 unsigned NumBits = VT.getSizeInBits();
3867 return getVShift(true, VT,
3868 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3869 VT, Op.getOperand(1)),
3870 NumBits/2, DAG, *this, dl);
3873 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3876 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3877 // is a non-constant being inserted into an element other than the low one,
3878 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3879 // movd/movss) to move this into the low element, then shuffle it into
3881 if (EVTBits == 32) {
3882 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3884 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3885 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3886 Subtarget->hasSSE2(), DAG);
3887 SmallVector<int, 8> MaskVec;
3888 for (unsigned i = 0; i < NumElems; i++)
3889 MaskVec.push_back(i == Idx ? 0 : 1);
3890 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3894 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3895 if (Values.size() == 1) {
3896 if (EVTBits == 32) {
3897 // Instead of a shuffle like this:
3898 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3899 // Check if it's possible to issue this instead.
3900 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3901 unsigned Idx = CountTrailingZeros_32(NonZeros);
3902 SDValue Item = Op.getOperand(Idx);
3903 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3904 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3909 // A vector full of immediates; various special cases are already
3910 // handled, so this is best done with a single constant-pool load.
3914 // Let legalizer expand 2-wide build_vectors.
3915 if (EVTBits == 64) {
3916 if (NumNonZero == 1) {
3917 // One half is zero or undef.
3918 unsigned Idx = CountTrailingZeros_32(NonZeros);
3919 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3920 Op.getOperand(Idx));
3921 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3922 Subtarget->hasSSE2(), DAG);
3927 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3928 if (EVTBits == 8 && NumElems == 16) {
3929 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3931 if (V.getNode()) return V;
3934 if (EVTBits == 16 && NumElems == 8) {
3935 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3937 if (V.getNode()) return V;
3940 // If element VT is == 32 bits, turn it into a number of shuffles.
3941 SmallVector<SDValue, 8> V;
3943 if (NumElems == 4 && NumZero > 0) {
3944 for (unsigned i = 0; i < 4; ++i) {
3945 bool isZero = !(NonZeros & (1 << i));
3947 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3949 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3952 for (unsigned i = 0; i < 2; ++i) {
3953 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3956 V[i] = V[i*2]; // Must be a zero vector.
3959 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3962 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3965 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3970 SmallVector<int, 8> MaskVec;
3971 bool Reverse = (NonZeros & 0x3) == 2;
3972 for (unsigned i = 0; i < 2; ++i)
3973 MaskVec.push_back(Reverse ? 1-i : i);
3974 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3975 for (unsigned i = 0; i < 2; ++i)
3976 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3977 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3980 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
3981 // Check for a build vector of consecutive loads.
3982 for (unsigned i = 0; i < NumElems; ++i)
3983 V[i] = Op.getOperand(i);
3985 // Check for elements which are consecutive loads.
3986 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
3990 // For SSE 4.1, use inserts into undef.
3991 if (getSubtarget()->hasSSE41()) {
3992 V[0] = DAG.getUNDEF(VT);
3993 for (unsigned i = 0; i < NumElems; ++i)
3994 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3995 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3996 Op.getOperand(i), DAG.getIntPtrConstant(i));
4000 // Otherwise, expand into a number of unpckl*
4002 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4003 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4004 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4005 for (unsigned i = 0; i < NumElems; ++i)
4006 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4008 while (NumElems != 0) {
4009 for (unsigned i = 0; i < NumElems; ++i)
4010 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
4019 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4020 // We support concatenate two MMX registers and place them in a MMX
4021 // register. This is better than doing a stack convert.
4022 DebugLoc dl = Op.getDebugLoc();
4023 EVT ResVT = Op.getValueType();
4024 assert(Op.getNumOperands() == 2);
4025 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4026 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4028 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
4029 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4030 InVec = Op.getOperand(1);
4031 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4032 unsigned NumElts = ResVT.getVectorNumElements();
4033 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4034 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4035 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4037 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
4038 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4039 Mask[0] = 0; Mask[1] = 2;
4040 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4042 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4045 // v8i16 shuffles - Prefer shuffles in the following order:
4046 // 1. [all] pshuflw, pshufhw, optional move
4047 // 2. [ssse3] 1 x pshufb
4048 // 3. [ssse3] 2 x pshufb + 1 x por
4049 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4051 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
4053 const X86TargetLowering &TLI) {
4054 SDValue V1 = SVOp->getOperand(0);
4055 SDValue V2 = SVOp->getOperand(1);
4056 DebugLoc dl = SVOp->getDebugLoc();
4057 SmallVector<int, 8> MaskVals;
4059 // Determine if more than 1 of the words in each of the low and high quadwords
4060 // of the result come from the same quadword of one of the two inputs. Undef
4061 // mask values count as coming from any quadword, for better codegen.
4062 SmallVector<unsigned, 4> LoQuad(4);
4063 SmallVector<unsigned, 4> HiQuad(4);
4064 BitVector InputQuads(4);
4065 for (unsigned i = 0; i < 8; ++i) {
4066 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4067 int EltIdx = SVOp->getMaskElt(i);
4068 MaskVals.push_back(EltIdx);
4077 InputQuads.set(EltIdx / 4);
4080 int BestLoQuad = -1;
4081 unsigned MaxQuad = 1;
4082 for (unsigned i = 0; i < 4; ++i) {
4083 if (LoQuad[i] > MaxQuad) {
4085 MaxQuad = LoQuad[i];
4089 int BestHiQuad = -1;
4091 for (unsigned i = 0; i < 4; ++i) {
4092 if (HiQuad[i] > MaxQuad) {
4094 MaxQuad = HiQuad[i];
4098 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4099 // of the two input vectors, shuffle them into one input vector so only a
4100 // single pshufb instruction is necessary. If There are more than 2 input
4101 // quads, disable the next transformation since it does not help SSSE3.
4102 bool V1Used = InputQuads[0] || InputQuads[1];
4103 bool V2Used = InputQuads[2] || InputQuads[3];
4104 if (TLI.getSubtarget()->hasSSSE3()) {
4105 if (InputQuads.count() == 2 && V1Used && V2Used) {
4106 BestLoQuad = InputQuads.find_first();
4107 BestHiQuad = InputQuads.find_next(BestLoQuad);
4109 if (InputQuads.count() > 2) {
4115 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4116 // the shuffle mask. If a quad is scored as -1, that means that it contains
4117 // words from all 4 input quadwords.
4119 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4120 SmallVector<int, 8> MaskV;
4121 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4122 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4123 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4124 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
4125 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
4126 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
4128 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4129 // source words for the shuffle, to aid later transformations.
4130 bool AllWordsInNewV = true;
4131 bool InOrder[2] = { true, true };
4132 for (unsigned i = 0; i != 8; ++i) {
4133 int idx = MaskVals[i];
4135 InOrder[i/4] = false;
4136 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4138 AllWordsInNewV = false;
4142 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4143 if (AllWordsInNewV) {
4144 for (int i = 0; i != 8; ++i) {
4145 int idx = MaskVals[i];
4148 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4149 if ((idx != i) && idx < 4)
4151 if ((idx != i) && idx > 3)
4160 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4161 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4162 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4163 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4164 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4168 // If we have SSSE3, and all words of the result are from 1 input vector,
4169 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4170 // is present, fall back to case 4.
4171 if (TLI.getSubtarget()->hasSSSE3()) {
4172 SmallVector<SDValue,16> pshufbMask;
4174 // If we have elements from both input vectors, set the high bit of the
4175 // shuffle mask element to zero out elements that come from V2 in the V1
4176 // mask, and elements that come from V1 in the V2 mask, so that the two
4177 // results can be OR'd together.
4178 bool TwoInputs = V1Used && V2Used;
4179 for (unsigned i = 0; i != 8; ++i) {
4180 int EltIdx = MaskVals[i] * 2;
4181 if (TwoInputs && (EltIdx >= 16)) {
4182 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4183 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4186 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4187 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4189 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4190 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4191 DAG.getNode(ISD::BUILD_VECTOR, dl,
4192 MVT::v16i8, &pshufbMask[0], 16));
4194 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4196 // Calculate the shuffle mask for the second input, shuffle it, and
4197 // OR it with the first shuffled input.
4199 for (unsigned i = 0; i != 8; ++i) {
4200 int EltIdx = MaskVals[i] * 2;
4202 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4203 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4206 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4207 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4209 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4210 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4211 DAG.getNode(ISD::BUILD_VECTOR, dl,
4212 MVT::v16i8, &pshufbMask[0], 16));
4213 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4214 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4217 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4218 // and update MaskVals with new element order.
4219 BitVector InOrder(8);
4220 if (BestLoQuad >= 0) {
4221 SmallVector<int, 8> MaskV;
4222 for (int i = 0; i != 4; ++i) {
4223 int idx = MaskVals[i];
4225 MaskV.push_back(-1);
4227 } else if ((idx / 4) == BestLoQuad) {
4228 MaskV.push_back(idx & 3);
4231 MaskV.push_back(-1);
4234 for (unsigned i = 4; i != 8; ++i)
4236 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4240 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4241 // and update MaskVals with the new element order.
4242 if (BestHiQuad >= 0) {
4243 SmallVector<int, 8> MaskV;
4244 for (unsigned i = 0; i != 4; ++i)
4246 for (unsigned i = 4; i != 8; ++i) {
4247 int idx = MaskVals[i];
4249 MaskV.push_back(-1);
4251 } else if ((idx / 4) == BestHiQuad) {
4252 MaskV.push_back((idx & 3) + 4);
4255 MaskV.push_back(-1);
4258 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4262 // In case BestHi & BestLo were both -1, which means each quadword has a word
4263 // from each of the four input quadwords, calculate the InOrder bitvector now
4264 // before falling through to the insert/extract cleanup.
4265 if (BestLoQuad == -1 && BestHiQuad == -1) {
4267 for (int i = 0; i != 8; ++i)
4268 if (MaskVals[i] < 0 || MaskVals[i] == i)
4272 // The other elements are put in the right place using pextrw and pinsrw.
4273 for (unsigned i = 0; i != 8; ++i) {
4276 int EltIdx = MaskVals[i];
4279 SDValue ExtOp = (EltIdx < 8)
4280 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4281 DAG.getIntPtrConstant(EltIdx))
4282 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4283 DAG.getIntPtrConstant(EltIdx - 8));
4284 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4285 DAG.getIntPtrConstant(i));
4290 // v16i8 shuffles - Prefer shuffles in the following order:
4291 // 1. [ssse3] 1 x pshufb
4292 // 2. [ssse3] 2 x pshufb + 1 x por
4293 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4295 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4297 const X86TargetLowering &TLI) {
4298 SDValue V1 = SVOp->getOperand(0);
4299 SDValue V2 = SVOp->getOperand(1);
4300 DebugLoc dl = SVOp->getDebugLoc();
4301 SmallVector<int, 16> MaskVals;
4302 SVOp->getMask(MaskVals);
4304 // If we have SSSE3, case 1 is generated when all result bytes come from
4305 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4306 // present, fall back to case 3.
4307 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4310 for (unsigned i = 0; i < 16; ++i) {
4311 int EltIdx = MaskVals[i];
4320 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4321 if (TLI.getSubtarget()->hasSSSE3()) {
4322 SmallVector<SDValue,16> pshufbMask;
4324 // If all result elements are from one input vector, then only translate
4325 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4327 // Otherwise, we have elements from both input vectors, and must zero out
4328 // elements that come from V2 in the first mask, and V1 in the second mask
4329 // so that we can OR them together.
4330 bool TwoInputs = !(V1Only || V2Only);
4331 for (unsigned i = 0; i != 16; ++i) {
4332 int EltIdx = MaskVals[i];
4333 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4334 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4337 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4339 // If all the elements are from V2, assign it to V1 and return after
4340 // building the first pshufb.
4343 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4344 DAG.getNode(ISD::BUILD_VECTOR, dl,
4345 MVT::v16i8, &pshufbMask[0], 16));
4349 // Calculate the shuffle mask for the second input, shuffle it, and
4350 // OR it with the first shuffled input.
4352 for (unsigned i = 0; i != 16; ++i) {
4353 int EltIdx = MaskVals[i];
4355 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4358 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4360 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4361 DAG.getNode(ISD::BUILD_VECTOR, dl,
4362 MVT::v16i8, &pshufbMask[0], 16));
4363 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4366 // No SSSE3 - Calculate in place words and then fix all out of place words
4367 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4368 // the 16 different words that comprise the two doublequadword input vectors.
4369 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4370 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4371 SDValue NewV = V2Only ? V2 : V1;
4372 for (int i = 0; i != 8; ++i) {
4373 int Elt0 = MaskVals[i*2];
4374 int Elt1 = MaskVals[i*2+1];
4376 // This word of the result is all undef, skip it.
4377 if (Elt0 < 0 && Elt1 < 0)
4380 // This word of the result is already in the correct place, skip it.
4381 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4383 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4386 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4387 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4390 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4391 // using a single extract together, load it and store it.
4392 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4393 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4394 DAG.getIntPtrConstant(Elt1 / 2));
4395 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4396 DAG.getIntPtrConstant(i));
4400 // If Elt1 is defined, extract it from the appropriate source. If the
4401 // source byte is not also odd, shift the extracted word left 8 bits
4402 // otherwise clear the bottom 8 bits if we need to do an or.
4404 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4405 DAG.getIntPtrConstant(Elt1 / 2));
4406 if ((Elt1 & 1) == 0)
4407 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4408 DAG.getConstant(8, TLI.getShiftAmountTy()));
4410 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4411 DAG.getConstant(0xFF00, MVT::i16));
4413 // If Elt0 is defined, extract it from the appropriate source. If the
4414 // source byte is not also even, shift the extracted word right 8 bits. If
4415 // Elt1 was also defined, OR the extracted values together before
4416 // inserting them in the result.
4418 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4419 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4420 if ((Elt0 & 1) != 0)
4421 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4422 DAG.getConstant(8, TLI.getShiftAmountTy()));
4424 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4425 DAG.getConstant(0x00FF, MVT::i16));
4426 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4429 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4430 DAG.getIntPtrConstant(i));
4432 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4435 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4436 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
4437 /// done when every pair / quad of shuffle mask elements point to elements in
4438 /// the right sequence. e.g.
4439 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4441 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4443 const TargetLowering &TLI, DebugLoc dl) {
4444 EVT VT = SVOp->getValueType(0);
4445 SDValue V1 = SVOp->getOperand(0);
4446 SDValue V2 = SVOp->getOperand(1);
4447 unsigned NumElems = VT.getVectorNumElements();
4448 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4449 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4450 EVT MaskEltVT = MaskVT.getVectorElementType();
4452 switch (VT.getSimpleVT().SimpleTy) {
4453 default: assert(false && "Unexpected!");
4454 case MVT::v4f32: NewVT = MVT::v2f64; break;
4455 case MVT::v4i32: NewVT = MVT::v2i64; break;
4456 case MVT::v8i16: NewVT = MVT::v4i32; break;
4457 case MVT::v16i8: NewVT = MVT::v4i32; break;
4460 if (NewWidth == 2) {
4466 int Scale = NumElems / NewWidth;
4467 SmallVector<int, 8> MaskVec;
4468 for (unsigned i = 0; i < NumElems; i += Scale) {
4470 for (int j = 0; j < Scale; ++j) {
4471 int EltIdx = SVOp->getMaskElt(i+j);
4475 StartIdx = EltIdx - (EltIdx % Scale);
4476 if (EltIdx != StartIdx + j)
4480 MaskVec.push_back(-1);
4482 MaskVec.push_back(StartIdx / Scale);
4485 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4486 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4487 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4490 /// getVZextMovL - Return a zero-extending vector move low node.
4492 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4493 SDValue SrcOp, SelectionDAG &DAG,
4494 const X86Subtarget *Subtarget, DebugLoc dl) {
4495 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4496 LoadSDNode *LD = NULL;
4497 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4498 LD = dyn_cast<LoadSDNode>(SrcOp);
4500 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4502 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4503 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4504 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4505 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4506 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4508 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4509 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4510 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4511 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4519 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4520 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4521 DAG.getNode(ISD::BIT_CONVERT, dl,
4525 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4528 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4529 SDValue V1 = SVOp->getOperand(0);
4530 SDValue V2 = SVOp->getOperand(1);
4531 DebugLoc dl = SVOp->getDebugLoc();
4532 EVT VT = SVOp->getValueType(0);
4534 SmallVector<std::pair<int, int>, 8> Locs;
4536 SmallVector<int, 8> Mask1(4U, -1);
4537 SmallVector<int, 8> PermMask;
4538 SVOp->getMask(PermMask);
4542 for (unsigned i = 0; i != 4; ++i) {
4543 int Idx = PermMask[i];
4545 Locs[i] = std::make_pair(-1, -1);
4547 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4549 Locs[i] = std::make_pair(0, NumLo);
4553 Locs[i] = std::make_pair(1, NumHi);
4555 Mask1[2+NumHi] = Idx;
4561 if (NumLo <= 2 && NumHi <= 2) {
4562 // If no more than two elements come from either vector. This can be
4563 // implemented with two shuffles. First shuffle gather the elements.
4564 // The second shuffle, which takes the first shuffle as both of its
4565 // vector operands, put the elements into the right order.
4566 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4568 SmallVector<int, 8> Mask2(4U, -1);
4570 for (unsigned i = 0; i != 4; ++i) {
4571 if (Locs[i].first == -1)
4574 unsigned Idx = (i < 2) ? 0 : 4;
4575 Idx += Locs[i].first * 2 + Locs[i].second;
4580 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4581 } else if (NumLo == 3 || NumHi == 3) {
4582 // Otherwise, we must have three elements from one vector, call it X, and
4583 // one element from the other, call it Y. First, use a shufps to build an
4584 // intermediate vector with the one element from Y and the element from X
4585 // that will be in the same half in the final destination (the indexes don't
4586 // matter). Then, use a shufps to build the final vector, taking the half
4587 // containing the element from Y from the intermediate, and the other half
4590 // Normalize it so the 3 elements come from V1.
4591 CommuteVectorShuffleMask(PermMask, VT);
4595 // Find the element from V2.
4597 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4598 int Val = PermMask[HiIndex];
4605 Mask1[0] = PermMask[HiIndex];
4607 Mask1[2] = PermMask[HiIndex^1];
4609 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4612 Mask1[0] = PermMask[0];
4613 Mask1[1] = PermMask[1];
4614 Mask1[2] = HiIndex & 1 ? 6 : 4;
4615 Mask1[3] = HiIndex & 1 ? 4 : 6;
4616 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4618 Mask1[0] = HiIndex & 1 ? 2 : 0;
4619 Mask1[1] = HiIndex & 1 ? 0 : 2;
4620 Mask1[2] = PermMask[2];
4621 Mask1[3] = PermMask[3];
4626 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4630 // Break it into (shuffle shuffle_hi, shuffle_lo).
4632 SmallVector<int,8> LoMask(4U, -1);
4633 SmallVector<int,8> HiMask(4U, -1);
4635 SmallVector<int,8> *MaskPtr = &LoMask;
4636 unsigned MaskIdx = 0;
4639 for (unsigned i = 0; i != 4; ++i) {
4646 int Idx = PermMask[i];
4648 Locs[i] = std::make_pair(-1, -1);
4649 } else if (Idx < 4) {
4650 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4651 (*MaskPtr)[LoIdx] = Idx;
4654 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4655 (*MaskPtr)[HiIdx] = Idx;
4660 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4661 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4662 SmallVector<int, 8> MaskOps;
4663 for (unsigned i = 0; i != 4; ++i) {
4664 if (Locs[i].first == -1) {
4665 MaskOps.push_back(-1);
4667 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4668 MaskOps.push_back(Idx);
4671 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4675 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
4676 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4677 SDValue V1 = Op.getOperand(0);
4678 SDValue V2 = Op.getOperand(1);
4679 EVT VT = Op.getValueType();
4680 DebugLoc dl = Op.getDebugLoc();
4681 unsigned NumElems = VT.getVectorNumElements();
4682 bool isMMX = VT.getSizeInBits() == 64;
4683 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4684 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4685 bool V1IsSplat = false;
4686 bool V2IsSplat = false;
4688 if (isZeroShuffle(SVOp))
4689 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4691 // Promote splats to v4f32.
4692 if (SVOp->isSplat()) {
4693 if (isMMX || NumElems < 4)
4695 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4698 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4700 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4701 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4702 if (NewOp.getNode())
4703 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4704 LowerVECTOR_SHUFFLE(NewOp, DAG));
4705 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4706 // FIXME: Figure out a cleaner way to do this.
4707 // Try to make use of movq to zero out the top part.
4708 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4709 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4710 if (NewOp.getNode()) {
4711 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4712 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4713 DAG, Subtarget, dl);
4715 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4716 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4717 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4718 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4719 DAG, Subtarget, dl);
4723 if (X86::isPSHUFDMask(SVOp))
4726 // Check if this can be converted into a logical shift.
4727 bool isLeft = false;
4730 bool isShift = getSubtarget()->hasSSE2() &&
4731 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4732 if (isShift && ShVal.hasOneUse()) {
4733 // If the shifted value has multiple uses, it may be cheaper to use
4734 // v_set0 + movlhps or movhlps, etc.
4735 EVT EltVT = VT.getVectorElementType();
4736 ShAmt *= EltVT.getSizeInBits();
4737 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4740 if (X86::isMOVLMask(SVOp)) {
4743 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4744 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4749 // FIXME: fold these into legal mask.
4750 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4751 X86::isMOVSLDUPMask(SVOp) ||
4752 X86::isMOVHLPSMask(SVOp) ||
4753 X86::isMOVLHPSMask(SVOp) ||
4754 X86::isMOVLPMask(SVOp)))
4757 if (ShouldXformToMOVHLPS(SVOp) ||
4758 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4759 return CommuteVectorShuffle(SVOp, DAG);
4762 // No better options. Use a vshl / vsrl.
4763 EVT EltVT = VT.getVectorElementType();
4764 ShAmt *= EltVT.getSizeInBits();
4765 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4768 bool Commuted = false;
4769 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4770 // 1,1,1,1 -> v8i16 though.
4771 V1IsSplat = isSplatVector(V1.getNode());
4772 V2IsSplat = isSplatVector(V2.getNode());
4774 // Canonicalize the splat or undef, if present, to be on the RHS.
4775 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4776 Op = CommuteVectorShuffle(SVOp, DAG);
4777 SVOp = cast<ShuffleVectorSDNode>(Op);
4778 V1 = SVOp->getOperand(0);
4779 V2 = SVOp->getOperand(1);
4780 std::swap(V1IsSplat, V2IsSplat);
4781 std::swap(V1IsUndef, V2IsUndef);
4785 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4786 // Shuffling low element of v1 into undef, just return v1.
4789 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4790 // the instruction selector will not match, so get a canonical MOVL with
4791 // swapped operands to undo the commute.
4792 return getMOVL(DAG, dl, VT, V2, V1);
4795 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4796 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4797 X86::isUNPCKLMask(SVOp) ||
4798 X86::isUNPCKHMask(SVOp))
4802 // Normalize mask so all entries that point to V2 points to its first
4803 // element then try to match unpck{h|l} again. If match, return a
4804 // new vector_shuffle with the corrected mask.
4805 SDValue NewMask = NormalizeMask(SVOp, DAG);
4806 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4807 if (NSVOp != SVOp) {
4808 if (X86::isUNPCKLMask(NSVOp, true)) {
4810 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4817 // Commute is back and try unpck* again.
4818 // FIXME: this seems wrong.
4819 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4820 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4821 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4822 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4823 X86::isUNPCKLMask(NewSVOp) ||
4824 X86::isUNPCKHMask(NewSVOp))
4828 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4830 // Normalize the node to match x86 shuffle ops if needed
4831 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4832 return CommuteVectorShuffle(SVOp, DAG);
4834 // Check for legal shuffle and return?
4835 SmallVector<int, 16> PermMask;
4836 SVOp->getMask(PermMask);
4837 if (isShuffleMaskLegal(PermMask, VT))
4840 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4841 if (VT == MVT::v8i16) {
4842 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4843 if (NewOp.getNode())
4847 if (VT == MVT::v16i8) {
4848 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4849 if (NewOp.getNode())
4853 // Handle all 4 wide cases with a number of shuffles except for MMX.
4854 if (NumElems == 4 && !isMMX)
4855 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4861 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4862 SelectionDAG &DAG) const {
4863 EVT VT = Op.getValueType();
4864 DebugLoc dl = Op.getDebugLoc();
4865 if (VT.getSizeInBits() == 8) {
4866 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4867 Op.getOperand(0), Op.getOperand(1));
4868 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4869 DAG.getValueType(VT));
4870 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4871 } else if (VT.getSizeInBits() == 16) {
4872 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4873 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4875 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4876 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4877 DAG.getNode(ISD::BIT_CONVERT, dl,
4881 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4882 Op.getOperand(0), Op.getOperand(1));
4883 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4884 DAG.getValueType(VT));
4885 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4886 } else if (VT == MVT::f32) {
4887 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4888 // the result back to FR32 register. It's only worth matching if the
4889 // result has a single use which is a store or a bitcast to i32. And in
4890 // the case of a store, it's not worth it if the index is a constant 0,
4891 // because a MOVSSmr can be used instead, which is smaller and faster.
4892 if (!Op.hasOneUse())
4894 SDNode *User = *Op.getNode()->use_begin();
4895 if ((User->getOpcode() != ISD::STORE ||
4896 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4897 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4898 (User->getOpcode() != ISD::BIT_CONVERT ||
4899 User->getValueType(0) != MVT::i32))
4901 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4902 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4905 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4906 } else if (VT == MVT::i32) {
4907 // ExtractPS works with constant index.
4908 if (isa<ConstantSDNode>(Op.getOperand(1)))
4916 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
4917 SelectionDAG &DAG) const {
4918 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4921 if (Subtarget->hasSSE41()) {
4922 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4927 EVT VT = Op.getValueType();
4928 DebugLoc dl = Op.getDebugLoc();
4929 // TODO: handle v16i8.
4930 if (VT.getSizeInBits() == 16) {
4931 SDValue Vec = Op.getOperand(0);
4932 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4934 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4935 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4936 DAG.getNode(ISD::BIT_CONVERT, dl,
4939 // Transform it so it match pextrw which produces a 32-bit result.
4940 EVT EltVT = MVT::i32;
4941 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4942 Op.getOperand(0), Op.getOperand(1));
4943 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4944 DAG.getValueType(VT));
4945 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4946 } else if (VT.getSizeInBits() == 32) {
4947 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4951 // SHUFPS the element to the lowest double word, then movss.
4952 int Mask[4] = { Idx, -1, -1, -1 };
4953 EVT VVT = Op.getOperand(0).getValueType();
4954 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4955 DAG.getUNDEF(VVT), Mask);
4956 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4957 DAG.getIntPtrConstant(0));
4958 } else if (VT.getSizeInBits() == 64) {
4959 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4960 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4961 // to match extract_elt for f64.
4962 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4966 // UNPCKHPD the element to the lowest double word, then movsd.
4967 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4968 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4969 int Mask[2] = { 1, -1 };
4970 EVT VVT = Op.getOperand(0).getValueType();
4971 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4972 DAG.getUNDEF(VVT), Mask);
4973 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4974 DAG.getIntPtrConstant(0));
4981 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
4982 SelectionDAG &DAG) const {
4983 EVT VT = Op.getValueType();
4984 EVT EltVT = VT.getVectorElementType();
4985 DebugLoc dl = Op.getDebugLoc();
4987 SDValue N0 = Op.getOperand(0);
4988 SDValue N1 = Op.getOperand(1);
4989 SDValue N2 = Op.getOperand(2);
4991 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
4992 isa<ConstantSDNode>(N2)) {
4994 if (VT == MVT::v8i16)
4995 Opc = X86ISD::PINSRW;
4996 else if (VT == MVT::v4i16)
4997 Opc = X86ISD::MMX_PINSRW;
4998 else if (VT == MVT::v16i8)
4999 Opc = X86ISD::PINSRB;
5001 Opc = X86ISD::PINSRB;
5003 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
5005 if (N1.getValueType() != MVT::i32)
5006 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5007 if (N2.getValueType() != MVT::i32)
5008 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5009 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
5010 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
5011 // Bits [7:6] of the constant are the source select. This will always be
5012 // zero here. The DAG Combiner may combine an extract_elt index into these
5013 // bits. For example (insert (extract, 3), 2) could be matched by putting
5014 // the '3' into bits [7:6] of X86ISD::INSERTPS.
5015 // Bits [5:4] of the constant are the destination select. This is the
5016 // value of the incoming immediate.
5017 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
5018 // combine either bitwise AND or insert of float 0.0 to set these bits.
5019 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
5020 // Create this as a scalar to vector..
5021 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
5022 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
5023 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
5024 // PINSR* works with constant index.
5031 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
5032 EVT VT = Op.getValueType();
5033 EVT EltVT = VT.getVectorElementType();
5035 if (Subtarget->hasSSE41())
5036 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
5038 if (EltVT == MVT::i8)
5041 DebugLoc dl = Op.getDebugLoc();
5042 SDValue N0 = Op.getOperand(0);
5043 SDValue N1 = Op.getOperand(1);
5044 SDValue N2 = Op.getOperand(2);
5046 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
5047 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
5048 // as its second argument.
5049 if (N1.getValueType() != MVT::i32)
5050 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5051 if (N2.getValueType() != MVT::i32)
5052 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5053 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW,
5054 dl, VT, N0, N1, N2);
5060 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5061 DebugLoc dl = Op.getDebugLoc();
5062 if (Op.getValueType() == MVT::v2f32)
5063 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
5064 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
5065 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
5066 Op.getOperand(0))));
5068 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
5069 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
5071 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
5072 EVT VT = MVT::v2i32;
5073 switch (Op.getValueType().getSimpleVT().SimpleTy) {
5080 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
5081 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
5084 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
5085 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
5086 // one of the above mentioned nodes. It has to be wrapped because otherwise
5087 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
5088 // be used to form addressing mode. These wrapped nodes will be selected
5091 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
5092 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
5094 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5096 unsigned char OpFlag = 0;
5097 unsigned WrapperKind = X86ISD::Wrapper;
5098 CodeModel::Model M = getTargetMachine().getCodeModel();
5100 if (Subtarget->isPICStyleRIPRel() &&
5101 (M == CodeModel::Small || M == CodeModel::Kernel))
5102 WrapperKind = X86ISD::WrapperRIP;
5103 else if (Subtarget->isPICStyleGOT())
5104 OpFlag = X86II::MO_GOTOFF;
5105 else if (Subtarget->isPICStyleStubPIC())
5106 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5108 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
5110 CP->getOffset(), OpFlag);
5111 DebugLoc DL = CP->getDebugLoc();
5112 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5113 // With PIC, the address is actually $g + Offset.
5115 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5116 DAG.getNode(X86ISD::GlobalBaseReg,
5117 DebugLoc(), getPointerTy()),
5124 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
5125 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
5127 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5129 unsigned char OpFlag = 0;
5130 unsigned WrapperKind = X86ISD::Wrapper;
5131 CodeModel::Model M = getTargetMachine().getCodeModel();
5133 if (Subtarget->isPICStyleRIPRel() &&
5134 (M == CodeModel::Small || M == CodeModel::Kernel))
5135 WrapperKind = X86ISD::WrapperRIP;
5136 else if (Subtarget->isPICStyleGOT())
5137 OpFlag = X86II::MO_GOTOFF;
5138 else if (Subtarget->isPICStyleStubPIC())
5139 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5141 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
5143 DebugLoc DL = JT->getDebugLoc();
5144 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5146 // With PIC, the address is actually $g + Offset.
5148 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5149 DAG.getNode(X86ISD::GlobalBaseReg,
5150 DebugLoc(), getPointerTy()),
5158 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
5159 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5161 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5163 unsigned char OpFlag = 0;
5164 unsigned WrapperKind = X86ISD::Wrapper;
5165 CodeModel::Model M = getTargetMachine().getCodeModel();
5167 if (Subtarget->isPICStyleRIPRel() &&
5168 (M == CodeModel::Small || M == CodeModel::Kernel))
5169 WrapperKind = X86ISD::WrapperRIP;
5170 else if (Subtarget->isPICStyleGOT())
5171 OpFlag = X86II::MO_GOTOFF;
5172 else if (Subtarget->isPICStyleStubPIC())
5173 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5175 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5177 DebugLoc DL = Op.getDebugLoc();
5178 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5181 // With PIC, the address is actually $g + Offset.
5182 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5183 !Subtarget->is64Bit()) {
5184 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5185 DAG.getNode(X86ISD::GlobalBaseReg,
5186 DebugLoc(), getPointerTy()),
5194 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
5195 // Create the TargetBlockAddressAddress node.
5196 unsigned char OpFlags =
5197 Subtarget->ClassifyBlockAddressReference();
5198 CodeModel::Model M = getTargetMachine().getCodeModel();
5199 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5200 DebugLoc dl = Op.getDebugLoc();
5201 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5202 /*isTarget=*/true, OpFlags);
5204 if (Subtarget->isPICStyleRIPRel() &&
5205 (M == CodeModel::Small || M == CodeModel::Kernel))
5206 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5208 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5210 // With PIC, the address is actually $g + Offset.
5211 if (isGlobalRelativeToPICBase(OpFlags)) {
5212 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5213 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5221 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5223 SelectionDAG &DAG) const {
5224 // Create the TargetGlobalAddress node, folding in the constant
5225 // offset if it is legal.
5226 unsigned char OpFlags =
5227 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5228 CodeModel::Model M = getTargetMachine().getCodeModel();
5230 if (OpFlags == X86II::MO_NO_FLAG &&
5231 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5232 // A direct static reference to a global.
5233 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
5236 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
5239 if (Subtarget->isPICStyleRIPRel() &&
5240 (M == CodeModel::Small || M == CodeModel::Kernel))
5241 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5243 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5245 // With PIC, the address is actually $g + Offset.
5246 if (isGlobalRelativeToPICBase(OpFlags)) {
5247 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5248 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5252 // For globals that require a load from a stub to get the address, emit the
5254 if (isGlobalStubReference(OpFlags))
5255 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
5256 PseudoSourceValue::getGOT(), 0, false, false, 0);
5258 // If there was a non-zero offset that we didn't fold, create an explicit
5261 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
5262 DAG.getConstant(Offset, getPointerTy()));
5268 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
5269 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
5270 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
5271 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
5275 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
5276 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
5277 unsigned char OperandFlags) {
5278 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5279 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5280 DebugLoc dl = GA->getDebugLoc();
5281 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
5282 GA->getValueType(0),
5286 SDValue Ops[] = { Chain, TGA, *InFlag };
5287 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
5289 SDValue Ops[] = { Chain, TGA };
5290 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
5293 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5294 MFI->setAdjustsStack(true);
5296 SDValue Flag = Chain.getValue(1);
5297 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
5300 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
5302 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5305 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
5306 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
5307 DAG.getNode(X86ISD::GlobalBaseReg,
5308 DebugLoc(), PtrVT), InFlag);
5309 InFlag = Chain.getValue(1);
5311 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
5314 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
5316 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5318 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
5319 X86::RAX, X86II::MO_TLSGD);
5322 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
5323 // "local exec" model.
5324 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5325 const EVT PtrVT, TLSModel::Model model,
5327 DebugLoc dl = GA->getDebugLoc();
5328 // Get the Thread Pointer
5329 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
5331 DAG.getRegister(is64Bit? X86::FS : X86::GS,
5334 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
5335 NULL, 0, false, false, 0);
5337 unsigned char OperandFlags = 0;
5338 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
5340 unsigned WrapperKind = X86ISD::Wrapper;
5341 if (model == TLSModel::LocalExec) {
5342 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
5343 } else if (is64Bit) {
5344 assert(model == TLSModel::InitialExec);
5345 OperandFlags = X86II::MO_GOTTPOFF;
5346 WrapperKind = X86ISD::WrapperRIP;
5348 assert(model == TLSModel::InitialExec);
5349 OperandFlags = X86II::MO_INDNTPOFF;
5352 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
5354 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5355 GA->getOffset(), OperandFlags);
5356 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
5358 if (model == TLSModel::InitialExec)
5359 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
5360 PseudoSourceValue::getGOT(), 0, false, false, 0);
5362 // The address of the thread local variable is the add of the thread
5363 // pointer with the offset of the variable.
5364 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5368 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
5369 // TODO: implement the "local dynamic" model
5370 // TODO: implement the "initial exec"model for pic executables
5371 assert(Subtarget->isTargetELF() &&
5372 "TLS not implemented for non-ELF targets");
5373 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5374 const GlobalValue *GV = GA->getGlobal();
5376 // If GV is an alias then use the aliasee for determining
5377 // thread-localness.
5378 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5379 GV = GA->resolveAliasedGlobal(false);
5381 TLSModel::Model model = getTLSModel(GV,
5382 getTargetMachine().getRelocationModel());
5385 case TLSModel::GeneralDynamic:
5386 case TLSModel::LocalDynamic: // not implemented
5387 if (Subtarget->is64Bit())
5388 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5389 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5391 case TLSModel::InitialExec:
5392 case TLSModel::LocalExec:
5393 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5394 Subtarget->is64Bit());
5397 llvm_unreachable("Unreachable");
5402 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5403 /// take a 2 x i32 value to shift plus a shift amount.
5404 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
5405 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5406 EVT VT = Op.getValueType();
5407 unsigned VTBits = VT.getSizeInBits();
5408 DebugLoc dl = Op.getDebugLoc();
5409 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5410 SDValue ShOpLo = Op.getOperand(0);
5411 SDValue ShOpHi = Op.getOperand(1);
5412 SDValue ShAmt = Op.getOperand(2);
5413 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5414 DAG.getConstant(VTBits - 1, MVT::i8))
5415 : DAG.getConstant(0, VT);
5418 if (Op.getOpcode() == ISD::SHL_PARTS) {
5419 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5420 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5422 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5423 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5426 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5427 DAG.getConstant(VTBits, MVT::i8));
5428 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
5429 AndNode, DAG.getConstant(0, MVT::i8));
5432 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5433 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5434 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5436 if (Op.getOpcode() == ISD::SHL_PARTS) {
5437 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5438 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5440 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5441 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5444 SDValue Ops[2] = { Lo, Hi };
5445 return DAG.getMergeValues(Ops, 2, dl);
5448 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
5449 SelectionDAG &DAG) const {
5450 EVT SrcVT = Op.getOperand(0).getValueType();
5452 if (SrcVT.isVector()) {
5453 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5459 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5460 "Unknown SINT_TO_FP to lower!");
5462 // These are really Legal; return the operand so the caller accepts it as
5464 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5466 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5467 Subtarget->is64Bit()) {
5471 DebugLoc dl = Op.getDebugLoc();
5472 unsigned Size = SrcVT.getSizeInBits()/8;
5473 MachineFunction &MF = DAG.getMachineFunction();
5474 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5475 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5476 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5478 PseudoSourceValue::getFixedStack(SSFI), 0,
5480 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5483 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5485 SelectionDAG &DAG) const {
5487 DebugLoc dl = Op.getDebugLoc();
5489 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5491 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5493 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5494 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
5495 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5496 Tys, Ops, array_lengthof(Ops));
5499 Chain = Result.getValue(1);
5500 SDValue InFlag = Result.getValue(2);
5502 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5503 // shouldn't be necessary except that RFP cannot be live across
5504 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5505 MachineFunction &MF = DAG.getMachineFunction();
5506 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5507 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5508 Tys = DAG.getVTList(MVT::Other);
5510 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
5512 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
5513 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5514 PseudoSourceValue::getFixedStack(SSFI), 0,
5521 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5522 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
5523 SelectionDAG &DAG) const {
5524 // This algorithm is not obvious. Here it is in C code, more or less:
5526 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5527 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5528 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5530 // Copy ints to xmm registers.
5531 __m128i xh = _mm_cvtsi32_si128( hi );
5532 __m128i xl = _mm_cvtsi32_si128( lo );
5534 // Combine into low half of a single xmm register.
5535 __m128i x = _mm_unpacklo_epi32( xh, xl );
5539 // Merge in appropriate exponents to give the integer bits the right
5541 x = _mm_unpacklo_epi32( x, exp );
5543 // Subtract away the biases to deal with the IEEE-754 double precision
5545 d = _mm_sub_pd( (__m128d) x, bias );
5547 // All conversions up to here are exact. The correctly rounded result is
5548 // calculated using the current rounding mode using the following
5550 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5551 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5552 // store doesn't really need to be here (except
5553 // maybe to zero the other double)
5558 DebugLoc dl = Op.getDebugLoc();
5559 LLVMContext *Context = DAG.getContext();
5561 // Build some magic constants.
5562 std::vector<Constant*> CV0;
5563 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5564 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5565 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5566 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5567 Constant *C0 = ConstantVector::get(CV0);
5568 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5570 std::vector<Constant*> CV1;
5572 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5574 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5575 Constant *C1 = ConstantVector::get(CV1);
5576 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5578 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5579 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5581 DAG.getIntPtrConstant(1)));
5582 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5583 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5585 DAG.getIntPtrConstant(0)));
5586 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5587 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5588 PseudoSourceValue::getConstantPool(), 0,
5590 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5591 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5592 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5593 PseudoSourceValue::getConstantPool(), 0,
5595 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5597 // Add the halves; easiest way is to swap them into another reg first.
5598 int ShufMask[2] = { 1, -1 };
5599 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5600 DAG.getUNDEF(MVT::v2f64), ShufMask);
5601 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5602 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5603 DAG.getIntPtrConstant(0));
5606 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5607 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
5608 SelectionDAG &DAG) const {
5609 DebugLoc dl = Op.getDebugLoc();
5610 // FP constant to bias correct the final result.
5611 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5614 // Load the 32-bit value into an XMM register.
5615 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5616 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5618 DAG.getIntPtrConstant(0)));
5620 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5621 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5622 DAG.getIntPtrConstant(0));
5624 // Or the load with the bias.
5625 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5626 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5627 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5629 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5630 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5631 MVT::v2f64, Bias)));
5632 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5633 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5634 DAG.getIntPtrConstant(0));
5636 // Subtract the bias.
5637 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5639 // Handle final rounding.
5640 EVT DestVT = Op.getValueType();
5642 if (DestVT.bitsLT(MVT::f64)) {
5643 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5644 DAG.getIntPtrConstant(0));
5645 } else if (DestVT.bitsGT(MVT::f64)) {
5646 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5649 // Handle final rounding.
5653 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
5654 SelectionDAG &DAG) const {
5655 SDValue N0 = Op.getOperand(0);
5656 DebugLoc dl = Op.getDebugLoc();
5658 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
5659 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5660 // the optimization here.
5661 if (DAG.SignBitIsZero(N0))
5662 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5664 EVT SrcVT = N0.getValueType();
5665 EVT DstVT = Op.getValueType();
5666 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
5667 return LowerUINT_TO_FP_i64(Op, DAG);
5668 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
5669 return LowerUINT_TO_FP_i32(Op, DAG);
5671 // Make a 64-bit buffer, and use it to build an FILD.
5672 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5673 if (SrcVT == MVT::i32) {
5674 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5675 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5676 getPointerTy(), StackSlot, WordOff);
5677 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5678 StackSlot, NULL, 0, false, false, 0);
5679 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5680 OffsetSlot, NULL, 0, false, false, 0);
5681 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5685 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
5686 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5687 StackSlot, NULL, 0, false, false, 0);
5688 // For i64 source, we need to add the appropriate power of 2 if the input
5689 // was negative. This is the same as the optimization in
5690 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
5691 // we must be careful to do the computation in x87 extended precision, not
5692 // in SSE. (The generic code can't know it's OK to do this, or how to.)
5693 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
5694 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
5695 SDValue Fild = DAG.getNode(X86ISD::FILD, dl, Tys, Ops, 3);
5697 APInt FF(32, 0x5F800000ULL);
5699 // Check whether the sign bit is set.
5700 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
5701 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
5704 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
5705 SDValue FudgePtr = DAG.getConstantPool(
5706 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
5709 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
5710 SDValue Zero = DAG.getIntPtrConstant(0);
5711 SDValue Four = DAG.getIntPtrConstant(4);
5712 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
5714 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
5716 // Load the value out, extending it from f32 to f80.
5717 // FIXME: Avoid the extend by constructing the right constant pool?
5718 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
5719 FudgePtr, PseudoSourceValue::getConstantPool(),
5720 0, MVT::f32, false, false, 4);
5721 // Extend everything to 80 bits to force it to be done on x87.
5722 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
5723 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
5726 std::pair<SDValue,SDValue> X86TargetLowering::
5727 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
5728 DebugLoc dl = Op.getDebugLoc();
5730 EVT DstTy = Op.getValueType();
5733 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5737 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5738 DstTy.getSimpleVT() >= MVT::i16 &&
5739 "Unknown FP_TO_SINT to lower!");
5741 // These are really Legal.
5742 if (DstTy == MVT::i32 &&
5743 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5744 return std::make_pair(SDValue(), SDValue());
5745 if (Subtarget->is64Bit() &&
5746 DstTy == MVT::i64 &&
5747 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5748 return std::make_pair(SDValue(), SDValue());
5750 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5752 MachineFunction &MF = DAG.getMachineFunction();
5753 unsigned MemSize = DstTy.getSizeInBits()/8;
5754 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5755 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5758 switch (DstTy.getSimpleVT().SimpleTy) {
5759 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5760 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5761 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5762 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5765 SDValue Chain = DAG.getEntryNode();
5766 SDValue Value = Op.getOperand(0);
5767 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5768 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5769 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5770 PseudoSourceValue::getFixedStack(SSFI), 0,
5772 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5774 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5776 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5777 Chain = Value.getValue(1);
5778 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5779 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5782 // Build the FP_TO_INT*_IN_MEM
5783 SDValue Ops[] = { Chain, Value, StackSlot };
5784 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5786 return std::make_pair(FIST, StackSlot);
5789 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
5790 SelectionDAG &DAG) const {
5791 if (Op.getValueType().isVector()) {
5792 if (Op.getValueType() == MVT::v2i32 &&
5793 Op.getOperand(0).getValueType() == MVT::v2f64) {
5799 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5800 SDValue FIST = Vals.first, StackSlot = Vals.second;
5801 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5802 if (FIST.getNode() == 0) return Op;
5805 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5806 FIST, StackSlot, NULL, 0, false, false, 0);
5809 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
5810 SelectionDAG &DAG) const {
5811 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5812 SDValue FIST = Vals.first, StackSlot = Vals.second;
5813 assert(FIST.getNode() && "Unexpected failure");
5816 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5817 FIST, StackSlot, NULL, 0, false, false, 0);
5820 SDValue X86TargetLowering::LowerFABS(SDValue Op,
5821 SelectionDAG &DAG) const {
5822 LLVMContext *Context = DAG.getContext();
5823 DebugLoc dl = Op.getDebugLoc();
5824 EVT VT = Op.getValueType();
5827 EltVT = VT.getVectorElementType();
5828 std::vector<Constant*> CV;
5829 if (EltVT == MVT::f64) {
5830 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5834 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5840 Constant *C = ConstantVector::get(CV);
5841 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5842 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5843 PseudoSourceValue::getConstantPool(), 0,
5845 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5848 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
5849 LLVMContext *Context = DAG.getContext();
5850 DebugLoc dl = Op.getDebugLoc();
5851 EVT VT = Op.getValueType();
5854 EltVT = VT.getVectorElementType();
5855 std::vector<Constant*> CV;
5856 if (EltVT == MVT::f64) {
5857 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5861 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5867 Constant *C = ConstantVector::get(CV);
5868 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5869 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5870 PseudoSourceValue::getConstantPool(), 0,
5872 if (VT.isVector()) {
5873 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5874 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5875 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5877 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5879 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5883 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5884 LLVMContext *Context = DAG.getContext();
5885 SDValue Op0 = Op.getOperand(0);
5886 SDValue Op1 = Op.getOperand(1);
5887 DebugLoc dl = Op.getDebugLoc();
5888 EVT VT = Op.getValueType();
5889 EVT SrcVT = Op1.getValueType();
5891 // If second operand is smaller, extend it first.
5892 if (SrcVT.bitsLT(VT)) {
5893 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5896 // And if it is bigger, shrink it first.
5897 if (SrcVT.bitsGT(VT)) {
5898 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5902 // At this point the operands and the result should have the same
5903 // type, and that won't be f80 since that is not custom lowered.
5905 // First get the sign bit of second operand.
5906 std::vector<Constant*> CV;
5907 if (SrcVT == MVT::f64) {
5908 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5909 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5911 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5912 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5913 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5914 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5916 Constant *C = ConstantVector::get(CV);
5917 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5918 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5919 PseudoSourceValue::getConstantPool(), 0,
5921 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5923 // Shift sign bit right or left if the two operands have different types.
5924 if (SrcVT.bitsGT(VT)) {
5925 // Op0 is MVT::f32, Op1 is MVT::f64.
5926 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5927 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5928 DAG.getConstant(32, MVT::i32));
5929 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5930 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5931 DAG.getIntPtrConstant(0));
5934 // Clear first operand sign bit.
5936 if (VT == MVT::f64) {
5937 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5938 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5940 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5941 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5942 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5943 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5945 C = ConstantVector::get(CV);
5946 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5947 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5948 PseudoSourceValue::getConstantPool(), 0,
5950 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5952 // Or the value with the sign bit.
5953 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5956 /// Emit nodes that will be selected as "test Op0,Op0", or something
5958 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5959 SelectionDAG &DAG) const {
5960 DebugLoc dl = Op.getDebugLoc();
5962 // CF and OF aren't always set the way we want. Determine which
5963 // of these we need.
5964 bool NeedCF = false;
5965 bool NeedOF = false;
5967 case X86::COND_A: case X86::COND_AE:
5968 case X86::COND_B: case X86::COND_BE:
5971 case X86::COND_G: case X86::COND_GE:
5972 case X86::COND_L: case X86::COND_LE:
5973 case X86::COND_O: case X86::COND_NO:
5979 // See if we can use the EFLAGS value from the operand instead of
5980 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5981 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5982 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5983 unsigned Opcode = 0;
5984 unsigned NumOperands = 0;
5985 switch (Op.getNode()->getOpcode()) {
5987 // Due to an isel shortcoming, be conservative if this add is
5988 // likely to be selected as part of a load-modify-store
5989 // instruction. When the root node in a match is a store, isel
5990 // doesn't know how to remap non-chain non-flag uses of other
5991 // nodes in the match, such as the ADD in this case. This leads
5992 // to the ADD being left around and reselected, with the result
5993 // being two adds in the output. Alas, even if none our users
5994 // are stores, that doesn't prove we're O.K. Ergo, if we have
5995 // any parents that aren't CopyToReg or SETCC, eschew INC/DEC.
5996 // A better fix seems to require climbing the DAG back to the
5997 // root, and it doesn't seem to be worth the effort.
5998 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5999 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6000 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
6002 if (ConstantSDNode *C =
6003 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
6004 // An add of one will be selected as an INC.
6005 if (C->getAPIntValue() == 1) {
6006 Opcode = X86ISD::INC;
6010 // An add of negative one (subtract of one) will be selected as a DEC.
6011 if (C->getAPIntValue().isAllOnesValue()) {
6012 Opcode = X86ISD::DEC;
6017 // Otherwise use a regular EFLAGS-setting add.
6018 Opcode = X86ISD::ADD;
6022 // If the primary and result isn't used, don't bother using X86ISD::AND,
6023 // because a TEST instruction will be better.
6024 bool NonFlagUse = false;
6025 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6026 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
6028 unsigned UOpNo = UI.getOperandNo();
6029 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
6030 // Look pass truncate.
6031 UOpNo = User->use_begin().getOperandNo();
6032 User = *User->use_begin();
6034 if (User->getOpcode() != ISD::BRCOND &&
6035 User->getOpcode() != ISD::SETCC &&
6036 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
6048 // Due to the ISEL shortcoming noted above, be conservative if this op is
6049 // likely to be selected as part of a load-modify-store instruction.
6050 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6051 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6052 if (UI->getOpcode() == ISD::STORE)
6054 // Otherwise use a regular EFLAGS-setting instruction.
6055 switch (Op.getNode()->getOpcode()) {
6056 case ISD::SUB: Opcode = X86ISD::SUB; break;
6057 case ISD::OR: Opcode = X86ISD::OR; break;
6058 case ISD::XOR: Opcode = X86ISD::XOR; break;
6059 case ISD::AND: Opcode = X86ISD::AND; break;
6060 default: llvm_unreachable("unexpected operator!");
6071 return SDValue(Op.getNode(), 1);
6077 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
6078 SmallVector<SDValue, 4> Ops;
6079 for (unsigned i = 0; i != NumOperands; ++i)
6080 Ops.push_back(Op.getOperand(i));
6081 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
6082 DAG.ReplaceAllUsesWith(Op, New);
6083 return SDValue(New.getNode(), 1);
6087 // Otherwise just emit a CMP with 0, which is the TEST pattern.
6088 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6089 DAG.getConstant(0, Op.getValueType()));
6092 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
6094 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
6095 SelectionDAG &DAG) const {
6096 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
6097 if (C->getAPIntValue() == 0)
6098 return EmitTest(Op0, X86CC, DAG);
6100 DebugLoc dl = Op0.getDebugLoc();
6101 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
6104 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
6105 /// if it's possible.
6106 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
6107 DebugLoc dl, SelectionDAG &DAG) const {
6108 SDValue Op0 = And.getOperand(0);
6109 SDValue Op1 = And.getOperand(1);
6110 if (Op0.getOpcode() == ISD::TRUNCATE)
6111 Op0 = Op0.getOperand(0);
6112 if (Op1.getOpcode() == ISD::TRUNCATE)
6113 Op1 = Op1.getOperand(0);
6116 if (Op1.getOpcode() == ISD::SHL) {
6117 if (ConstantSDNode *And10C = dyn_cast<ConstantSDNode>(Op1.getOperand(0)))
6118 if (And10C->getZExtValue() == 1) {
6120 RHS = Op1.getOperand(1);
6122 } else if (Op0.getOpcode() == ISD::SHL) {
6123 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
6124 if (And00C->getZExtValue() == 1) {
6126 RHS = Op0.getOperand(1);
6128 } else if (Op1.getOpcode() == ISD::Constant) {
6129 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
6130 SDValue AndLHS = Op0;
6131 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
6132 LHS = AndLHS.getOperand(0);
6133 RHS = AndLHS.getOperand(1);
6137 if (LHS.getNode()) {
6138 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
6139 // instruction. Since the shift amount is in-range-or-undefined, we know
6140 // that doing a bittest on the i32 value is ok. We extend to i32 because
6141 // the encoding for the i16 version is larger than the i32 version.
6142 // Also promote i16 to i32 for performance / code size reason.
6143 if (LHS.getValueType() == MVT::i8 ||
6144 LHS.getValueType() == MVT::i16)
6145 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
6147 // If the operand types disagree, extend the shift amount to match. Since
6148 // BT ignores high bits (like shifts) we can use anyextend.
6149 if (LHS.getValueType() != RHS.getValueType())
6150 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
6152 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
6153 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
6154 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6155 DAG.getConstant(Cond, MVT::i8), BT);
6161 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
6162 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
6163 SDValue Op0 = Op.getOperand(0);
6164 SDValue Op1 = Op.getOperand(1);
6165 DebugLoc dl = Op.getDebugLoc();
6166 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6168 // Optimize to BT if possible.
6169 // Lower (X & (1 << N)) == 0 to BT(X, N).
6170 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
6171 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
6172 if (Op0.getOpcode() == ISD::AND &&
6174 Op1.getOpcode() == ISD::Constant &&
6175 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
6176 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6177 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
6178 if (NewSetCC.getNode())
6182 // Look for "(setcc) == / != 1" to avoid unncessary setcc.
6183 if (Op0.getOpcode() == X86ISD::SETCC &&
6184 Op1.getOpcode() == ISD::Constant &&
6185 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
6186 cast<ConstantSDNode>(Op1)->isNullValue()) &&
6187 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6188 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
6189 bool Invert = (CC == ISD::SETNE) ^
6190 cast<ConstantSDNode>(Op1)->isNullValue();
6192 CCode = X86::GetOppositeBranchCondition(CCode);
6193 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6194 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
6197 bool isFP = Op1.getValueType().isFloatingPoint();
6198 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
6199 if (X86CC == X86::COND_INVALID)
6202 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
6204 // Use sbb x, x to materialize carry bit into a GPR.
6205 if (X86CC == X86::COND_B)
6206 return DAG.getNode(ISD::AND, dl, MVT::i8,
6207 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
6208 DAG.getConstant(X86CC, MVT::i8), Cond),
6209 DAG.getConstant(1, MVT::i8));
6211 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6212 DAG.getConstant(X86CC, MVT::i8), Cond);
6215 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
6217 SDValue Op0 = Op.getOperand(0);
6218 SDValue Op1 = Op.getOperand(1);
6219 SDValue CC = Op.getOperand(2);
6220 EVT VT = Op.getValueType();
6221 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
6222 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
6223 DebugLoc dl = Op.getDebugLoc();
6227 EVT VT0 = Op0.getValueType();
6228 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
6229 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
6232 switch (SetCCOpcode) {
6235 case ISD::SETEQ: SSECC = 0; break;
6237 case ISD::SETGT: Swap = true; // Fallthrough
6239 case ISD::SETOLT: SSECC = 1; break;
6241 case ISD::SETGE: Swap = true; // Fallthrough
6243 case ISD::SETOLE: SSECC = 2; break;
6244 case ISD::SETUO: SSECC = 3; break;
6246 case ISD::SETNE: SSECC = 4; break;
6247 case ISD::SETULE: Swap = true;
6248 case ISD::SETUGE: SSECC = 5; break;
6249 case ISD::SETULT: Swap = true;
6250 case ISD::SETUGT: SSECC = 6; break;
6251 case ISD::SETO: SSECC = 7; break;
6254 std::swap(Op0, Op1);
6256 // In the two special cases we can't handle, emit two comparisons.
6258 if (SetCCOpcode == ISD::SETUEQ) {
6260 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
6261 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
6262 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
6264 else if (SetCCOpcode == ISD::SETONE) {
6266 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
6267 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
6268 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
6270 llvm_unreachable("Illegal FP comparison");
6272 // Handle all other FP comparisons here.
6273 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
6276 // We are handling one of the integer comparisons here. Since SSE only has
6277 // GT and EQ comparisons for integer, swapping operands and multiple
6278 // operations may be required for some comparisons.
6279 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
6280 bool Swap = false, Invert = false, FlipSigns = false;
6282 switch (VT.getSimpleVT().SimpleTy) {
6285 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
6287 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
6289 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
6290 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
6293 switch (SetCCOpcode) {
6295 case ISD::SETNE: Invert = true;
6296 case ISD::SETEQ: Opc = EQOpc; break;
6297 case ISD::SETLT: Swap = true;
6298 case ISD::SETGT: Opc = GTOpc; break;
6299 case ISD::SETGE: Swap = true;
6300 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
6301 case ISD::SETULT: Swap = true;
6302 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
6303 case ISD::SETUGE: Swap = true;
6304 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
6307 std::swap(Op0, Op1);
6309 // Since SSE has no unsigned integer comparisons, we need to flip the sign
6310 // bits of the inputs before performing those operations.
6312 EVT EltVT = VT.getVectorElementType();
6313 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
6315 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
6316 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
6318 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
6319 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
6322 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
6324 // If the logical-not of the result is required, perform that now.
6326 Result = DAG.getNOT(dl, Result, VT);
6331 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
6332 static bool isX86LogicalCmp(SDValue Op) {
6333 unsigned Opc = Op.getNode()->getOpcode();
6334 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
6336 if (Op.getResNo() == 1 &&
6337 (Opc == X86ISD::ADD ||
6338 Opc == X86ISD::SUB ||
6339 Opc == X86ISD::SMUL ||
6340 Opc == X86ISD::UMUL ||
6341 Opc == X86ISD::INC ||
6342 Opc == X86ISD::DEC ||
6343 Opc == X86ISD::OR ||
6344 Opc == X86ISD::XOR ||
6345 Opc == X86ISD::AND))
6351 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
6352 bool addTest = true;
6353 SDValue Cond = Op.getOperand(0);
6354 DebugLoc dl = Op.getDebugLoc();
6357 if (Cond.getOpcode() == ISD::SETCC) {
6358 SDValue NewCond = LowerSETCC(Cond, DAG);
6359 if (NewCond.getNode())
6363 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
6364 SDValue Op1 = Op.getOperand(1);
6365 SDValue Op2 = Op.getOperand(2);
6366 if (Cond.getOpcode() == X86ISD::SETCC &&
6367 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
6368 SDValue Cmp = Cond.getOperand(1);
6369 if (Cmp.getOpcode() == X86ISD::CMP) {
6370 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
6371 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
6372 ConstantSDNode *RHSC =
6373 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
6374 if (N1C && N1C->isAllOnesValue() &&
6375 N2C && N2C->isNullValue() &&
6376 RHSC && RHSC->isNullValue()) {
6377 SDValue CmpOp0 = Cmp.getOperand(0);
6378 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6379 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
6380 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
6381 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
6386 // Look pass (and (setcc_carry (cmp ...)), 1).
6387 if (Cond.getOpcode() == ISD::AND &&
6388 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6389 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6390 if (C && C->getAPIntValue() == 1)
6391 Cond = Cond.getOperand(0);
6394 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6395 // setting operand in place of the X86ISD::SETCC.
6396 if (Cond.getOpcode() == X86ISD::SETCC ||
6397 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6398 CC = Cond.getOperand(0);
6400 SDValue Cmp = Cond.getOperand(1);
6401 unsigned Opc = Cmp.getOpcode();
6402 EVT VT = Op.getValueType();
6404 bool IllegalFPCMov = false;
6405 if (VT.isFloatingPoint() && !VT.isVector() &&
6406 !isScalarFPTypeInSSEReg(VT)) // FPStack?
6407 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
6409 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
6410 Opc == X86ISD::BT) { // FIXME
6417 // Look pass the truncate.
6418 if (Cond.getOpcode() == ISD::TRUNCATE)
6419 Cond = Cond.getOperand(0);
6421 // We know the result of AND is compared against zero. Try to match
6423 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6424 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6425 if (NewSetCC.getNode()) {
6426 CC = NewSetCC.getOperand(0);
6427 Cond = NewSetCC.getOperand(1);
6434 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6435 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6438 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
6439 // condition is true.
6440 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
6441 SDValue Ops[] = { Op2, Op1, CC, Cond };
6442 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
6445 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
6446 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
6447 // from the AND / OR.
6448 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
6449 Opc = Op.getOpcode();
6450 if (Opc != ISD::OR && Opc != ISD::AND)
6452 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6453 Op.getOperand(0).hasOneUse() &&
6454 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
6455 Op.getOperand(1).hasOneUse());
6458 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
6459 // 1 and that the SETCC node has a single use.
6460 static bool isXor1OfSetCC(SDValue Op) {
6461 if (Op.getOpcode() != ISD::XOR)
6463 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6464 if (N1C && N1C->getAPIntValue() == 1) {
6465 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6466 Op.getOperand(0).hasOneUse();
6471 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
6472 bool addTest = true;
6473 SDValue Chain = Op.getOperand(0);
6474 SDValue Cond = Op.getOperand(1);
6475 SDValue Dest = Op.getOperand(2);
6476 DebugLoc dl = Op.getDebugLoc();
6479 if (Cond.getOpcode() == ISD::SETCC) {
6480 SDValue NewCond = LowerSETCC(Cond, DAG);
6481 if (NewCond.getNode())
6485 // FIXME: LowerXALUO doesn't handle these!!
6486 else if (Cond.getOpcode() == X86ISD::ADD ||
6487 Cond.getOpcode() == X86ISD::SUB ||
6488 Cond.getOpcode() == X86ISD::SMUL ||
6489 Cond.getOpcode() == X86ISD::UMUL)
6490 Cond = LowerXALUO(Cond, DAG);
6493 // Look pass (and (setcc_carry (cmp ...)), 1).
6494 if (Cond.getOpcode() == ISD::AND &&
6495 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6496 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6497 if (C && C->getAPIntValue() == 1)
6498 Cond = Cond.getOperand(0);
6501 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6502 // setting operand in place of the X86ISD::SETCC.
6503 if (Cond.getOpcode() == X86ISD::SETCC ||
6504 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6505 CC = Cond.getOperand(0);
6507 SDValue Cmp = Cond.getOperand(1);
6508 unsigned Opc = Cmp.getOpcode();
6509 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6510 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6514 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6518 // These can only come from an arithmetic instruction with overflow,
6519 // e.g. SADDO, UADDO.
6520 Cond = Cond.getNode()->getOperand(1);
6527 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6528 SDValue Cmp = Cond.getOperand(0).getOperand(1);
6529 if (CondOpc == ISD::OR) {
6530 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6531 // two branches instead of an explicit OR instruction with a
6533 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6534 isX86LogicalCmp(Cmp)) {
6535 CC = Cond.getOperand(0).getOperand(0);
6536 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6537 Chain, Dest, CC, Cmp);
6538 CC = Cond.getOperand(1).getOperand(0);
6542 } else { // ISD::AND
6543 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6544 // two branches instead of an explicit AND instruction with a
6545 // separate test. However, we only do this if this block doesn't
6546 // have a fall-through edge, because this requires an explicit
6547 // jmp when the condition is false.
6548 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6549 isX86LogicalCmp(Cmp) &&
6550 Op.getNode()->hasOneUse()) {
6551 X86::CondCode CCode =
6552 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6553 CCode = X86::GetOppositeBranchCondition(CCode);
6554 CC = DAG.getConstant(CCode, MVT::i8);
6555 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
6556 // Look for an unconditional branch following this conditional branch.
6557 // We need this because we need to reverse the successors in order
6558 // to implement FCMP_OEQ.
6559 if (User.getOpcode() == ISD::BR) {
6560 SDValue FalseBB = User.getOperand(1);
6562 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
6563 assert(NewBR == User);
6566 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6567 Chain, Dest, CC, Cmp);
6568 X86::CondCode CCode =
6569 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6570 CCode = X86::GetOppositeBranchCondition(CCode);
6571 CC = DAG.getConstant(CCode, MVT::i8);
6577 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6578 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6579 // It should be transformed during dag combiner except when the condition
6580 // is set by a arithmetics with overflow node.
6581 X86::CondCode CCode =
6582 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6583 CCode = X86::GetOppositeBranchCondition(CCode);
6584 CC = DAG.getConstant(CCode, MVT::i8);
6585 Cond = Cond.getOperand(0).getOperand(1);
6591 // Look pass the truncate.
6592 if (Cond.getOpcode() == ISD::TRUNCATE)
6593 Cond = Cond.getOperand(0);
6595 // We know the result of AND is compared against zero. Try to match
6597 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6598 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6599 if (NewSetCC.getNode()) {
6600 CC = NewSetCC.getOperand(0);
6601 Cond = NewSetCC.getOperand(1);
6608 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6609 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6611 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6612 Chain, Dest, CC, Cond);
6616 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6617 // Calls to _alloca is needed to probe the stack when allocating more than 4k
6618 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
6619 // that the guard pages used by the OS virtual memory manager are allocated in
6620 // correct sequence.
6622 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6623 SelectionDAG &DAG) const {
6624 assert(Subtarget->isTargetCygMing() &&
6625 "This should be used only on Cygwin/Mingw targets");
6626 DebugLoc dl = Op.getDebugLoc();
6629 SDValue Chain = Op.getOperand(0);
6630 SDValue Size = Op.getOperand(1);
6631 // FIXME: Ensure alignment here
6635 EVT IntPtr = getPointerTy();
6636 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6638 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6639 Flag = Chain.getValue(1);
6641 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6643 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag);
6644 Flag = Chain.getValue(1);
6646 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6648 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6649 return DAG.getMergeValues(Ops1, 2, dl);
6652 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
6653 MachineFunction &MF = DAG.getMachineFunction();
6654 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
6656 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6657 DebugLoc dl = Op.getDebugLoc();
6659 if (!Subtarget->is64Bit()) {
6660 // vastart just stores the address of the VarArgsFrameIndex slot into the
6661 // memory location argument.
6662 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
6664 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
6669 // gp_offset (0 - 6 * 8)
6670 // fp_offset (48 - 48 + 8 * 16)
6671 // overflow_arg_area (point to parameters coming in memory).
6673 SmallVector<SDValue, 8> MemOps;
6674 SDValue FIN = Op.getOperand(1);
6676 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6677 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
6679 FIN, SV, 0, false, false, 0);
6680 MemOps.push_back(Store);
6683 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6684 FIN, DAG.getIntPtrConstant(4));
6685 Store = DAG.getStore(Op.getOperand(0), dl,
6686 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
6688 FIN, SV, 0, false, false, 0);
6689 MemOps.push_back(Store);
6691 // Store ptr to overflow_arg_area
6692 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6693 FIN, DAG.getIntPtrConstant(4));
6694 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
6696 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0,
6698 MemOps.push_back(Store);
6700 // Store ptr to reg_save_area.
6701 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6702 FIN, DAG.getIntPtrConstant(8));
6703 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
6705 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0,
6707 MemOps.push_back(Store);
6708 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6709 &MemOps[0], MemOps.size());
6712 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
6713 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6714 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6715 SDValue Chain = Op.getOperand(0);
6716 SDValue SrcPtr = Op.getOperand(1);
6717 SDValue SrcSV = Op.getOperand(2);
6719 report_fatal_error("VAArgInst is not yet implemented for x86-64!");
6723 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
6724 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6725 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6726 SDValue Chain = Op.getOperand(0);
6727 SDValue DstPtr = Op.getOperand(1);
6728 SDValue SrcPtr = Op.getOperand(2);
6729 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6730 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6731 DebugLoc dl = Op.getDebugLoc();
6733 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6734 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
6735 false, DstSV, 0, SrcSV, 0);
6739 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
6740 DebugLoc dl = Op.getDebugLoc();
6741 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6743 default: return SDValue(); // Don't custom lower most intrinsics.
6744 // Comparison intrinsics.
6745 case Intrinsic::x86_sse_comieq_ss:
6746 case Intrinsic::x86_sse_comilt_ss:
6747 case Intrinsic::x86_sse_comile_ss:
6748 case Intrinsic::x86_sse_comigt_ss:
6749 case Intrinsic::x86_sse_comige_ss:
6750 case Intrinsic::x86_sse_comineq_ss:
6751 case Intrinsic::x86_sse_ucomieq_ss:
6752 case Intrinsic::x86_sse_ucomilt_ss:
6753 case Intrinsic::x86_sse_ucomile_ss:
6754 case Intrinsic::x86_sse_ucomigt_ss:
6755 case Intrinsic::x86_sse_ucomige_ss:
6756 case Intrinsic::x86_sse_ucomineq_ss:
6757 case Intrinsic::x86_sse2_comieq_sd:
6758 case Intrinsic::x86_sse2_comilt_sd:
6759 case Intrinsic::x86_sse2_comile_sd:
6760 case Intrinsic::x86_sse2_comigt_sd:
6761 case Intrinsic::x86_sse2_comige_sd:
6762 case Intrinsic::x86_sse2_comineq_sd:
6763 case Intrinsic::x86_sse2_ucomieq_sd:
6764 case Intrinsic::x86_sse2_ucomilt_sd:
6765 case Intrinsic::x86_sse2_ucomile_sd:
6766 case Intrinsic::x86_sse2_ucomigt_sd:
6767 case Intrinsic::x86_sse2_ucomige_sd:
6768 case Intrinsic::x86_sse2_ucomineq_sd: {
6770 ISD::CondCode CC = ISD::SETCC_INVALID;
6773 case Intrinsic::x86_sse_comieq_ss:
6774 case Intrinsic::x86_sse2_comieq_sd:
6778 case Intrinsic::x86_sse_comilt_ss:
6779 case Intrinsic::x86_sse2_comilt_sd:
6783 case Intrinsic::x86_sse_comile_ss:
6784 case Intrinsic::x86_sse2_comile_sd:
6788 case Intrinsic::x86_sse_comigt_ss:
6789 case Intrinsic::x86_sse2_comigt_sd:
6793 case Intrinsic::x86_sse_comige_ss:
6794 case Intrinsic::x86_sse2_comige_sd:
6798 case Intrinsic::x86_sse_comineq_ss:
6799 case Intrinsic::x86_sse2_comineq_sd:
6803 case Intrinsic::x86_sse_ucomieq_ss:
6804 case Intrinsic::x86_sse2_ucomieq_sd:
6805 Opc = X86ISD::UCOMI;
6808 case Intrinsic::x86_sse_ucomilt_ss:
6809 case Intrinsic::x86_sse2_ucomilt_sd:
6810 Opc = X86ISD::UCOMI;
6813 case Intrinsic::x86_sse_ucomile_ss:
6814 case Intrinsic::x86_sse2_ucomile_sd:
6815 Opc = X86ISD::UCOMI;
6818 case Intrinsic::x86_sse_ucomigt_ss:
6819 case Intrinsic::x86_sse2_ucomigt_sd:
6820 Opc = X86ISD::UCOMI;
6823 case Intrinsic::x86_sse_ucomige_ss:
6824 case Intrinsic::x86_sse2_ucomige_sd:
6825 Opc = X86ISD::UCOMI;
6828 case Intrinsic::x86_sse_ucomineq_ss:
6829 case Intrinsic::x86_sse2_ucomineq_sd:
6830 Opc = X86ISD::UCOMI;
6835 SDValue LHS = Op.getOperand(1);
6836 SDValue RHS = Op.getOperand(2);
6837 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6838 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6839 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6840 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6841 DAG.getConstant(X86CC, MVT::i8), Cond);
6842 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6844 // ptest intrinsics. The intrinsic these come from are designed to return
6845 // an integer value, not just an instruction so lower it to the ptest
6846 // pattern and a setcc for the result.
6847 case Intrinsic::x86_sse41_ptestz:
6848 case Intrinsic::x86_sse41_ptestc:
6849 case Intrinsic::x86_sse41_ptestnzc:{
6852 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6853 case Intrinsic::x86_sse41_ptestz:
6855 X86CC = X86::COND_E;
6857 case Intrinsic::x86_sse41_ptestc:
6859 X86CC = X86::COND_B;
6861 case Intrinsic::x86_sse41_ptestnzc:
6863 X86CC = X86::COND_A;
6867 SDValue LHS = Op.getOperand(1);
6868 SDValue RHS = Op.getOperand(2);
6869 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6870 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6871 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6872 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6875 // Fix vector shift instructions where the last operand is a non-immediate
6877 case Intrinsic::x86_sse2_pslli_w:
6878 case Intrinsic::x86_sse2_pslli_d:
6879 case Intrinsic::x86_sse2_pslli_q:
6880 case Intrinsic::x86_sse2_psrli_w:
6881 case Intrinsic::x86_sse2_psrli_d:
6882 case Intrinsic::x86_sse2_psrli_q:
6883 case Intrinsic::x86_sse2_psrai_w:
6884 case Intrinsic::x86_sse2_psrai_d:
6885 case Intrinsic::x86_mmx_pslli_w:
6886 case Intrinsic::x86_mmx_pslli_d:
6887 case Intrinsic::x86_mmx_pslli_q:
6888 case Intrinsic::x86_mmx_psrli_w:
6889 case Intrinsic::x86_mmx_psrli_d:
6890 case Intrinsic::x86_mmx_psrli_q:
6891 case Intrinsic::x86_mmx_psrai_w:
6892 case Intrinsic::x86_mmx_psrai_d: {
6893 SDValue ShAmt = Op.getOperand(2);
6894 if (isa<ConstantSDNode>(ShAmt))
6897 unsigned NewIntNo = 0;
6898 EVT ShAmtVT = MVT::v4i32;
6900 case Intrinsic::x86_sse2_pslli_w:
6901 NewIntNo = Intrinsic::x86_sse2_psll_w;
6903 case Intrinsic::x86_sse2_pslli_d:
6904 NewIntNo = Intrinsic::x86_sse2_psll_d;
6906 case Intrinsic::x86_sse2_pslli_q:
6907 NewIntNo = Intrinsic::x86_sse2_psll_q;
6909 case Intrinsic::x86_sse2_psrli_w:
6910 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6912 case Intrinsic::x86_sse2_psrli_d:
6913 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6915 case Intrinsic::x86_sse2_psrli_q:
6916 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6918 case Intrinsic::x86_sse2_psrai_w:
6919 NewIntNo = Intrinsic::x86_sse2_psra_w;
6921 case Intrinsic::x86_sse2_psrai_d:
6922 NewIntNo = Intrinsic::x86_sse2_psra_d;
6925 ShAmtVT = MVT::v2i32;
6927 case Intrinsic::x86_mmx_pslli_w:
6928 NewIntNo = Intrinsic::x86_mmx_psll_w;
6930 case Intrinsic::x86_mmx_pslli_d:
6931 NewIntNo = Intrinsic::x86_mmx_psll_d;
6933 case Intrinsic::x86_mmx_pslli_q:
6934 NewIntNo = Intrinsic::x86_mmx_psll_q;
6936 case Intrinsic::x86_mmx_psrli_w:
6937 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6939 case Intrinsic::x86_mmx_psrli_d:
6940 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6942 case Intrinsic::x86_mmx_psrli_q:
6943 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6945 case Intrinsic::x86_mmx_psrai_w:
6946 NewIntNo = Intrinsic::x86_mmx_psra_w;
6948 case Intrinsic::x86_mmx_psrai_d:
6949 NewIntNo = Intrinsic::x86_mmx_psra_d;
6951 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6957 // The vector shift intrinsics with scalars uses 32b shift amounts but
6958 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
6962 ShOps[1] = DAG.getConstant(0, MVT::i32);
6963 if (ShAmtVT == MVT::v4i32) {
6964 ShOps[2] = DAG.getUNDEF(MVT::i32);
6965 ShOps[3] = DAG.getUNDEF(MVT::i32);
6966 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
6968 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
6971 EVT VT = Op.getValueType();
6972 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
6973 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6974 DAG.getConstant(NewIntNo, MVT::i32),
6975 Op.getOperand(1), ShAmt);
6980 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
6981 SelectionDAG &DAG) const {
6982 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6983 MFI->setReturnAddressIsTaken(true);
6985 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6986 DebugLoc dl = Op.getDebugLoc();
6989 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6991 DAG.getConstant(TD->getPointerSize(),
6992 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6993 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6994 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6996 NULL, 0, false, false, 0);
6999 // Just load the return address.
7000 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
7001 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7002 RetAddrFI, NULL, 0, false, false, 0);
7005 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
7006 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7007 MFI->setFrameAddressIsTaken(true);
7009 EVT VT = Op.getValueType();
7010 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
7011 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7012 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
7013 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
7015 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
7020 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
7021 SelectionDAG &DAG) const {
7022 return DAG.getIntPtrConstant(2*TD->getPointerSize());
7025 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
7026 MachineFunction &MF = DAG.getMachineFunction();
7027 SDValue Chain = Op.getOperand(0);
7028 SDValue Offset = Op.getOperand(1);
7029 SDValue Handler = Op.getOperand(2);
7030 DebugLoc dl = Op.getDebugLoc();
7032 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7034 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7036 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
7037 DAG.getIntPtrConstant(-TD->getPointerSize()));
7038 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7039 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0);
7040 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7041 MF.getRegInfo().addLiveOut(StoreAddrReg);
7043 return DAG.getNode(X86ISD::EH_RETURN, dl,
7045 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7048 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7049 SelectionDAG &DAG) const {
7050 SDValue Root = Op.getOperand(0);
7051 SDValue Trmp = Op.getOperand(1); // trampoline
7052 SDValue FPtr = Op.getOperand(2); // nested function
7053 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7054 DebugLoc dl = Op.getDebugLoc();
7056 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7058 if (Subtarget->is64Bit()) {
7059 SDValue OutChains[6];
7061 // Large code-model.
7062 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
7063 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
7065 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7066 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7068 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7070 // Load the pointer to the nested function into R11.
7071 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7072 SDValue Addr = Trmp;
7073 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7074 Addr, TrmpAddr, 0, false, false, 0);
7076 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7077 DAG.getConstant(2, MVT::i64));
7078 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2,
7081 // Load the 'nest' parameter value into R10.
7082 // R10 is specified in X86CallingConv.td
7083 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
7084 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7085 DAG.getConstant(10, MVT::i64));
7086 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7087 Addr, TrmpAddr, 10, false, false, 0);
7089 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7090 DAG.getConstant(12, MVT::i64));
7091 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12,
7094 // Jump to the nested function.
7095 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
7096 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7097 DAG.getConstant(20, MVT::i64));
7098 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7099 Addr, TrmpAddr, 20, false, false, 0);
7101 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
7102 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7103 DAG.getConstant(22, MVT::i64));
7104 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
7105 TrmpAddr, 22, false, false, 0);
7108 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
7109 return DAG.getMergeValues(Ops, 2, dl);
7111 const Function *Func =
7112 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
7113 CallingConv::ID CC = Func->getCallingConv();
7118 llvm_unreachable("Unsupported calling convention");
7119 case CallingConv::C:
7120 case CallingConv::X86_StdCall: {
7121 // Pass 'nest' parameter in ECX.
7122 // Must be kept in sync with X86CallingConv.td
7125 // Check that ECX wasn't needed by an 'inreg' parameter.
7126 const FunctionType *FTy = Func->getFunctionType();
7127 const AttrListPtr &Attrs = Func->getAttributes();
7129 if (!Attrs.isEmpty() && !Func->isVarArg()) {
7130 unsigned InRegCount = 0;
7133 for (FunctionType::param_iterator I = FTy->param_begin(),
7134 E = FTy->param_end(); I != E; ++I, ++Idx)
7135 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
7136 // FIXME: should only count parameters that are lowered to integers.
7137 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
7139 if (InRegCount > 2) {
7140 report_fatal_error("Nest register in use - reduce number of inreg parameters!");
7145 case CallingConv::X86_FastCall:
7146 case CallingConv::X86_ThisCall:
7147 case CallingConv::Fast:
7148 // Pass 'nest' parameter in EAX.
7149 // Must be kept in sync with X86CallingConv.td
7154 SDValue OutChains[4];
7157 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7158 DAG.getConstant(10, MVT::i32));
7159 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
7161 // This is storing the opcode for MOV32ri.
7162 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
7163 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
7164 OutChains[0] = DAG.getStore(Root, dl,
7165 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
7166 Trmp, TrmpAddr, 0, false, false, 0);
7168 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7169 DAG.getConstant(1, MVT::i32));
7170 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1,
7173 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
7174 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7175 DAG.getConstant(5, MVT::i32));
7176 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
7177 TrmpAddr, 5, false, false, 1);
7179 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7180 DAG.getConstant(6, MVT::i32));
7181 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6,
7185 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
7186 return DAG.getMergeValues(Ops, 2, dl);
7190 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
7191 SelectionDAG &DAG) const {
7193 The rounding mode is in bits 11:10 of FPSR, and has the following
7200 FLT_ROUNDS, on the other hand, expects the following:
7207 To perform the conversion, we do:
7208 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
7211 MachineFunction &MF = DAG.getMachineFunction();
7212 const TargetMachine &TM = MF.getTarget();
7213 const TargetFrameInfo &TFI = *TM.getFrameInfo();
7214 unsigned StackAlignment = TFI.getStackAlignment();
7215 EVT VT = Op.getValueType();
7216 DebugLoc dl = Op.getDebugLoc();
7218 // Save FP Control Word to stack slot
7219 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
7220 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7222 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
7223 DAG.getEntryNode(), StackSlot);
7225 // Load FP Control Word from stack slot
7226 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0,
7229 // Transform as necessary
7231 DAG.getNode(ISD::SRL, dl, MVT::i16,
7232 DAG.getNode(ISD::AND, dl, MVT::i16,
7233 CWD, DAG.getConstant(0x800, MVT::i16)),
7234 DAG.getConstant(11, MVT::i8));
7236 DAG.getNode(ISD::SRL, dl, MVT::i16,
7237 DAG.getNode(ISD::AND, dl, MVT::i16,
7238 CWD, DAG.getConstant(0x400, MVT::i16)),
7239 DAG.getConstant(9, MVT::i8));
7242 DAG.getNode(ISD::AND, dl, MVT::i16,
7243 DAG.getNode(ISD::ADD, dl, MVT::i16,
7244 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
7245 DAG.getConstant(1, MVT::i16)),
7246 DAG.getConstant(3, MVT::i16));
7249 return DAG.getNode((VT.getSizeInBits() < 16 ?
7250 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
7253 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
7254 EVT VT = Op.getValueType();
7256 unsigned NumBits = VT.getSizeInBits();
7257 DebugLoc dl = Op.getDebugLoc();
7259 Op = Op.getOperand(0);
7260 if (VT == MVT::i8) {
7261 // Zero extend to i32 since there is not an i8 bsr.
7263 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7266 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
7267 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7268 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
7270 // If src is zero (i.e. bsr sets ZF), returns NumBits.
7273 DAG.getConstant(NumBits+NumBits-1, OpVT),
7274 DAG.getConstant(X86::COND_E, MVT::i8),
7277 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7279 // Finally xor with NumBits-1.
7280 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
7283 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7287 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
7288 EVT VT = Op.getValueType();
7290 unsigned NumBits = VT.getSizeInBits();
7291 DebugLoc dl = Op.getDebugLoc();
7293 Op = Op.getOperand(0);
7294 if (VT == MVT::i8) {
7296 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7299 // Issue a bsf (scan bits forward) which also sets EFLAGS.
7300 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7301 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7303 // If src is zero (i.e. bsf sets ZF), returns NumBits.
7306 DAG.getConstant(NumBits, OpVT),
7307 DAG.getConstant(X86::COND_E, MVT::i8),
7310 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7313 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7317 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
7318 EVT VT = Op.getValueType();
7319 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7320 DebugLoc dl = Op.getDebugLoc();
7322 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7323 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7324 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7325 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7326 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7328 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7329 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7330 // return AloBlo + AloBhi + AhiBlo;
7332 SDValue A = Op.getOperand(0);
7333 SDValue B = Op.getOperand(1);
7335 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7336 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7337 A, DAG.getConstant(32, MVT::i32));
7338 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7339 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7340 B, DAG.getConstant(32, MVT::i32));
7341 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7342 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7344 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7345 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7347 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7348 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7350 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7351 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7352 AloBhi, DAG.getConstant(32, MVT::i32));
7353 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7354 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7355 AhiBlo, DAG.getConstant(32, MVT::i32));
7356 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7357 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7362 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
7363 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7364 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7365 // looks for this combo and may remove the "setcc" instruction if the "setcc"
7366 // has only one use.
7367 SDNode *N = Op.getNode();
7368 SDValue LHS = N->getOperand(0);
7369 SDValue RHS = N->getOperand(1);
7370 unsigned BaseOp = 0;
7372 DebugLoc dl = Op.getDebugLoc();
7374 switch (Op.getOpcode()) {
7375 default: llvm_unreachable("Unknown ovf instruction!");
7377 // A subtract of one will be selected as a INC. Note that INC doesn't
7378 // set CF, so we can't do this for UADDO.
7379 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7380 if (C->getAPIntValue() == 1) {
7381 BaseOp = X86ISD::INC;
7385 BaseOp = X86ISD::ADD;
7389 BaseOp = X86ISD::ADD;
7393 // A subtract of one will be selected as a DEC. Note that DEC doesn't
7394 // set CF, so we can't do this for USUBO.
7395 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7396 if (C->getAPIntValue() == 1) {
7397 BaseOp = X86ISD::DEC;
7401 BaseOp = X86ISD::SUB;
7405 BaseOp = X86ISD::SUB;
7409 BaseOp = X86ISD::SMUL;
7413 BaseOp = X86ISD::UMUL;
7418 // Also sets EFLAGS.
7419 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7420 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7423 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7424 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7426 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7430 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
7431 EVT T = Op.getValueType();
7432 DebugLoc dl = Op.getDebugLoc();
7435 switch(T.getSimpleVT().SimpleTy) {
7437 assert(false && "Invalid value type!");
7438 case MVT::i8: Reg = X86::AL; size = 1; break;
7439 case MVT::i16: Reg = X86::AX; size = 2; break;
7440 case MVT::i32: Reg = X86::EAX; size = 4; break;
7442 assert(Subtarget->is64Bit() && "Node not type legal!");
7443 Reg = X86::RAX; size = 8;
7446 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7447 Op.getOperand(2), SDValue());
7448 SDValue Ops[] = { cpIn.getValue(0),
7451 DAG.getTargetConstant(size, MVT::i8),
7453 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7454 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7456 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7460 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7461 SelectionDAG &DAG) const {
7462 assert(Subtarget->is64Bit() && "Result not type legalized?");
7463 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7464 SDValue TheChain = Op.getOperand(0);
7465 DebugLoc dl = Op.getDebugLoc();
7466 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7467 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7468 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7470 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7471 DAG.getConstant(32, MVT::i8));
7473 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7476 return DAG.getMergeValues(Ops, 2, dl);
7479 SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op,
7480 SelectionDAG &DAG) const {
7481 EVT SrcVT = Op.getOperand(0).getValueType();
7482 EVT DstVT = Op.getValueType();
7483 assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
7484 Subtarget->hasMMX() && !DisableMMX) &&
7485 "Unexpected custom BIT_CONVERT");
7486 assert((DstVT == MVT::i64 ||
7487 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
7488 "Unexpected custom BIT_CONVERT");
7489 // i64 <=> MMX conversions are Legal.
7490 if (SrcVT==MVT::i64 && DstVT.isVector())
7492 if (DstVT==MVT::i64 && SrcVT.isVector())
7494 // MMX <=> MMX conversions are Legal.
7495 if (SrcVT.isVector() && DstVT.isVector())
7497 // All other conversions need to be expanded.
7500 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
7501 SDNode *Node = Op.getNode();
7502 DebugLoc dl = Node->getDebugLoc();
7503 EVT T = Node->getValueType(0);
7504 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7505 DAG.getConstant(0, T), Node->getOperand(2));
7506 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7507 cast<AtomicSDNode>(Node)->getMemoryVT(),
7508 Node->getOperand(0),
7509 Node->getOperand(1), negOp,
7510 cast<AtomicSDNode>(Node)->getSrcValue(),
7511 cast<AtomicSDNode>(Node)->getAlignment());
7514 /// LowerOperation - Provide custom lowering hooks for some operations.
7516 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7517 switch (Op.getOpcode()) {
7518 default: llvm_unreachable("Should not custom lower this!");
7519 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7520 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7521 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7522 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
7523 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7524 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7525 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7526 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7527 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7528 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7529 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7530 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7531 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7532 case ISD::SHL_PARTS:
7533 case ISD::SRA_PARTS:
7534 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7535 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7536 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7537 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7538 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7539 case ISD::FABS: return LowerFABS(Op, DAG);
7540 case ISD::FNEG: return LowerFNEG(Op, DAG);
7541 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7542 case ISD::SETCC: return LowerSETCC(Op, DAG);
7543 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7544 case ISD::SELECT: return LowerSELECT(Op, DAG);
7545 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7546 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7547 case ISD::VASTART: return LowerVASTART(Op, DAG);
7548 case ISD::VAARG: return LowerVAARG(Op, DAG);
7549 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7550 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7551 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7552 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7553 case ISD::FRAME_TO_ARGS_OFFSET:
7554 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7555 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7556 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7557 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7558 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7559 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7560 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7561 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7567 case ISD::UMULO: return LowerXALUO(Op, DAG);
7568 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7569 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG);
7573 void X86TargetLowering::
7574 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7575 SelectionDAG &DAG, unsigned NewOp) const {
7576 EVT T = Node->getValueType(0);
7577 DebugLoc dl = Node->getDebugLoc();
7578 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7580 SDValue Chain = Node->getOperand(0);
7581 SDValue In1 = Node->getOperand(1);
7582 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7583 Node->getOperand(2), DAG.getIntPtrConstant(0));
7584 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7585 Node->getOperand(2), DAG.getIntPtrConstant(1));
7586 SDValue Ops[] = { Chain, In1, In2L, In2H };
7587 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7589 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7590 cast<MemSDNode>(Node)->getMemOperand());
7591 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7592 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7593 Results.push_back(Result.getValue(2));
7596 /// ReplaceNodeResults - Replace a node with an illegal result type
7597 /// with a new node built out of custom code.
7598 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7599 SmallVectorImpl<SDValue>&Results,
7600 SelectionDAG &DAG) const {
7601 DebugLoc dl = N->getDebugLoc();
7602 switch (N->getOpcode()) {
7604 assert(false && "Do not know how to custom type legalize this operation!");
7606 case ISD::FP_TO_SINT: {
7607 std::pair<SDValue,SDValue> Vals =
7608 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7609 SDValue FIST = Vals.first, StackSlot = Vals.second;
7610 if (FIST.getNode() != 0) {
7611 EVT VT = N->getValueType(0);
7612 // Return a load from the stack slot.
7613 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0,
7618 case ISD::READCYCLECOUNTER: {
7619 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7620 SDValue TheChain = N->getOperand(0);
7621 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7622 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7624 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7626 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7627 SDValue Ops[] = { eax, edx };
7628 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7629 Results.push_back(edx.getValue(1));
7632 case ISD::ATOMIC_CMP_SWAP: {
7633 EVT T = N->getValueType(0);
7634 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7635 SDValue cpInL, cpInH;
7636 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7637 DAG.getConstant(0, MVT::i32));
7638 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7639 DAG.getConstant(1, MVT::i32));
7640 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7641 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7643 SDValue swapInL, swapInH;
7644 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7645 DAG.getConstant(0, MVT::i32));
7646 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7647 DAG.getConstant(1, MVT::i32));
7648 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7650 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7651 swapInL.getValue(1));
7652 SDValue Ops[] = { swapInH.getValue(0),
7654 swapInH.getValue(1) };
7655 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7656 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7657 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7658 MVT::i32, Result.getValue(1));
7659 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7660 MVT::i32, cpOutL.getValue(2));
7661 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7662 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7663 Results.push_back(cpOutH.getValue(1));
7666 case ISD::ATOMIC_LOAD_ADD:
7667 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7669 case ISD::ATOMIC_LOAD_AND:
7670 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7672 case ISD::ATOMIC_LOAD_NAND:
7673 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7675 case ISD::ATOMIC_LOAD_OR:
7676 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7678 case ISD::ATOMIC_LOAD_SUB:
7679 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7681 case ISD::ATOMIC_LOAD_XOR:
7682 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7684 case ISD::ATOMIC_SWAP:
7685 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7690 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7692 default: return NULL;
7693 case X86ISD::BSF: return "X86ISD::BSF";
7694 case X86ISD::BSR: return "X86ISD::BSR";
7695 case X86ISD::SHLD: return "X86ISD::SHLD";
7696 case X86ISD::SHRD: return "X86ISD::SHRD";
7697 case X86ISD::FAND: return "X86ISD::FAND";
7698 case X86ISD::FOR: return "X86ISD::FOR";
7699 case X86ISD::FXOR: return "X86ISD::FXOR";
7700 case X86ISD::FSRL: return "X86ISD::FSRL";
7701 case X86ISD::FILD: return "X86ISD::FILD";
7702 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7703 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7704 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7705 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7706 case X86ISD::FLD: return "X86ISD::FLD";
7707 case X86ISD::FST: return "X86ISD::FST";
7708 case X86ISD::CALL: return "X86ISD::CALL";
7709 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7710 case X86ISD::BT: return "X86ISD::BT";
7711 case X86ISD::CMP: return "X86ISD::CMP";
7712 case X86ISD::COMI: return "X86ISD::COMI";
7713 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7714 case X86ISD::SETCC: return "X86ISD::SETCC";
7715 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
7716 case X86ISD::CMOV: return "X86ISD::CMOV";
7717 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7718 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7719 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7720 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7721 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7722 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7723 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7724 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7725 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7726 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7727 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7728 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7729 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
7730 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7731 case X86ISD::FMAX: return "X86ISD::FMAX";
7732 case X86ISD::FMIN: return "X86ISD::FMIN";
7733 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7734 case X86ISD::FRCP: return "X86ISD::FRCP";
7735 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7736 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7737 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7738 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7739 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7740 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7741 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7742 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7743 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7744 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7745 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7746 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7747 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7748 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7749 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7750 case X86ISD::VSHL: return "X86ISD::VSHL";
7751 case X86ISD::VSRL: return "X86ISD::VSRL";
7752 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7753 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7754 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7755 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7756 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7757 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7758 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7759 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7760 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7761 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7762 case X86ISD::ADD: return "X86ISD::ADD";
7763 case X86ISD::SUB: return "X86ISD::SUB";
7764 case X86ISD::SMUL: return "X86ISD::SMUL";
7765 case X86ISD::UMUL: return "X86ISD::UMUL";
7766 case X86ISD::INC: return "X86ISD::INC";
7767 case X86ISD::DEC: return "X86ISD::DEC";
7768 case X86ISD::OR: return "X86ISD::OR";
7769 case X86ISD::XOR: return "X86ISD::XOR";
7770 case X86ISD::AND: return "X86ISD::AND";
7771 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7772 case X86ISD::PTEST: return "X86ISD::PTEST";
7773 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7774 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA";
7778 // isLegalAddressingMode - Return true if the addressing mode represented
7779 // by AM is legal for this target, for a load/store of the specified type.
7780 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7781 const Type *Ty) const {
7782 // X86 supports extremely general addressing modes.
7783 CodeModel::Model M = getTargetMachine().getCodeModel();
7785 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7786 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7791 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7793 // If a reference to this global requires an extra load, we can't fold it.
7794 if (isGlobalStubReference(GVFlags))
7797 // If BaseGV requires a register for the PIC base, we cannot also have a
7798 // BaseReg specified.
7799 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7802 // If lower 4G is not available, then we must use rip-relative addressing.
7803 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7813 // These scales always work.
7818 // These scales are formed with basereg+scalereg. Only accept if there is
7823 default: // Other stuff never works.
7831 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7832 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
7834 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7835 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7836 if (NumBits1 <= NumBits2)
7841 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7842 if (!VT1.isInteger() || !VT2.isInteger())
7844 unsigned NumBits1 = VT1.getSizeInBits();
7845 unsigned NumBits2 = VT2.getSizeInBits();
7846 if (NumBits1 <= NumBits2)
7851 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7852 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7853 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
7856 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7857 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7858 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7861 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7862 // i16 instructions are longer (0x66 prefix) and potentially slower.
7863 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7866 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7867 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7868 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7869 /// are assumed to be legal.
7871 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7873 // Very little shuffling can be done for 64-bit vectors right now.
7874 if (VT.getSizeInBits() == 64)
7875 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
7877 // FIXME: pshufb, blends, shifts.
7878 return (VT.getVectorNumElements() == 2 ||
7879 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7880 isMOVLMask(M, VT) ||
7881 isSHUFPMask(M, VT) ||
7882 isPSHUFDMask(M, VT) ||
7883 isPSHUFHWMask(M, VT) ||
7884 isPSHUFLWMask(M, VT) ||
7885 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7886 isUNPCKLMask(M, VT) ||
7887 isUNPCKHMask(M, VT) ||
7888 isUNPCKL_v_undef_Mask(M, VT) ||
7889 isUNPCKH_v_undef_Mask(M, VT));
7893 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7895 unsigned NumElts = VT.getVectorNumElements();
7896 // FIXME: This collection of masks seems suspect.
7899 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7900 return (isMOVLMask(Mask, VT) ||
7901 isCommutedMOVLMask(Mask, VT, true) ||
7902 isSHUFPMask(Mask, VT) ||
7903 isCommutedSHUFPMask(Mask, VT));
7908 //===----------------------------------------------------------------------===//
7909 // X86 Scheduler Hooks
7910 //===----------------------------------------------------------------------===//
7912 // private utility function
7914 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7915 MachineBasicBlock *MBB,
7923 TargetRegisterClass *RC,
7924 bool invSrc) const {
7925 // For the atomic bitwise operator, we generate
7928 // ld t1 = [bitinstr.addr]
7929 // op t2 = t1, [bitinstr.val]
7931 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7933 // fallthrough -->nextMBB
7934 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7935 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7936 MachineFunction::iterator MBBIter = MBB;
7939 /// First build the CFG
7940 MachineFunction *F = MBB->getParent();
7941 MachineBasicBlock *thisMBB = MBB;
7942 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7943 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7944 F->insert(MBBIter, newMBB);
7945 F->insert(MBBIter, nextMBB);
7947 // Move all successors to thisMBB to nextMBB
7948 nextMBB->transferSuccessors(thisMBB);
7950 // Update thisMBB to fall through to newMBB
7951 thisMBB->addSuccessor(newMBB);
7953 // newMBB jumps to itself and fall through to nextMBB
7954 newMBB->addSuccessor(nextMBB);
7955 newMBB->addSuccessor(newMBB);
7957 // Insert instructions into newMBB based on incoming instruction
7958 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7959 "unexpected number of operands");
7960 DebugLoc dl = bInstr->getDebugLoc();
7961 MachineOperand& destOper = bInstr->getOperand(0);
7962 MachineOperand* argOpers[2 + X86AddrNumOperands];
7963 int numArgs = bInstr->getNumOperands() - 1;
7964 for (int i=0; i < numArgs; ++i)
7965 argOpers[i] = &bInstr->getOperand(i+1);
7967 // x86 address has 4 operands: base, index, scale, and displacement
7968 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7969 int valArgIndx = lastAddrIndx + 1;
7971 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7972 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7973 for (int i=0; i <= lastAddrIndx; ++i)
7974 (*MIB).addOperand(*argOpers[i]);
7976 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7978 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7983 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7984 assert((argOpers[valArgIndx]->isReg() ||
7985 argOpers[valArgIndx]->isImm()) &&
7987 if (argOpers[valArgIndx]->isReg())
7988 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7990 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7992 (*MIB).addOperand(*argOpers[valArgIndx]);
7994 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7997 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7998 for (int i=0; i <= lastAddrIndx; ++i)
7999 (*MIB).addOperand(*argOpers[i]);
8001 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8002 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8003 bInstr->memoperands_end());
8005 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
8009 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8011 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
8015 // private utility function: 64 bit atomics on 32 bit host.
8017 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
8018 MachineBasicBlock *MBB,
8023 bool invSrc) const {
8024 // For the atomic bitwise operator, we generate
8025 // thisMBB (instructions are in pairs, except cmpxchg8b)
8026 // ld t1,t2 = [bitinstr.addr]
8028 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
8029 // op t5, t6 <- out1, out2, [bitinstr.val]
8030 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
8031 // mov ECX, EBX <- t5, t6
8032 // mov EAX, EDX <- t1, t2
8033 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
8034 // mov t3, t4 <- EAX, EDX
8036 // result in out1, out2
8037 // fallthrough -->nextMBB
8039 const TargetRegisterClass *RC = X86::GR32RegisterClass;
8040 const unsigned LoadOpc = X86::MOV32rm;
8041 const unsigned copyOpc = X86::MOV32rr;
8042 const unsigned NotOpc = X86::NOT32r;
8043 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8044 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8045 MachineFunction::iterator MBBIter = MBB;
8048 /// First build the CFG
8049 MachineFunction *F = MBB->getParent();
8050 MachineBasicBlock *thisMBB = MBB;
8051 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8052 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8053 F->insert(MBBIter, newMBB);
8054 F->insert(MBBIter, nextMBB);
8056 // Move all successors to thisMBB to nextMBB
8057 nextMBB->transferSuccessors(thisMBB);
8059 // Update thisMBB to fall through to newMBB
8060 thisMBB->addSuccessor(newMBB);
8062 // newMBB jumps to itself and fall through to nextMBB
8063 newMBB->addSuccessor(nextMBB);
8064 newMBB->addSuccessor(newMBB);
8066 DebugLoc dl = bInstr->getDebugLoc();
8067 // Insert instructions into newMBB based on incoming instruction
8068 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
8069 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
8070 "unexpected number of operands");
8071 MachineOperand& dest1Oper = bInstr->getOperand(0);
8072 MachineOperand& dest2Oper = bInstr->getOperand(1);
8073 MachineOperand* argOpers[2 + X86AddrNumOperands];
8074 for (int i=0; i < 2 + X86AddrNumOperands; ++i) {
8075 argOpers[i] = &bInstr->getOperand(i+2);
8077 // We use some of the operands multiple times, so conservatively just
8078 // clear any kill flags that might be present.
8079 if (argOpers[i]->isReg() && argOpers[i]->isUse())
8080 argOpers[i]->setIsKill(false);
8083 // x86 address has 5 operands: base, index, scale, displacement, and segment.
8084 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8086 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8087 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
8088 for (int i=0; i <= lastAddrIndx; ++i)
8089 (*MIB).addOperand(*argOpers[i]);
8090 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8091 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
8092 // add 4 to displacement.
8093 for (int i=0; i <= lastAddrIndx-2; ++i)
8094 (*MIB).addOperand(*argOpers[i]);
8095 MachineOperand newOp3 = *(argOpers[3]);
8097 newOp3.setImm(newOp3.getImm()+4);
8099 newOp3.setOffset(newOp3.getOffset()+4);
8100 (*MIB).addOperand(newOp3);
8101 (*MIB).addOperand(*argOpers[lastAddrIndx]);
8103 // t3/4 are defined later, at the bottom of the loop
8104 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
8105 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
8106 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
8107 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
8108 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
8109 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
8111 // The subsequent operations should be using the destination registers of
8112 //the PHI instructions.
8114 t1 = F->getRegInfo().createVirtualRegister(RC);
8115 t2 = F->getRegInfo().createVirtualRegister(RC);
8116 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
8117 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
8119 t1 = dest1Oper.getReg();
8120 t2 = dest2Oper.getReg();
8123 int valArgIndx = lastAddrIndx + 1;
8124 assert((argOpers[valArgIndx]->isReg() ||
8125 argOpers[valArgIndx]->isImm()) &&
8127 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
8128 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
8129 if (argOpers[valArgIndx]->isReg())
8130 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
8132 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
8133 if (regOpcL != X86::MOV32rr)
8135 (*MIB).addOperand(*argOpers[valArgIndx]);
8136 assert(argOpers[valArgIndx + 1]->isReg() ==
8137 argOpers[valArgIndx]->isReg());
8138 assert(argOpers[valArgIndx + 1]->isImm() ==
8139 argOpers[valArgIndx]->isImm());
8140 if (argOpers[valArgIndx + 1]->isReg())
8141 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
8143 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
8144 if (regOpcH != X86::MOV32rr)
8146 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
8148 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
8150 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
8153 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
8155 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
8158 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
8159 for (int i=0; i <= lastAddrIndx; ++i)
8160 (*MIB).addOperand(*argOpers[i]);
8162 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8163 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8164 bInstr->memoperands_end());
8166 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
8167 MIB.addReg(X86::EAX);
8168 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
8169 MIB.addReg(X86::EDX);
8172 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8174 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
8178 // private utility function
8180 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
8181 MachineBasicBlock *MBB,
8182 unsigned cmovOpc) const {
8183 // For the atomic min/max operator, we generate
8186 // ld t1 = [min/max.addr]
8187 // mov t2 = [min/max.val]
8189 // cmov[cond] t2 = t1
8191 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8193 // fallthrough -->nextMBB
8195 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8196 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8197 MachineFunction::iterator MBBIter = MBB;
8200 /// First build the CFG
8201 MachineFunction *F = MBB->getParent();
8202 MachineBasicBlock *thisMBB = MBB;
8203 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8204 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8205 F->insert(MBBIter, newMBB);
8206 F->insert(MBBIter, nextMBB);
8208 // Move all successors of thisMBB to nextMBB
8209 nextMBB->transferSuccessors(thisMBB);
8211 // Update thisMBB to fall through to newMBB
8212 thisMBB->addSuccessor(newMBB);
8214 // newMBB jumps to newMBB and fall through to nextMBB
8215 newMBB->addSuccessor(nextMBB);
8216 newMBB->addSuccessor(newMBB);
8218 DebugLoc dl = mInstr->getDebugLoc();
8219 // Insert instructions into newMBB based on incoming instruction
8220 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
8221 "unexpected number of operands");
8222 MachineOperand& destOper = mInstr->getOperand(0);
8223 MachineOperand* argOpers[2 + X86AddrNumOperands];
8224 int numArgs = mInstr->getNumOperands() - 1;
8225 for (int i=0; i < numArgs; ++i)
8226 argOpers[i] = &mInstr->getOperand(i+1);
8228 // x86 address has 4 operands: base, index, scale, and displacement
8229 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8230 int valArgIndx = lastAddrIndx + 1;
8232 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8233 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
8234 for (int i=0; i <= lastAddrIndx; ++i)
8235 (*MIB).addOperand(*argOpers[i]);
8237 // We only support register and immediate values
8238 assert((argOpers[valArgIndx]->isReg() ||
8239 argOpers[valArgIndx]->isImm()) &&
8242 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8243 if (argOpers[valArgIndx]->isReg())
8244 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8246 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8247 (*MIB).addOperand(*argOpers[valArgIndx]);
8249 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
8252 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
8257 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8258 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
8262 // Cmp and exchange if none has modified the memory location
8263 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
8264 for (int i=0; i <= lastAddrIndx; ++i)
8265 (*MIB).addOperand(*argOpers[i]);
8267 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8268 (*MIB).setMemRefs(mInstr->memoperands_begin(),
8269 mInstr->memoperands_end());
8271 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
8272 MIB.addReg(X86::EAX);
8275 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8277 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
8281 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
8282 // all of this code can be replaced with that in the .td file.
8284 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
8285 unsigned numArgs, bool memArg) const {
8287 MachineFunction *F = BB->getParent();
8288 DebugLoc dl = MI->getDebugLoc();
8289 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8293 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
8295 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
8297 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
8299 for (unsigned i = 0; i < numArgs; ++i) {
8300 MachineOperand &Op = MI->getOperand(i+1);
8302 if (!(Op.isReg() && Op.isImplicit()))
8306 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
8309 F->DeleteMachineInstr(MI);
8315 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
8317 MachineBasicBlock *MBB) const {
8318 // Emit code to save XMM registers to the stack. The ABI says that the
8319 // number of registers to save is given in %al, so it's theoretically
8320 // possible to do an indirect jump trick to avoid saving all of them,
8321 // however this code takes a simpler approach and just executes all
8322 // of the stores if %al is non-zero. It's less code, and it's probably
8323 // easier on the hardware branch predictor, and stores aren't all that
8324 // expensive anyway.
8326 // Create the new basic blocks. One block contains all the XMM stores,
8327 // and one block is the final destination regardless of whether any
8328 // stores were performed.
8329 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8330 MachineFunction *F = MBB->getParent();
8331 MachineFunction::iterator MBBIter = MBB;
8333 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8334 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8335 F->insert(MBBIter, XMMSaveMBB);
8336 F->insert(MBBIter, EndMBB);
8339 // Move any original successors of MBB to the end block.
8340 EndMBB->transferSuccessors(MBB);
8341 // The original block will now fall through to the XMM save block.
8342 MBB->addSuccessor(XMMSaveMBB);
8343 // The XMMSaveMBB will fall through to the end block.
8344 XMMSaveMBB->addSuccessor(EndMBB);
8346 // Now add the instructions.
8347 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8348 DebugLoc DL = MI->getDebugLoc();
8350 unsigned CountReg = MI->getOperand(0).getReg();
8351 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8352 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8354 if (!Subtarget->isTargetWin64()) {
8355 // If %al is 0, branch around the XMM save block.
8356 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8357 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
8358 MBB->addSuccessor(EndMBB);
8361 // In the XMM save block, save all the XMM argument registers.
8362 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8363 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8364 MachineMemOperand *MMO =
8365 F->getMachineMemOperand(
8366 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8367 MachineMemOperand::MOStore, Offset,
8368 /*Size=*/16, /*Align=*/16);
8369 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8370 .addFrameIndex(RegSaveFrameIndex)
8371 .addImm(/*Scale=*/1)
8372 .addReg(/*IndexReg=*/0)
8373 .addImm(/*Disp=*/Offset)
8374 .addReg(/*Segment=*/0)
8375 .addReg(MI->getOperand(i).getReg())
8376 .addMemOperand(MMO);
8379 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8385 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8386 MachineBasicBlock *BB) const {
8387 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8388 DebugLoc DL = MI->getDebugLoc();
8390 // To "insert" a SELECT_CC instruction, we actually have to insert the
8391 // diamond control-flow pattern. The incoming instruction knows the
8392 // destination vreg to set, the condition code register to branch on, the
8393 // true/false values to select between, and a branch opcode to use.
8394 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8395 MachineFunction::iterator It = BB;
8401 // cmpTY ccX, r1, r2
8403 // fallthrough --> copy0MBB
8404 MachineBasicBlock *thisMBB = BB;
8405 MachineFunction *F = BB->getParent();
8406 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8407 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8409 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8410 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8411 F->insert(It, copy0MBB);
8412 F->insert(It, sinkMBB);
8413 // Update machine-CFG edges by first adding all successors of the current
8414 // block to the new block which will contain the Phi node for the select.
8415 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
8416 E = BB->succ_end(); I != E; ++I)
8417 sinkMBB->addSuccessor(*I);
8418 // Next, remove all successors of the current block, and add the true
8419 // and fallthrough blocks as its successors.
8420 while (!BB->succ_empty())
8421 BB->removeSuccessor(BB->succ_begin());
8422 // Add the true and fallthrough blocks as its successors.
8423 BB->addSuccessor(copy0MBB);
8424 BB->addSuccessor(sinkMBB);
8427 // %FalseValue = ...
8428 // # fallthrough to sinkMBB
8429 copy0MBB->addSuccessor(sinkMBB);
8432 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8434 BuildMI(sinkMBB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
8435 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8436 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8438 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8443 X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI,
8444 MachineBasicBlock *BB) const {
8445 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8446 DebugLoc DL = MI->getDebugLoc();
8447 MachineFunction *F = BB->getParent();
8449 // The lowering is pretty easy: we're just emitting the call to _alloca. The
8450 // non-trivial part is impdef of ESP.
8451 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
8454 BuildMI(BB, DL, TII->get(X86::CALLpcrel32))
8455 .addExternalSymbol("_alloca")
8456 .addReg(X86::EAX, RegState::Implicit)
8457 .addReg(X86::ESP, RegState::Implicit)
8458 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
8459 .addReg(X86::ESP, RegState::Define | RegState::Implicit);
8461 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8466 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8467 MachineBasicBlock *BB) const {
8468 switch (MI->getOpcode()) {
8469 default: assert(false && "Unexpected instr type to insert");
8470 case X86::MINGW_ALLOCA:
8471 return EmitLoweredMingwAlloca(MI, BB);
8473 case X86::CMOV_V1I64:
8474 case X86::CMOV_FR32:
8475 case X86::CMOV_FR64:
8476 case X86::CMOV_V4F32:
8477 case X86::CMOV_V2F64:
8478 case X86::CMOV_V2I64:
8479 case X86::CMOV_GR16:
8480 case X86::CMOV_GR32:
8481 case X86::CMOV_RFP32:
8482 case X86::CMOV_RFP64:
8483 case X86::CMOV_RFP80:
8484 return EmitLoweredSelect(MI, BB);
8486 case X86::FP32_TO_INT16_IN_MEM:
8487 case X86::FP32_TO_INT32_IN_MEM:
8488 case X86::FP32_TO_INT64_IN_MEM:
8489 case X86::FP64_TO_INT16_IN_MEM:
8490 case X86::FP64_TO_INT32_IN_MEM:
8491 case X86::FP64_TO_INT64_IN_MEM:
8492 case X86::FP80_TO_INT16_IN_MEM:
8493 case X86::FP80_TO_INT32_IN_MEM:
8494 case X86::FP80_TO_INT64_IN_MEM: {
8495 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8496 DebugLoc DL = MI->getDebugLoc();
8498 // Change the floating point control register to use "round towards zero"
8499 // mode when truncating to an integer value.
8500 MachineFunction *F = BB->getParent();
8501 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8502 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
8504 // Load the old value of the high byte of the control word...
8506 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8507 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
8510 // Set the high part to be round to zero...
8511 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8514 // Reload the modified control word now...
8515 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8517 // Restore the memory image of control word to original value
8518 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8521 // Get the X86 opcode to use.
8523 switch (MI->getOpcode()) {
8524 default: llvm_unreachable("illegal opcode!");
8525 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8526 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8527 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8528 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8529 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8530 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8531 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8532 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8533 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8537 MachineOperand &Op = MI->getOperand(0);
8539 AM.BaseType = X86AddressMode::RegBase;
8540 AM.Base.Reg = Op.getReg();
8542 AM.BaseType = X86AddressMode::FrameIndexBase;
8543 AM.Base.FrameIndex = Op.getIndex();
8545 Op = MI->getOperand(1);
8547 AM.Scale = Op.getImm();
8548 Op = MI->getOperand(2);
8550 AM.IndexReg = Op.getImm();
8551 Op = MI->getOperand(3);
8552 if (Op.isGlobal()) {
8553 AM.GV = Op.getGlobal();
8555 AM.Disp = Op.getImm();
8557 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
8558 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
8560 // Reload the original control word now.
8561 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8563 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8566 // String/text processing lowering.
8567 case X86::PCMPISTRM128REG:
8568 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8569 case X86::PCMPISTRM128MEM:
8570 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8571 case X86::PCMPESTRM128REG:
8572 return EmitPCMP(MI, BB, 5, false /* in mem */);
8573 case X86::PCMPESTRM128MEM:
8574 return EmitPCMP(MI, BB, 5, true /* in mem */);
8577 case X86::ATOMAND32:
8578 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8579 X86::AND32ri, X86::MOV32rm,
8580 X86::LCMPXCHG32, X86::MOV32rr,
8581 X86::NOT32r, X86::EAX,
8582 X86::GR32RegisterClass);
8584 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8585 X86::OR32ri, X86::MOV32rm,
8586 X86::LCMPXCHG32, X86::MOV32rr,
8587 X86::NOT32r, X86::EAX,
8588 X86::GR32RegisterClass);
8589 case X86::ATOMXOR32:
8590 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8591 X86::XOR32ri, X86::MOV32rm,
8592 X86::LCMPXCHG32, X86::MOV32rr,
8593 X86::NOT32r, X86::EAX,
8594 X86::GR32RegisterClass);
8595 case X86::ATOMNAND32:
8596 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8597 X86::AND32ri, X86::MOV32rm,
8598 X86::LCMPXCHG32, X86::MOV32rr,
8599 X86::NOT32r, X86::EAX,
8600 X86::GR32RegisterClass, true);
8601 case X86::ATOMMIN32:
8602 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8603 case X86::ATOMMAX32:
8604 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8605 case X86::ATOMUMIN32:
8606 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8607 case X86::ATOMUMAX32:
8608 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8610 case X86::ATOMAND16:
8611 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8612 X86::AND16ri, X86::MOV16rm,
8613 X86::LCMPXCHG16, X86::MOV16rr,
8614 X86::NOT16r, X86::AX,
8615 X86::GR16RegisterClass);
8617 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8618 X86::OR16ri, X86::MOV16rm,
8619 X86::LCMPXCHG16, X86::MOV16rr,
8620 X86::NOT16r, X86::AX,
8621 X86::GR16RegisterClass);
8622 case X86::ATOMXOR16:
8623 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8624 X86::XOR16ri, X86::MOV16rm,
8625 X86::LCMPXCHG16, X86::MOV16rr,
8626 X86::NOT16r, X86::AX,
8627 X86::GR16RegisterClass);
8628 case X86::ATOMNAND16:
8629 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8630 X86::AND16ri, X86::MOV16rm,
8631 X86::LCMPXCHG16, X86::MOV16rr,
8632 X86::NOT16r, X86::AX,
8633 X86::GR16RegisterClass, true);
8634 case X86::ATOMMIN16:
8635 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8636 case X86::ATOMMAX16:
8637 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8638 case X86::ATOMUMIN16:
8639 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8640 case X86::ATOMUMAX16:
8641 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8644 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8645 X86::AND8ri, X86::MOV8rm,
8646 X86::LCMPXCHG8, X86::MOV8rr,
8647 X86::NOT8r, X86::AL,
8648 X86::GR8RegisterClass);
8650 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8651 X86::OR8ri, X86::MOV8rm,
8652 X86::LCMPXCHG8, X86::MOV8rr,
8653 X86::NOT8r, X86::AL,
8654 X86::GR8RegisterClass);
8656 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8657 X86::XOR8ri, X86::MOV8rm,
8658 X86::LCMPXCHG8, X86::MOV8rr,
8659 X86::NOT8r, X86::AL,
8660 X86::GR8RegisterClass);
8661 case X86::ATOMNAND8:
8662 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8663 X86::AND8ri, X86::MOV8rm,
8664 X86::LCMPXCHG8, X86::MOV8rr,
8665 X86::NOT8r, X86::AL,
8666 X86::GR8RegisterClass, true);
8667 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8668 // This group is for 64-bit host.
8669 case X86::ATOMAND64:
8670 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8671 X86::AND64ri32, X86::MOV64rm,
8672 X86::LCMPXCHG64, X86::MOV64rr,
8673 X86::NOT64r, X86::RAX,
8674 X86::GR64RegisterClass);
8676 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8677 X86::OR64ri32, X86::MOV64rm,
8678 X86::LCMPXCHG64, X86::MOV64rr,
8679 X86::NOT64r, X86::RAX,
8680 X86::GR64RegisterClass);
8681 case X86::ATOMXOR64:
8682 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8683 X86::XOR64ri32, X86::MOV64rm,
8684 X86::LCMPXCHG64, X86::MOV64rr,
8685 X86::NOT64r, X86::RAX,
8686 X86::GR64RegisterClass);
8687 case X86::ATOMNAND64:
8688 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8689 X86::AND64ri32, X86::MOV64rm,
8690 X86::LCMPXCHG64, X86::MOV64rr,
8691 X86::NOT64r, X86::RAX,
8692 X86::GR64RegisterClass, true);
8693 case X86::ATOMMIN64:
8694 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8695 case X86::ATOMMAX64:
8696 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8697 case X86::ATOMUMIN64:
8698 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8699 case X86::ATOMUMAX64:
8700 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8702 // This group does 64-bit operations on a 32-bit host.
8703 case X86::ATOMAND6432:
8704 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8705 X86::AND32rr, X86::AND32rr,
8706 X86::AND32ri, X86::AND32ri,
8708 case X86::ATOMOR6432:
8709 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8710 X86::OR32rr, X86::OR32rr,
8711 X86::OR32ri, X86::OR32ri,
8713 case X86::ATOMXOR6432:
8714 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8715 X86::XOR32rr, X86::XOR32rr,
8716 X86::XOR32ri, X86::XOR32ri,
8718 case X86::ATOMNAND6432:
8719 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8720 X86::AND32rr, X86::AND32rr,
8721 X86::AND32ri, X86::AND32ri,
8723 case X86::ATOMADD6432:
8724 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8725 X86::ADD32rr, X86::ADC32rr,
8726 X86::ADD32ri, X86::ADC32ri,
8728 case X86::ATOMSUB6432:
8729 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8730 X86::SUB32rr, X86::SBB32rr,
8731 X86::SUB32ri, X86::SBB32ri,
8733 case X86::ATOMSWAP6432:
8734 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8735 X86::MOV32rr, X86::MOV32rr,
8736 X86::MOV32ri, X86::MOV32ri,
8738 case X86::VASTART_SAVE_XMM_REGS:
8739 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8743 //===----------------------------------------------------------------------===//
8744 // X86 Optimization Hooks
8745 //===----------------------------------------------------------------------===//
8747 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8751 const SelectionDAG &DAG,
8752 unsigned Depth) const {
8753 unsigned Opc = Op.getOpcode();
8754 assert((Opc >= ISD::BUILTIN_OP_END ||
8755 Opc == ISD::INTRINSIC_WO_CHAIN ||
8756 Opc == ISD::INTRINSIC_W_CHAIN ||
8757 Opc == ISD::INTRINSIC_VOID) &&
8758 "Should use MaskedValueIsZero if you don't know whether Op"
8759 " is a target node!");
8761 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8773 // These nodes' second result is a boolean.
8774 if (Op.getResNo() == 0)
8778 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8779 Mask.getBitWidth() - 1);
8784 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8785 /// node is a GlobalAddress + offset.
8786 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8787 const GlobalValue* &GA,
8788 int64_t &Offset) const {
8789 if (N->getOpcode() == X86ISD::Wrapper) {
8790 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8791 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8792 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8796 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8799 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8800 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8801 /// if the load addresses are consecutive, non-overlapping, and in the right
8803 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8804 const TargetLowering &TLI) {
8805 DebugLoc dl = N->getDebugLoc();
8806 EVT VT = N->getValueType(0);
8807 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8809 if (VT.getSizeInBits() != 128)
8812 SmallVector<SDValue, 16> Elts;
8813 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
8814 Elts.push_back(DAG.getShuffleScalarElt(SVN, i));
8816 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
8819 /// PerformShuffleCombine - Detect vector gather/scatter index generation
8820 /// and convert it from being a bunch of shuffles and extracts to a simple
8821 /// store and scalar loads to extract the elements.
8822 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
8823 const TargetLowering &TLI) {
8824 SDValue InputVector = N->getOperand(0);
8826 // Only operate on vectors of 4 elements, where the alternative shuffling
8827 // gets to be more expensive.
8828 if (InputVector.getValueType() != MVT::v4i32)
8831 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
8832 // single use which is a sign-extend or zero-extend, and all elements are
8834 SmallVector<SDNode *, 4> Uses;
8835 unsigned ExtractedElements = 0;
8836 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
8837 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
8838 if (UI.getUse().getResNo() != InputVector.getResNo())
8841 SDNode *Extract = *UI;
8842 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8845 if (Extract->getValueType(0) != MVT::i32)
8847 if (!Extract->hasOneUse())
8849 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
8850 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
8852 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
8855 // Record which element was extracted.
8856 ExtractedElements |=
8857 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
8859 Uses.push_back(Extract);
8862 // If not all the elements were used, this may not be worthwhile.
8863 if (ExtractedElements != 15)
8866 // Ok, we've now decided to do the transformation.
8867 DebugLoc dl = InputVector.getDebugLoc();
8869 // Store the value to a temporary stack slot.
8870 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
8871 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL, 0,
8874 // Replace each use (extract) with a load of the appropriate element.
8875 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
8876 UE = Uses.end(); UI != UE; ++UI) {
8877 SDNode *Extract = *UI;
8879 // Compute the element's address.
8880 SDValue Idx = Extract->getOperand(1);
8882 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
8883 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
8884 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
8886 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), OffsetVal, StackPtr);
8889 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, ScalarAddr,
8890 NULL, 0, false, false, 0);
8892 // Replace the exact with the load.
8893 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
8896 // The replacement was made in place; don't return anything.
8900 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8901 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8902 const X86Subtarget *Subtarget) {
8903 DebugLoc DL = N->getDebugLoc();
8904 SDValue Cond = N->getOperand(0);
8905 // Get the LHS/RHS of the select.
8906 SDValue LHS = N->getOperand(1);
8907 SDValue RHS = N->getOperand(2);
8909 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
8910 // instructions match the semantics of the common C idiom x<y?x:y but not
8911 // x<=y?x:y, because of how they handle negative zero (which can be
8912 // ignored in unsafe-math mode).
8913 if (Subtarget->hasSSE2() &&
8914 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8915 Cond.getOpcode() == ISD::SETCC) {
8916 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8918 unsigned Opcode = 0;
8919 // Check for x CC y ? x : y.
8920 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
8921 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
8925 // Converting this to a min would handle NaNs incorrectly, and swapping
8926 // the operands would cause it to handle comparisons between positive
8927 // and negative zero incorrectly.
8928 if (!FiniteOnlyFPMath() &&
8929 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
8930 if (!UnsafeFPMath &&
8931 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
8933 std::swap(LHS, RHS);
8935 Opcode = X86ISD::FMIN;
8938 // Converting this to a min would handle comparisons between positive
8939 // and negative zero incorrectly.
8940 if (!UnsafeFPMath &&
8941 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
8943 Opcode = X86ISD::FMIN;
8946 // Converting this to a min would handle both negative zeros and NaNs
8947 // incorrectly, but we can swap the operands to fix both.
8948 std::swap(LHS, RHS);
8952 Opcode = X86ISD::FMIN;
8956 // Converting this to a max would handle comparisons between positive
8957 // and negative zero incorrectly.
8958 if (!UnsafeFPMath &&
8959 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
8961 Opcode = X86ISD::FMAX;
8964 // Converting this to a max would handle NaNs incorrectly, and swapping
8965 // the operands would cause it to handle comparisons between positive
8966 // and negative zero incorrectly.
8967 if (!FiniteOnlyFPMath() &&
8968 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
8969 if (!UnsafeFPMath &&
8970 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
8972 std::swap(LHS, RHS);
8974 Opcode = X86ISD::FMAX;
8977 // Converting this to a max would handle both negative zeros and NaNs
8978 // incorrectly, but we can swap the operands to fix both.
8979 std::swap(LHS, RHS);
8983 Opcode = X86ISD::FMAX;
8986 // Check for x CC y ? y : x -- a min/max with reversed arms.
8987 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
8988 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
8992 // Converting this to a min would handle comparisons between positive
8993 // and negative zero incorrectly, and swapping the operands would
8994 // cause it to handle NaNs incorrectly.
8995 if (!UnsafeFPMath &&
8996 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
8997 if (!FiniteOnlyFPMath() &&
8998 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9000 std::swap(LHS, RHS);
9002 Opcode = X86ISD::FMIN;
9005 // Converting this to a min would handle NaNs incorrectly.
9006 if (!UnsafeFPMath &&
9007 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9009 Opcode = X86ISD::FMIN;
9012 // Converting this to a min would handle both negative zeros and NaNs
9013 // incorrectly, but we can swap the operands to fix both.
9014 std::swap(LHS, RHS);
9018 Opcode = X86ISD::FMIN;
9022 // Converting this to a max would handle NaNs incorrectly.
9023 if (!FiniteOnlyFPMath() &&
9024 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9026 Opcode = X86ISD::FMAX;
9029 // Converting this to a max would handle comparisons between positive
9030 // and negative zero incorrectly, and swapping the operands would
9031 // cause it to handle NaNs incorrectly.
9032 if (!UnsafeFPMath &&
9033 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
9034 if (!FiniteOnlyFPMath() &&
9035 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9037 std::swap(LHS, RHS);
9039 Opcode = X86ISD::FMAX;
9042 // Converting this to a max would handle both negative zeros and NaNs
9043 // incorrectly, but we can swap the operands to fix both.
9044 std::swap(LHS, RHS);
9048 Opcode = X86ISD::FMAX;
9054 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
9057 // If this is a select between two integer constants, try to do some
9059 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
9060 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
9061 // Don't do this for crazy integer types.
9062 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
9063 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
9064 // so that TrueC (the true value) is larger than FalseC.
9065 bool NeedsCondInvert = false;
9067 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
9068 // Efficiently invertible.
9069 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
9070 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
9071 isa<ConstantSDNode>(Cond.getOperand(1))))) {
9072 NeedsCondInvert = true;
9073 std::swap(TrueC, FalseC);
9076 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
9077 if (FalseC->getAPIntValue() == 0 &&
9078 TrueC->getAPIntValue().isPowerOf2()) {
9079 if (NeedsCondInvert) // Invert the condition if needed.
9080 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9081 DAG.getConstant(1, Cond.getValueType()));
9083 // Zero extend the condition if needed.
9084 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
9086 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9087 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
9088 DAG.getConstant(ShAmt, MVT::i8));
9091 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
9092 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9093 if (NeedsCondInvert) // Invert the condition if needed.
9094 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9095 DAG.getConstant(1, Cond.getValueType()));
9097 // Zero extend the condition if needed.
9098 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9099 FalseC->getValueType(0), Cond);
9100 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9101 SDValue(FalseC, 0));
9104 // Optimize cases that will turn into an LEA instruction. This requires
9105 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9106 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9107 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9108 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9110 bool isFastMultiplier = false;
9112 switch ((unsigned char)Diff) {
9114 case 1: // result = add base, cond
9115 case 2: // result = lea base( , cond*2)
9116 case 3: // result = lea base(cond, cond*2)
9117 case 4: // result = lea base( , cond*4)
9118 case 5: // result = lea base(cond, cond*4)
9119 case 8: // result = lea base( , cond*8)
9120 case 9: // result = lea base(cond, cond*8)
9121 isFastMultiplier = true;
9126 if (isFastMultiplier) {
9127 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9128 if (NeedsCondInvert) // Invert the condition if needed.
9129 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9130 DAG.getConstant(1, Cond.getValueType()));
9132 // Zero extend the condition if needed.
9133 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9135 // Scale the condition by the difference.
9137 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9138 DAG.getConstant(Diff, Cond.getValueType()));
9140 // Add the base if non-zero.
9141 if (FalseC->getAPIntValue() != 0)
9142 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9143 SDValue(FalseC, 0));
9153 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
9154 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
9155 TargetLowering::DAGCombinerInfo &DCI) {
9156 DebugLoc DL = N->getDebugLoc();
9158 // If the flag operand isn't dead, don't touch this CMOV.
9159 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
9162 // If this is a select between two integer constants, try to do some
9163 // optimizations. Note that the operands are ordered the opposite of SELECT
9165 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
9166 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9167 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
9168 // larger than FalseC (the false value).
9169 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
9171 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
9172 CC = X86::GetOppositeBranchCondition(CC);
9173 std::swap(TrueC, FalseC);
9176 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
9177 // This is efficient for any integer data type (including i8/i16) and
9179 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
9180 SDValue Cond = N->getOperand(3);
9181 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9182 DAG.getConstant(CC, MVT::i8), Cond);
9184 // Zero extend the condition if needed.
9185 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
9187 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9188 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
9189 DAG.getConstant(ShAmt, MVT::i8));
9190 if (N->getNumValues() == 2) // Dead flag value?
9191 return DCI.CombineTo(N, Cond, SDValue());
9195 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
9196 // for any integer data type, including i8/i16.
9197 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9198 SDValue Cond = N->getOperand(3);
9199 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9200 DAG.getConstant(CC, MVT::i8), Cond);
9202 // Zero extend the condition if needed.
9203 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9204 FalseC->getValueType(0), Cond);
9205 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9206 SDValue(FalseC, 0));
9208 if (N->getNumValues() == 2) // Dead flag value?
9209 return DCI.CombineTo(N, Cond, SDValue());
9213 // Optimize cases that will turn into an LEA instruction. This requires
9214 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9215 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9216 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9217 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9219 bool isFastMultiplier = false;
9221 switch ((unsigned char)Diff) {
9223 case 1: // result = add base, cond
9224 case 2: // result = lea base( , cond*2)
9225 case 3: // result = lea base(cond, cond*2)
9226 case 4: // result = lea base( , cond*4)
9227 case 5: // result = lea base(cond, cond*4)
9228 case 8: // result = lea base( , cond*8)
9229 case 9: // result = lea base(cond, cond*8)
9230 isFastMultiplier = true;
9235 if (isFastMultiplier) {
9236 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9237 SDValue Cond = N->getOperand(3);
9238 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9239 DAG.getConstant(CC, MVT::i8), Cond);
9240 // Zero extend the condition if needed.
9241 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9243 // Scale the condition by the difference.
9245 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9246 DAG.getConstant(Diff, Cond.getValueType()));
9248 // Add the base if non-zero.
9249 if (FalseC->getAPIntValue() != 0)
9250 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9251 SDValue(FalseC, 0));
9252 if (N->getNumValues() == 2) // Dead flag value?
9253 return DCI.CombineTo(N, Cond, SDValue());
9263 /// PerformMulCombine - Optimize a single multiply with constant into two
9264 /// in order to implement it with two cheaper instructions, e.g.
9265 /// LEA + SHL, LEA + LEA.
9266 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
9267 TargetLowering::DAGCombinerInfo &DCI) {
9268 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9271 EVT VT = N->getValueType(0);
9275 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
9278 uint64_t MulAmt = C->getZExtValue();
9279 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
9282 uint64_t MulAmt1 = 0;
9283 uint64_t MulAmt2 = 0;
9284 if ((MulAmt % 9) == 0) {
9286 MulAmt2 = MulAmt / 9;
9287 } else if ((MulAmt % 5) == 0) {
9289 MulAmt2 = MulAmt / 5;
9290 } else if ((MulAmt % 3) == 0) {
9292 MulAmt2 = MulAmt / 3;
9295 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
9296 DebugLoc DL = N->getDebugLoc();
9298 if (isPowerOf2_64(MulAmt2) &&
9299 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
9300 // If second multiplifer is pow2, issue it first. We want the multiply by
9301 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
9303 std::swap(MulAmt1, MulAmt2);
9306 if (isPowerOf2_64(MulAmt1))
9307 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
9308 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
9310 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
9311 DAG.getConstant(MulAmt1, VT));
9313 if (isPowerOf2_64(MulAmt2))
9314 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
9315 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
9317 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
9318 DAG.getConstant(MulAmt2, VT));
9320 // Do not add new nodes to DAG combiner worklist.
9321 DCI.CombineTo(N, NewMul, false);
9326 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
9327 SDValue N0 = N->getOperand(0);
9328 SDValue N1 = N->getOperand(1);
9329 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
9330 EVT VT = N0.getValueType();
9332 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
9333 // since the result of setcc_c is all zero's or all ones.
9334 if (N1C && N0.getOpcode() == ISD::AND &&
9335 N0.getOperand(1).getOpcode() == ISD::Constant) {
9336 SDValue N00 = N0.getOperand(0);
9337 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
9338 ((N00.getOpcode() == ISD::ANY_EXTEND ||
9339 N00.getOpcode() == ISD::ZERO_EXTEND) &&
9340 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
9341 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
9342 APInt ShAmt = N1C->getAPIntValue();
9343 Mask = Mask.shl(ShAmt);
9345 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9346 N00, DAG.getConstant(Mask, VT));
9353 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9355 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9356 const X86Subtarget *Subtarget) {
9357 EVT VT = N->getValueType(0);
9358 if (!VT.isVector() && VT.isInteger() &&
9359 N->getOpcode() == ISD::SHL)
9360 return PerformSHLCombine(N, DAG);
9362 // On X86 with SSE2 support, we can transform this to a vector shift if
9363 // all elements are shifted by the same amount. We can't do this in legalize
9364 // because the a constant vector is typically transformed to a constant pool
9365 // so we have no knowledge of the shift amount.
9366 if (!Subtarget->hasSSE2())
9369 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9372 SDValue ShAmtOp = N->getOperand(1);
9373 EVT EltVT = VT.getVectorElementType();
9374 DebugLoc DL = N->getDebugLoc();
9375 SDValue BaseShAmt = SDValue();
9376 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9377 unsigned NumElts = VT.getVectorNumElements();
9379 for (; i != NumElts; ++i) {
9380 SDValue Arg = ShAmtOp.getOperand(i);
9381 if (Arg.getOpcode() == ISD::UNDEF) continue;
9385 for (; i != NumElts; ++i) {
9386 SDValue Arg = ShAmtOp.getOperand(i);
9387 if (Arg.getOpcode() == ISD::UNDEF) continue;
9388 if (Arg != BaseShAmt) {
9392 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9393 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9394 SDValue InVec = ShAmtOp.getOperand(0);
9395 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9396 unsigned NumElts = InVec.getValueType().getVectorNumElements();
9398 for (; i != NumElts; ++i) {
9399 SDValue Arg = InVec.getOperand(i);
9400 if (Arg.getOpcode() == ISD::UNDEF) continue;
9404 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9405 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9406 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9407 if (C->getZExtValue() == SplatIdx)
9408 BaseShAmt = InVec.getOperand(1);
9411 if (BaseShAmt.getNode() == 0)
9412 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9413 DAG.getIntPtrConstant(0));
9417 // The shift amount is an i32.
9418 if (EltVT.bitsGT(MVT::i32))
9419 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9420 else if (EltVT.bitsLT(MVT::i32))
9421 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9423 // The shift amount is identical so we can do a vector shift.
9424 SDValue ValOp = N->getOperand(0);
9425 switch (N->getOpcode()) {
9427 llvm_unreachable("Unknown shift opcode!");
9430 if (VT == MVT::v2i64)
9431 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9432 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9434 if (VT == MVT::v4i32)
9435 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9436 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9438 if (VT == MVT::v8i16)
9439 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9440 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9444 if (VT == MVT::v4i32)
9445 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9446 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9448 if (VT == MVT::v8i16)
9449 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9450 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9454 if (VT == MVT::v2i64)
9455 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9456 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9458 if (VT == MVT::v4i32)
9459 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9460 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9462 if (VT == MVT::v8i16)
9463 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9464 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9471 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
9472 TargetLowering::DAGCombinerInfo &DCI,
9473 const X86Subtarget *Subtarget) {
9474 if (DCI.isBeforeLegalizeOps())
9477 EVT VT = N->getValueType(0);
9478 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
9481 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
9482 SDValue N0 = N->getOperand(0);
9483 SDValue N1 = N->getOperand(1);
9484 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
9486 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
9488 if (!N0.hasOneUse() || !N1.hasOneUse())
9491 SDValue ShAmt0 = N0.getOperand(1);
9492 if (ShAmt0.getValueType() != MVT::i8)
9494 SDValue ShAmt1 = N1.getOperand(1);
9495 if (ShAmt1.getValueType() != MVT::i8)
9497 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
9498 ShAmt0 = ShAmt0.getOperand(0);
9499 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
9500 ShAmt1 = ShAmt1.getOperand(0);
9502 DebugLoc DL = N->getDebugLoc();
9503 unsigned Opc = X86ISD::SHLD;
9504 SDValue Op0 = N0.getOperand(0);
9505 SDValue Op1 = N1.getOperand(0);
9506 if (ShAmt0.getOpcode() == ISD::SUB) {
9508 std::swap(Op0, Op1);
9509 std::swap(ShAmt0, ShAmt1);
9512 unsigned Bits = VT.getSizeInBits();
9513 if (ShAmt1.getOpcode() == ISD::SUB) {
9514 SDValue Sum = ShAmt1.getOperand(0);
9515 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
9516 if (SumC->getSExtValue() == Bits &&
9517 ShAmt1.getOperand(1) == ShAmt0)
9518 return DAG.getNode(Opc, DL, VT,
9520 DAG.getNode(ISD::TRUNCATE, DL,
9523 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
9524 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
9526 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
9527 return DAG.getNode(Opc, DL, VT,
9528 N0.getOperand(0), N1.getOperand(0),
9529 DAG.getNode(ISD::TRUNCATE, DL,
9536 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9537 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9538 const X86Subtarget *Subtarget) {
9539 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
9540 // the FP state in cases where an emms may be missing.
9541 // A preferable solution to the general problem is to figure out the right
9542 // places to insert EMMS. This qualifies as a quick hack.
9544 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9545 StoreSDNode *St = cast<StoreSDNode>(N);
9546 EVT VT = St->getValue().getValueType();
9547 if (VT.getSizeInBits() != 64)
9550 const Function *F = DAG.getMachineFunction().getFunction();
9551 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9552 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9553 && Subtarget->hasSSE2();
9554 if ((VT.isVector() ||
9555 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9556 isa<LoadSDNode>(St->getValue()) &&
9557 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9558 St->getChain().hasOneUse() && !St->isVolatile()) {
9559 SDNode* LdVal = St->getValue().getNode();
9561 int TokenFactorIndex = -1;
9562 SmallVector<SDValue, 8> Ops;
9563 SDNode* ChainVal = St->getChain().getNode();
9564 // Must be a store of a load. We currently handle two cases: the load
9565 // is a direct child, and it's under an intervening TokenFactor. It is
9566 // possible to dig deeper under nested TokenFactors.
9567 if (ChainVal == LdVal)
9568 Ld = cast<LoadSDNode>(St->getChain());
9569 else if (St->getValue().hasOneUse() &&
9570 ChainVal->getOpcode() == ISD::TokenFactor) {
9571 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9572 if (ChainVal->getOperand(i).getNode() == LdVal) {
9573 TokenFactorIndex = i;
9574 Ld = cast<LoadSDNode>(St->getValue());
9576 Ops.push_back(ChainVal->getOperand(i));
9580 if (!Ld || !ISD::isNormalLoad(Ld))
9583 // If this is not the MMX case, i.e. we are just turning i64 load/store
9584 // into f64 load/store, avoid the transformation if there are multiple
9585 // uses of the loaded value.
9586 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9589 DebugLoc LdDL = Ld->getDebugLoc();
9590 DebugLoc StDL = N->getDebugLoc();
9591 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9592 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9594 if (Subtarget->is64Bit() || F64IsLegal) {
9595 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9596 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9597 Ld->getBasePtr(), Ld->getSrcValue(),
9598 Ld->getSrcValueOffset(), Ld->isVolatile(),
9599 Ld->isNonTemporal(), Ld->getAlignment());
9600 SDValue NewChain = NewLd.getValue(1);
9601 if (TokenFactorIndex != -1) {
9602 Ops.push_back(NewChain);
9603 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9606 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9607 St->getSrcValue(), St->getSrcValueOffset(),
9608 St->isVolatile(), St->isNonTemporal(),
9609 St->getAlignment());
9612 // Otherwise, lower to two pairs of 32-bit loads / stores.
9613 SDValue LoAddr = Ld->getBasePtr();
9614 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9615 DAG.getConstant(4, MVT::i32));
9617 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9618 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9619 Ld->isVolatile(), Ld->isNonTemporal(),
9620 Ld->getAlignment());
9621 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9622 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9623 Ld->isVolatile(), Ld->isNonTemporal(),
9624 MinAlign(Ld->getAlignment(), 4));
9626 SDValue NewChain = LoLd.getValue(1);
9627 if (TokenFactorIndex != -1) {
9628 Ops.push_back(LoLd);
9629 Ops.push_back(HiLd);
9630 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9634 LoAddr = St->getBasePtr();
9635 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9636 DAG.getConstant(4, MVT::i32));
9638 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9639 St->getSrcValue(), St->getSrcValueOffset(),
9640 St->isVolatile(), St->isNonTemporal(),
9641 St->getAlignment());
9642 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9644 St->getSrcValueOffset() + 4,
9646 St->isNonTemporal(),
9647 MinAlign(St->getAlignment(), 4));
9648 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9653 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9654 /// X86ISD::FXOR nodes.
9655 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9656 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9657 // F[X]OR(0.0, x) -> x
9658 // F[X]OR(x, 0.0) -> x
9659 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9660 if (C->getValueAPF().isPosZero())
9661 return N->getOperand(1);
9662 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9663 if (C->getValueAPF().isPosZero())
9664 return N->getOperand(0);
9668 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9669 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9670 // FAND(0.0, x) -> 0.0
9671 // FAND(x, 0.0) -> 0.0
9672 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9673 if (C->getValueAPF().isPosZero())
9674 return N->getOperand(0);
9675 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9676 if (C->getValueAPF().isPosZero())
9677 return N->getOperand(1);
9681 static SDValue PerformBTCombine(SDNode *N,
9683 TargetLowering::DAGCombinerInfo &DCI) {
9684 // BT ignores high bits in the bit index operand.
9685 SDValue Op1 = N->getOperand(1);
9686 if (Op1.hasOneUse()) {
9687 unsigned BitWidth = Op1.getValueSizeInBits();
9688 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9689 APInt KnownZero, KnownOne;
9690 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
9691 !DCI.isBeforeLegalizeOps());
9692 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9693 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9694 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9695 DCI.CommitTargetLoweringOpt(TLO);
9700 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9701 SDValue Op = N->getOperand(0);
9702 if (Op.getOpcode() == ISD::BIT_CONVERT)
9703 Op = Op.getOperand(0);
9704 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9705 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9706 VT.getVectorElementType().getSizeInBits() ==
9707 OpVT.getVectorElementType().getSizeInBits()) {
9708 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9713 // On X86 and X86-64, atomic operations are lowered to locked instructions.
9714 // Locked instructions, in turn, have implicit fence semantics (all memory
9715 // operations are flushed before issuing the locked instruction, and the
9716 // are not buffered), so we can fold away the common pattern of
9717 // fence-atomic-fence.
9718 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
9719 SDValue atomic = N->getOperand(0);
9720 switch (atomic.getOpcode()) {
9721 case ISD::ATOMIC_CMP_SWAP:
9722 case ISD::ATOMIC_SWAP:
9723 case ISD::ATOMIC_LOAD_ADD:
9724 case ISD::ATOMIC_LOAD_SUB:
9725 case ISD::ATOMIC_LOAD_AND:
9726 case ISD::ATOMIC_LOAD_OR:
9727 case ISD::ATOMIC_LOAD_XOR:
9728 case ISD::ATOMIC_LOAD_NAND:
9729 case ISD::ATOMIC_LOAD_MIN:
9730 case ISD::ATOMIC_LOAD_MAX:
9731 case ISD::ATOMIC_LOAD_UMIN:
9732 case ISD::ATOMIC_LOAD_UMAX:
9738 SDValue fence = atomic.getOperand(0);
9739 if (fence.getOpcode() != ISD::MEMBARRIER)
9742 switch (atomic.getOpcode()) {
9743 case ISD::ATOMIC_CMP_SWAP:
9744 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9745 atomic.getOperand(1), atomic.getOperand(2),
9746 atomic.getOperand(3));
9747 case ISD::ATOMIC_SWAP:
9748 case ISD::ATOMIC_LOAD_ADD:
9749 case ISD::ATOMIC_LOAD_SUB:
9750 case ISD::ATOMIC_LOAD_AND:
9751 case ISD::ATOMIC_LOAD_OR:
9752 case ISD::ATOMIC_LOAD_XOR:
9753 case ISD::ATOMIC_LOAD_NAND:
9754 case ISD::ATOMIC_LOAD_MIN:
9755 case ISD::ATOMIC_LOAD_MAX:
9756 case ISD::ATOMIC_LOAD_UMIN:
9757 case ISD::ATOMIC_LOAD_UMAX:
9758 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9759 atomic.getOperand(1), atomic.getOperand(2));
9765 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9766 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
9767 // (and (i32 x86isd::setcc_carry), 1)
9768 // This eliminates the zext. This transformation is necessary because
9769 // ISD::SETCC is always legalized to i8.
9770 DebugLoc dl = N->getDebugLoc();
9771 SDValue N0 = N->getOperand(0);
9772 EVT VT = N->getValueType(0);
9773 if (N0.getOpcode() == ISD::AND &&
9775 N0.getOperand(0).hasOneUse()) {
9776 SDValue N00 = N0.getOperand(0);
9777 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9779 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
9780 if (!C || C->getZExtValue() != 1)
9782 return DAG.getNode(ISD::AND, dl, VT,
9783 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9784 N00.getOperand(0), N00.getOperand(1)),
9785 DAG.getConstant(1, VT));
9791 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9792 DAGCombinerInfo &DCI) const {
9793 SelectionDAG &DAG = DCI.DAG;
9794 switch (N->getOpcode()) {
9796 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9797 case ISD::EXTRACT_VECTOR_ELT:
9798 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
9799 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9800 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9801 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9804 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9805 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
9806 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9808 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9809 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9810 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9811 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9812 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
9813 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
9819 /// isTypeDesirableForOp - Return true if the target has native support for
9820 /// the specified value type and it is 'desirable' to use the type for the
9821 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
9822 /// instruction encodings are longer and some i16 instructions are slow.
9823 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
9824 if (!isTypeLegal(VT))
9833 case ISD::SIGN_EXTEND:
9834 case ISD::ZERO_EXTEND:
9835 case ISD::ANY_EXTEND:
9848 static bool MayFoldLoad(SDValue Op) {
9849 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
9852 static bool MayFoldIntoStore(SDValue Op) {
9853 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
9856 /// IsDesirableToPromoteOp - This method query the target whether it is
9857 /// beneficial for dag combiner to promote the specified node. If true, it
9858 /// should return the desired promotion type by reference.
9859 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
9860 EVT VT = Op.getValueType();
9864 bool Promote = false;
9865 bool Commute = false;
9866 switch (Op.getOpcode()) {
9869 LoadSDNode *LD = cast<LoadSDNode>(Op);
9870 // If the non-extending load has a single use and it's not live out, then it
9872 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
9874 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9875 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9876 // The only case where we'd want to promote LOAD (rather then it being
9877 // promoted as an operand is when it's only use is liveout.
9878 if (UI->getOpcode() != ISD::CopyToReg)
9885 case ISD::SIGN_EXTEND:
9886 case ISD::ZERO_EXTEND:
9887 case ISD::ANY_EXTEND:
9892 SDValue N0 = Op.getOperand(0);
9893 // Look out for (store (shl (load), x)).
9894 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
9907 SDValue N0 = Op.getOperand(0);
9908 SDValue N1 = Op.getOperand(1);
9909 if (!Commute && MayFoldLoad(N1))
9911 // Avoid disabling potential load folding opportunities.
9912 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
9914 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
9924 //===----------------------------------------------------------------------===//
9925 // X86 Inline Assembly Support
9926 //===----------------------------------------------------------------------===//
9928 static bool LowerToBSwap(CallInst *CI) {
9929 // FIXME: this should verify that we are targetting a 486 or better. If not,
9930 // we will turn this bswap into something that will be lowered to logical ops
9931 // instead of emitting the bswap asm. For now, we don't support 486 or lower
9932 // so don't worry about this.
9934 // Verify this is a simple bswap.
9935 if (CI->getNumOperands() != 2 ||
9936 CI->getType() != CI->getOperand(1)->getType() ||
9937 !CI->getType()->isIntegerTy())
9940 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
9941 if (!Ty || Ty->getBitWidth() % 16 != 0)
9944 // Okay, we can do this xform, do so now.
9945 const Type *Tys[] = { Ty };
9946 Module *M = CI->getParent()->getParent()->getParent();
9947 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
9949 Value *Op = CI->getOperand(1);
9950 Op = CallInst::Create(Int, Op, CI->getName(), CI);
9952 CI->replaceAllUsesWith(Op);
9953 CI->eraseFromParent();
9957 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
9958 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9959 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
9961 std::string AsmStr = IA->getAsmString();
9963 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
9964 SmallVector<StringRef, 4> AsmPieces;
9965 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
9967 switch (AsmPieces.size()) {
9968 default: return false;
9970 AsmStr = AsmPieces[0];
9972 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
9975 if (AsmPieces.size() == 2 &&
9976 (AsmPieces[0] == "bswap" ||
9977 AsmPieces[0] == "bswapq" ||
9978 AsmPieces[0] == "bswapl") &&
9979 (AsmPieces[1] == "$0" ||
9980 AsmPieces[1] == "${0:q}")) {
9981 // No need to check constraints, nothing other than the equivalent of
9982 // "=r,0" would be valid here.
9983 return LowerToBSwap(CI);
9985 // rorw $$8, ${0:w} --> llvm.bswap.i16
9986 if (CI->getType()->isIntegerTy(16) &&
9987 AsmPieces.size() == 3 &&
9988 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
9989 AsmPieces[1] == "$$8," &&
9990 AsmPieces[2] == "${0:w}" &&
9991 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
9993 const std::string &Constraints = IA->getConstraintString();
9994 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
9995 std::sort(AsmPieces.begin(), AsmPieces.end());
9996 if (AsmPieces.size() == 4 &&
9997 AsmPieces[0] == "~{cc}" &&
9998 AsmPieces[1] == "~{dirflag}" &&
9999 AsmPieces[2] == "~{flags}" &&
10000 AsmPieces[3] == "~{fpsr}") {
10001 return LowerToBSwap(CI);
10006 if (CI->getType()->isIntegerTy(64) &&
10007 Constraints.size() >= 2 &&
10008 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
10009 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
10010 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
10011 SmallVector<StringRef, 4> Words;
10012 SplitString(AsmPieces[0], Words, " \t");
10013 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
10015 SplitString(AsmPieces[1], Words, " \t");
10016 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
10018 SplitString(AsmPieces[2], Words, " \t,");
10019 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
10020 Words[2] == "%edx") {
10021 return LowerToBSwap(CI);
10033 /// getConstraintType - Given a constraint letter, return the type of
10034 /// constraint it is for this target.
10035 X86TargetLowering::ConstraintType
10036 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
10037 if (Constraint.size() == 1) {
10038 switch (Constraint[0]) {
10050 return C_RegisterClass;
10058 return TargetLowering::getConstraintType(Constraint);
10061 /// LowerXConstraint - try to replace an X constraint, which matches anything,
10062 /// with another that has more specific requirements based on the type of the
10063 /// corresponding operand.
10064 const char *X86TargetLowering::
10065 LowerXConstraint(EVT ConstraintVT) const {
10066 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
10067 // 'f' like normal targets.
10068 if (ConstraintVT.isFloatingPoint()) {
10069 if (Subtarget->hasSSE2())
10071 if (Subtarget->hasSSE1())
10075 return TargetLowering::LowerXConstraint(ConstraintVT);
10078 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10079 /// vector. If it is invalid, don't add anything to Ops.
10080 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10083 std::vector<SDValue>&Ops,
10084 SelectionDAG &DAG) const {
10085 SDValue Result(0, 0);
10087 switch (Constraint) {
10090 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10091 if (C->getZExtValue() <= 31) {
10092 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10098 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10099 if (C->getZExtValue() <= 63) {
10100 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10106 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10107 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
10108 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10114 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10115 if (C->getZExtValue() <= 255) {
10116 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10122 // 32-bit signed value
10123 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10124 const ConstantInt *CI = C->getConstantIntValue();
10125 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
10126 C->getSExtValue())) {
10127 // Widen to 64 bits here to get it sign extended.
10128 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
10131 // FIXME gcc accepts some relocatable values here too, but only in certain
10132 // memory models; it's complicated.
10137 // 32-bit unsigned value
10138 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10139 const ConstantInt *CI = C->getConstantIntValue();
10140 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
10141 C->getZExtValue())) {
10142 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10146 // FIXME gcc accepts some relocatable values here too, but only in certain
10147 // memory models; it's complicated.
10151 // Literal immediates are always ok.
10152 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
10153 // Widen to 64 bits here to get it sign extended.
10154 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
10158 // If we are in non-pic codegen mode, we allow the address of a global (with
10159 // an optional displacement) to be used with 'i'.
10160 GlobalAddressSDNode *GA = 0;
10161 int64_t Offset = 0;
10163 // Match either (GA), (GA+C), (GA+C1+C2), etc.
10165 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
10166 Offset += GA->getOffset();
10168 } else if (Op.getOpcode() == ISD::ADD) {
10169 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10170 Offset += C->getZExtValue();
10171 Op = Op.getOperand(0);
10174 } else if (Op.getOpcode() == ISD::SUB) {
10175 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10176 Offset += -C->getZExtValue();
10177 Op = Op.getOperand(0);
10182 // Otherwise, this isn't something we can handle, reject it.
10186 const GlobalValue *GV = GA->getGlobal();
10187 // If we require an extra load to get this address, as in PIC mode, we
10188 // can't accept it.
10189 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
10190 getTargetMachine())))
10194 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
10196 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
10202 if (Result.getNode()) {
10203 Ops.push_back(Result);
10206 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
10210 std::vector<unsigned> X86TargetLowering::
10211 getRegClassForInlineAsmConstraint(const std::string &Constraint,
10213 if (Constraint.size() == 1) {
10214 // FIXME: not handling fp-stack yet!
10215 switch (Constraint[0]) { // GCC X86 Constraint Letters
10216 default: break; // Unknown constraint letter
10217 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
10218 if (Subtarget->is64Bit()) {
10219 if (VT == MVT::i32)
10220 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
10221 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
10222 X86::R10D,X86::R11D,X86::R12D,
10223 X86::R13D,X86::R14D,X86::R15D,
10224 X86::EBP, X86::ESP, 0);
10225 else if (VT == MVT::i16)
10226 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
10227 X86::SI, X86::DI, X86::R8W,X86::R9W,
10228 X86::R10W,X86::R11W,X86::R12W,
10229 X86::R13W,X86::R14W,X86::R15W,
10230 X86::BP, X86::SP, 0);
10231 else if (VT == MVT::i8)
10232 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
10233 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
10234 X86::R10B,X86::R11B,X86::R12B,
10235 X86::R13B,X86::R14B,X86::R15B,
10236 X86::BPL, X86::SPL, 0);
10238 else if (VT == MVT::i64)
10239 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
10240 X86::RSI, X86::RDI, X86::R8, X86::R9,
10241 X86::R10, X86::R11, X86::R12,
10242 X86::R13, X86::R14, X86::R15,
10243 X86::RBP, X86::RSP, 0);
10247 // 32-bit fallthrough
10248 case 'Q': // Q_REGS
10249 if (VT == MVT::i32)
10250 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
10251 else if (VT == MVT::i16)
10252 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
10253 else if (VT == MVT::i8)
10254 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
10255 else if (VT == MVT::i64)
10256 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
10261 return std::vector<unsigned>();
10264 std::pair<unsigned, const TargetRegisterClass*>
10265 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10267 // First, see if this is a constraint that directly corresponds to an LLVM
10269 if (Constraint.size() == 1) {
10270 // GCC Constraint Letters
10271 switch (Constraint[0]) {
10273 case 'r': // GENERAL_REGS
10274 case 'l': // INDEX_REGS
10276 return std::make_pair(0U, X86::GR8RegisterClass);
10277 if (VT == MVT::i16)
10278 return std::make_pair(0U, X86::GR16RegisterClass);
10279 if (VT == MVT::i32 || !Subtarget->is64Bit())
10280 return std::make_pair(0U, X86::GR32RegisterClass);
10281 return std::make_pair(0U, X86::GR64RegisterClass);
10282 case 'R': // LEGACY_REGS
10284 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
10285 if (VT == MVT::i16)
10286 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
10287 if (VT == MVT::i32 || !Subtarget->is64Bit())
10288 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
10289 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
10290 case 'f': // FP Stack registers.
10291 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
10292 // value to the correct fpstack register class.
10293 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
10294 return std::make_pair(0U, X86::RFP32RegisterClass);
10295 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
10296 return std::make_pair(0U, X86::RFP64RegisterClass);
10297 return std::make_pair(0U, X86::RFP80RegisterClass);
10298 case 'y': // MMX_REGS if MMX allowed.
10299 if (!Subtarget->hasMMX()) break;
10300 return std::make_pair(0U, X86::VR64RegisterClass);
10301 case 'Y': // SSE_REGS if SSE2 allowed
10302 if (!Subtarget->hasSSE2()) break;
10304 case 'x': // SSE_REGS if SSE1 allowed
10305 if (!Subtarget->hasSSE1()) break;
10307 switch (VT.getSimpleVT().SimpleTy) {
10309 // Scalar SSE types.
10312 return std::make_pair(0U, X86::FR32RegisterClass);
10315 return std::make_pair(0U, X86::FR64RegisterClass);
10323 return std::make_pair(0U, X86::VR128RegisterClass);
10329 // Use the default implementation in TargetLowering to convert the register
10330 // constraint into a member of a register class.
10331 std::pair<unsigned, const TargetRegisterClass*> Res;
10332 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10334 // Not found as a standard register?
10335 if (Res.second == 0) {
10336 // Map st(0) -> st(7) -> ST0
10337 if (Constraint.size() == 7 && Constraint[0] == '{' &&
10338 tolower(Constraint[1]) == 's' &&
10339 tolower(Constraint[2]) == 't' &&
10340 Constraint[3] == '(' &&
10341 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
10342 Constraint[5] == ')' &&
10343 Constraint[6] == '}') {
10345 Res.first = X86::ST0+Constraint[4]-'0';
10346 Res.second = X86::RFP80RegisterClass;
10350 // GCC allows "st(0)" to be called just plain "st".
10351 if (StringRef("{st}").equals_lower(Constraint)) {
10352 Res.first = X86::ST0;
10353 Res.second = X86::RFP80RegisterClass;
10358 if (StringRef("{flags}").equals_lower(Constraint)) {
10359 Res.first = X86::EFLAGS;
10360 Res.second = X86::CCRRegisterClass;
10364 // 'A' means EAX + EDX.
10365 if (Constraint == "A") {
10366 Res.first = X86::EAX;
10367 Res.second = X86::GR32_ADRegisterClass;
10373 // Otherwise, check to see if this is a register class of the wrong value
10374 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
10375 // turn into {ax},{dx}.
10376 if (Res.second->hasType(VT))
10377 return Res; // Correct type already, nothing to do.
10379 // All of the single-register GCC register classes map their values onto
10380 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
10381 // really want an 8-bit or 32-bit register, map to the appropriate register
10382 // class and return the appropriate register.
10383 if (Res.second == X86::GR16RegisterClass) {
10384 if (VT == MVT::i8) {
10385 unsigned DestReg = 0;
10386 switch (Res.first) {
10388 case X86::AX: DestReg = X86::AL; break;
10389 case X86::DX: DestReg = X86::DL; break;
10390 case X86::CX: DestReg = X86::CL; break;
10391 case X86::BX: DestReg = X86::BL; break;
10394 Res.first = DestReg;
10395 Res.second = X86::GR8RegisterClass;
10397 } else if (VT == MVT::i32) {
10398 unsigned DestReg = 0;
10399 switch (Res.first) {
10401 case X86::AX: DestReg = X86::EAX; break;
10402 case X86::DX: DestReg = X86::EDX; break;
10403 case X86::CX: DestReg = X86::ECX; break;
10404 case X86::BX: DestReg = X86::EBX; break;
10405 case X86::SI: DestReg = X86::ESI; break;
10406 case X86::DI: DestReg = X86::EDI; break;
10407 case X86::BP: DestReg = X86::EBP; break;
10408 case X86::SP: DestReg = X86::ESP; break;
10411 Res.first = DestReg;
10412 Res.second = X86::GR32RegisterClass;
10414 } else if (VT == MVT::i64) {
10415 unsigned DestReg = 0;
10416 switch (Res.first) {
10418 case X86::AX: DestReg = X86::RAX; break;
10419 case X86::DX: DestReg = X86::RDX; break;
10420 case X86::CX: DestReg = X86::RCX; break;
10421 case X86::BX: DestReg = X86::RBX; break;
10422 case X86::SI: DestReg = X86::RSI; break;
10423 case X86::DI: DestReg = X86::RDI; break;
10424 case X86::BP: DestReg = X86::RBP; break;
10425 case X86::SP: DestReg = X86::RSP; break;
10428 Res.first = DestReg;
10429 Res.second = X86::GR64RegisterClass;
10432 } else if (Res.second == X86::FR32RegisterClass ||
10433 Res.second == X86::FR64RegisterClass ||
10434 Res.second == X86::VR128RegisterClass) {
10435 // Handle references to XMM physical registers that got mapped into the
10436 // wrong class. This can happen with constraints like {xmm0} where the
10437 // target independent register mapper will just pick the first match it can
10438 // find, ignoring the required type.
10439 if (VT == MVT::f32)
10440 Res.second = X86::FR32RegisterClass;
10441 else if (VT == MVT::f64)
10442 Res.second = X86::FR64RegisterClass;
10443 else if (X86::VR128RegisterClass->hasType(VT))
10444 Res.second = X86::VR128RegisterClass;