1 //===-- X86Instr3DNow.td - The 3DNow! Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the 3DNow! instruction set, which extends MMX to support
11 // floating point and also adds a few more random instructions for good measure.
13 //===----------------------------------------------------------------------===//
15 let Sched = WriteFAdd in {
16 def I3DNOW_FALU_ITINS : OpndItins<
17 IIC_3DNOW_FALU_RR, IIC_3DNOW_FALU_RM
21 let Sched = WriteCvtF2I in {
22 def I3DNOW_FCVT_F2I_ITINS : OpndItins<
23 IIC_3DNOW_FCVT_F2I_RR, IIC_3DNOW_FCVT_F2I_RM
27 let Sched = WriteCvtI2F in {
28 def I3DNOW_FCVT_I2F_ITINS : OpndItins<
29 IIC_3DNOW_FCVT_I2F_RR, IIC_3DNOW_FCVT_I2F_RM
33 let Sched = WriteVecIMul in {
34 def I3DNOW_MISC_FUNC_ITINS : OpndItins<
35 IIC_3DNOW_MISC_FUNC_REG, IIC_3DNOW_MISC_FUNC_MEM
39 let Sched = WriteShuffle in {
40 def I3DNOW_PSHUF_ITINS : OpndItins<
41 IIC_MMX_PSHUF, IIC_MMX_PSHUF
45 class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pat,
47 : I<o, F, outs, ins, asm, pat, itin>, TB, Requires<[Has3DNow]> {
50 class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat,
52 : I3DNow<o, F, (outs VR64:$dst), ins,
53 !strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), pat, itin>,
55 // FIXME: The disassembler doesn't support Has3DNow0F0FOpcode yet.
56 let isAsmParserOnly = 1;
57 let Constraints = "$src1 = $dst";
60 class I3DNow_conv<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat,
62 : I3DNow<o, F, (outs VR64:$dst), ins,
63 !strconcat(Mnemonic, "\t{$src, $dst|$dst, $src}"), pat, itin>,
65 // FIXME: The disassembler doesn't support Has3DNow0F0FOpcode yet.
66 let isAsmParserOnly = 1;
69 multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn, OpndItins itins,
70 bit Commutable = 0, string Ver = ""> {
71 let isCommutable = Commutable in
72 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
73 [(set VR64:$dst, (!cast<Intrinsic>(
74 !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, VR64:$src2))],
75 itins.rr>, Sched<[itins.Sched]>;
76 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn,
77 [(set VR64:$dst, (!cast<Intrinsic>(
78 !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1,
79 (bitconvert (load_mmx addr:$src2))))], itins.rm>,
80 Sched<[itins.Sched.Folded, ReadAfterLd]>;
83 multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn, OpndItins itins,
85 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
86 [(set VR64:$dst, (!cast<Intrinsic>(
87 !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src))], itins.rr>,
89 def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src), Mn,
90 [(set VR64:$dst, (!cast<Intrinsic>(
91 !strconcat("int_x86_3dnow", Ver, "_", Mn))
92 (bitconvert (load_mmx addr:$src))))], itins.rm>,
93 Sched<[itins.Sched.Folded, ReadAfterLd]>;
96 defm PAVGUSB : I3DNow_binop_rm_int<0xBF, "pavgusb", I3DNOW_MISC_FUNC_ITINS, 1>;
97 defm PF2ID : I3DNow_conv_rm_int<0x1D, "pf2id", I3DNOW_FCVT_F2I_ITINS>;
98 defm PFACC : I3DNow_binop_rm_int<0xAE, "pfacc", I3DNOW_FALU_ITINS>;
99 defm PFADD : I3DNow_binop_rm_int<0x9E, "pfadd", I3DNOW_FALU_ITINS, 1>;
100 defm PFCMPEQ : I3DNow_binop_rm_int<0xB0, "pfcmpeq", I3DNOW_FALU_ITINS, 1>;
101 defm PFCMPGE : I3DNow_binop_rm_int<0x90, "pfcmpge", I3DNOW_FALU_ITINS>;
102 defm PFCMPGT : I3DNow_binop_rm_int<0xA0, "pfcmpgt", I3DNOW_FALU_ITINS>;
103 defm PFMAX : I3DNow_binop_rm_int<0xA4, "pfmax", I3DNOW_FALU_ITINS>;
104 defm PFMIN : I3DNow_binop_rm_int<0x94, "pfmin", I3DNOW_FALU_ITINS>;
105 defm PFMUL : I3DNow_binop_rm_int<0xB4, "pfmul", I3DNOW_FALU_ITINS, 1>;
106 defm PFRCP : I3DNow_conv_rm_int<0x96, "pfrcp", I3DNOW_FALU_ITINS>;
107 defm PFRCPIT1 : I3DNow_binop_rm_int<0xA6, "pfrcpit1", I3DNOW_FALU_ITINS>;
108 defm PFRCPIT2 : I3DNow_binop_rm_int<0xB6, "pfrcpit2", I3DNOW_FALU_ITINS>;
109 defm PFRSQIT1 : I3DNow_binop_rm_int<0xA7, "pfrsqit1", I3DNOW_FALU_ITINS>;
110 defm PFRSQRT : I3DNow_conv_rm_int<0x97, "pfrsqrt", I3DNOW_FALU_ITINS>;
111 defm PFSUB : I3DNow_binop_rm_int<0x9A, "pfsub", I3DNOW_FALU_ITINS, 1>;
112 defm PFSUBR : I3DNow_binop_rm_int<0xAA, "pfsubr", I3DNOW_FALU_ITINS, 1>;
113 defm PI2FD : I3DNow_conv_rm_int<0x0D, "pi2fd", I3DNOW_FCVT_I2F_ITINS>;
114 defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw", I3DNOW_MISC_FUNC_ITINS, 1>;
116 def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms",
117 [(int_x86_mmx_femms)], IIC_MMX_EMMS>;
119 // PREFETCHWT1 is supported we want to use it for everything but T0.
120 def PrefetchWLevel : PatFrag<(ops), (i32 imm), [{
121 return N->getSExtValue() == 3 || !Subtarget->hasPREFETCHWT1();
124 // Use PREFETCHWT1 for NTA, T2, T1.
125 def PrefetchWT1Level : ImmLeaf<i32, [{
129 let SchedRW = [WriteLoad] in {
130 let Predicates = [Has3DNow, NoSSEPrefetch] in
131 def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr),
133 [(prefetch addr:$addr, imm, imm, (i32 1))],
136 def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr",
137 [(prefetch addr:$addr, (i32 1), (i32 PrefetchWLevel), (i32 1))],
138 IIC_SSE_PREFETCH>, TB, Requires<[HasPrefetchW]>;
140 def PREFETCHWT1 : I<0x0D, MRM2m, (outs), (ins i8mem:$addr), "prefetchwt1\t$addr",
141 [(prefetch addr:$addr, (i32 1), (i32 PrefetchWT1Level), (i32 1))],
142 IIC_SSE_PREFETCH>, TB, Requires<[HasPREFETCHWT1]>;
145 // "3DNowA" instructions
146 defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", I3DNOW_FCVT_F2I_ITINS, "a">;
147 defm PI2FW : I3DNow_conv_rm_int<0x0C, "pi2fw", I3DNOW_FCVT_I2F_ITINS, "a">;
148 defm PFNACC : I3DNow_binop_rm_int<0x8A, "pfnacc", I3DNOW_FALU_ITINS, 0, "a">;
149 defm PFPNACC : I3DNow_binop_rm_int<0x8E, "pfpnacc", I3DNOW_FALU_ITINS, 0, "a">;
150 defm PSWAPD : I3DNow_conv_rm_int<0xBB, "pswapd", I3DNOW_PSHUF_ITINS, "a">;