1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
47 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
49 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
50 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
51 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
53 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
54 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
57 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
59 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
63 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
65 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
67 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
69 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
71 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
73 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
77 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
78 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
79 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
80 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
82 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
84 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
86 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
87 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
89 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
91 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
92 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
94 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
95 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
97 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
98 [SDNPHasChain, SDNPMayStore,
99 SDNPMayLoad, SDNPMemOperand]>;
100 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
101 [SDNPHasChain, SDNPMayStore,
102 SDNPMayLoad, SDNPMemOperand]>;
103 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
104 [SDNPHasChain, SDNPMayStore,
105 SDNPMayLoad, SDNPMemOperand]>;
106 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
107 [SDNPHasChain, SDNPMayStore,
108 SDNPMayLoad, SDNPMemOperand]>;
109 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
110 [SDNPHasChain, SDNPMayStore,
111 SDNPMayLoad, SDNPMemOperand]>;
112 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
113 [SDNPHasChain, SDNPMayStore,
114 SDNPMayLoad, SDNPMemOperand]>;
115 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
116 [SDNPHasChain, SDNPMayStore,
117 SDNPMayLoad, SDNPMemOperand]>;
118 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
119 [SDNPHasChain, SDNPOptInFlag]>;
121 def X86vastart_save_xmm_regs :
122 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
123 SDT_X86VASTART_SAVE_XMM_REGS,
126 def X86callseq_start :
127 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
128 [SDNPHasChain, SDNPOutFlag]>;
130 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
131 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
133 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
134 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
136 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
137 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
138 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
139 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
142 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
143 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
145 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
146 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
148 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
149 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
150 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
151 SDT_X86SegmentBaseAddress, []>;
153 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
156 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
157 [SDNPHasChain, SDNPOptInFlag]>;
159 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>;
160 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
161 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
162 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
163 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
164 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
165 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags>;
166 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags>;
167 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags>;
169 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
171 //===----------------------------------------------------------------------===//
172 // X86 Operand Definitions.
175 def i32imm_pcrel : Operand<i32> {
176 let PrintMethod = "print_pcrel_imm";
179 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
180 // the index operand of an address, to conform to x86 encoding restrictions.
181 def ptr_rc_nosp : PointerLikeRegClass<1>;
183 // *mem - Operand definitions for the funky X86 addressing mode operands.
185 def X86MemAsmOperand : AsmOperandClass {
189 class X86MemOperand<string printMethod> : Operand<iPTR> {
190 let PrintMethod = printMethod;
191 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
192 let ParserMatchClass = X86MemAsmOperand;
195 def opaque32mem : X86MemOperand<"printopaquemem">;
196 def opaque48mem : X86MemOperand<"printopaquemem">;
197 def opaque80mem : X86MemOperand<"printopaquemem">;
199 def i8mem : X86MemOperand<"printi8mem">;
200 def i16mem : X86MemOperand<"printi16mem">;
201 def i32mem : X86MemOperand<"printi32mem">;
202 def i64mem : X86MemOperand<"printi64mem">;
203 def i128mem : X86MemOperand<"printi128mem">;
204 //def i256mem : X86MemOperand<"printi256mem">;
205 def f32mem : X86MemOperand<"printf32mem">;
206 def f64mem : X86MemOperand<"printf64mem">;
207 def f80mem : X86MemOperand<"printf80mem">;
208 def f128mem : X86MemOperand<"printf128mem">;
209 //def f256mem : X86MemOperand<"printf256mem">;
211 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
212 // plain GR64, so that it doesn't potentially require a REX prefix.
213 def i8mem_NOREX : Operand<i64> {
214 let PrintMethod = "printi8mem";
215 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
216 let ParserMatchClass = X86MemAsmOperand;
219 def lea32mem : Operand<i32> {
220 let PrintMethod = "printlea32mem";
221 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
222 let ParserMatchClass = X86MemAsmOperand;
225 def SSECC : Operand<i8> {
226 let PrintMethod = "printSSECC";
229 def ImmSExt8AsmOperand : AsmOperandClass {
230 let Name = "ImmSExt8";
231 let SuperClass = ImmAsmOperand;
234 // A couple of more descriptive operand definitions.
235 // 16-bits but only 8 bits are significant.
236 def i16i8imm : Operand<i16> {
237 let ParserMatchClass = ImmSExt8AsmOperand;
239 // 32-bits but only 8 bits are significant.
240 def i32i8imm : Operand<i32> {
241 let ParserMatchClass = ImmSExt8AsmOperand;
244 // Branch targets have OtherVT type and print as pc-relative values.
245 def brtarget : Operand<OtherVT> {
246 let PrintMethod = "print_pcrel_imm";
249 def brtarget8 : Operand<OtherVT> {
250 let PrintMethod = "print_pcrel_imm";
253 //===----------------------------------------------------------------------===//
254 // X86 Complex Pattern Definitions.
257 // Define X86 specific addressing mode.
258 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
259 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
260 [add, sub, mul, X86mul_imm, shl, or, frameindex],
262 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
263 [tglobaltlsaddr], []>;
265 //===----------------------------------------------------------------------===//
266 // X86 Instruction Predicate Definitions.
267 def HasMMX : Predicate<"Subtarget->hasMMX()">;
268 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
269 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
270 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
271 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
272 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
273 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
274 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
275 def HasAVX : Predicate<"Subtarget->hasAVX()">;
276 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
277 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
278 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
279 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
280 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
281 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
282 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
283 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
284 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
285 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
286 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
287 "TM.getCodeModel() != CodeModel::Kernel">;
288 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
289 "TM.getCodeModel() == CodeModel::Kernel">;
290 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
291 def OptForSpeed : Predicate<"!OptForSize">;
292 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
293 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
295 //===----------------------------------------------------------------------===//
296 // X86 Instruction Format Definitions.
299 include "X86InstrFormats.td"
301 //===----------------------------------------------------------------------===//
302 // Pattern fragments...
305 // X86 specific condition code. These correspond to CondCode in
306 // X86InstrInfo.h. They must be kept in synch.
307 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
308 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
309 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
310 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
311 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
312 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
313 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
314 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
315 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
316 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
317 def X86_COND_NO : PatLeaf<(i8 10)>;
318 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
319 def X86_COND_NS : PatLeaf<(i8 12)>;
320 def X86_COND_O : PatLeaf<(i8 13)>;
321 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
322 def X86_COND_S : PatLeaf<(i8 15)>;
324 def i16immSExt8 : PatLeaf<(i16 imm), [{
325 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
326 // sign extended field.
327 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
330 def i32immSExt8 : PatLeaf<(i32 imm), [{
331 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
332 // sign extended field.
333 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
336 // Helper fragments for loads.
337 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
338 // known to be 32-bit aligned or better. Ditto for i8 to i16.
339 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
340 LoadSDNode *LD = cast<LoadSDNode>(N);
341 if (const Value *Src = LD->getSrcValue())
342 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
343 if (PT->getAddressSpace() > 255)
345 ISD::LoadExtType ExtType = LD->getExtensionType();
346 if (ExtType == ISD::NON_EXTLOAD)
348 if (ExtType == ISD::EXTLOAD)
349 return LD->getAlignment() >= 2 && !LD->isVolatile();
353 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
354 LoadSDNode *LD = cast<LoadSDNode>(N);
355 if (const Value *Src = LD->getSrcValue())
356 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
357 if (PT->getAddressSpace() > 255)
359 ISD::LoadExtType ExtType = LD->getExtensionType();
360 if (ExtType == ISD::EXTLOAD)
361 return LD->getAlignment() >= 2 && !LD->isVolatile();
365 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
366 LoadSDNode *LD = cast<LoadSDNode>(N);
367 if (const Value *Src = LD->getSrcValue())
368 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
369 if (PT->getAddressSpace() > 255)
371 ISD::LoadExtType ExtType = LD->getExtensionType();
372 if (ExtType == ISD::NON_EXTLOAD)
374 if (ExtType == ISD::EXTLOAD)
375 return LD->getAlignment() >= 4 && !LD->isVolatile();
379 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
380 LoadSDNode *LD = cast<LoadSDNode>(N);
381 if (const Value *Src = LD->getSrcValue())
382 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
383 if (PT->getAddressSpace() > 255)
385 if (LD->isVolatile())
387 ISD::LoadExtType ExtType = LD->getExtensionType();
388 if (ExtType == ISD::NON_EXTLOAD)
390 if (ExtType == ISD::EXTLOAD)
391 return LD->getAlignment() >= 4;
395 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
396 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
397 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
398 return PT->getAddressSpace() == 256;
402 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
403 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
404 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
405 return PT->getAddressSpace() == 257;
409 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
410 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
411 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
412 if (PT->getAddressSpace() > 255)
416 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
417 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
418 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
419 if (PT->getAddressSpace() > 255)
424 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
425 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
426 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
427 if (PT->getAddressSpace() > 255)
431 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
432 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
433 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
434 if (PT->getAddressSpace() > 255)
438 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
439 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
440 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
441 if (PT->getAddressSpace() > 255)
446 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
447 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
448 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
450 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
451 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
452 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
453 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
454 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
455 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
457 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
458 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
459 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
460 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
461 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
462 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
465 // An 'and' node with a single use.
466 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
467 return N->hasOneUse();
469 // An 'srl' node with a single use.
470 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
471 return N->hasOneUse();
473 // An 'trunc' node with a single use.
474 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
475 return N->hasOneUse();
478 // 'shld' and 'shrd' instruction patterns. Note that even though these have
479 // the srl and shl in their patterns, the C++ code must still check for them,
480 // because predicates are tested before children nodes are explored.
482 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
483 (or (srl node:$src1, node:$amt1),
484 (shl node:$src2, node:$amt2)), [{
485 assert(N->getOpcode() == ISD::OR);
486 return N->getOperand(0).getOpcode() == ISD::SRL &&
487 N->getOperand(1).getOpcode() == ISD::SHL &&
488 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
489 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
490 N->getOperand(0).getConstantOperandVal(1) ==
491 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
494 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
495 (or (shl node:$src1, node:$amt1),
496 (srl node:$src2, node:$amt2)), [{
497 assert(N->getOpcode() == ISD::OR);
498 return N->getOperand(0).getOpcode() == ISD::SHL &&
499 N->getOperand(1).getOpcode() == ISD::SRL &&
500 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
501 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
502 N->getOperand(0).getConstantOperandVal(1) ==
503 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
506 //===----------------------------------------------------------------------===//
507 // Instruction list...
510 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
511 // a stack adjustment and the codegen must know that they may modify the stack
512 // pointer before prolog-epilog rewriting occurs.
513 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
514 // sub / add which can clobber EFLAGS.
515 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
516 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
518 [(X86callseq_start timm:$amt)]>,
519 Requires<[In32BitMode]>;
520 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
522 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
523 Requires<[In32BitMode]>;
526 // x86-64 va_start lowering magic.
527 let usesCustomInserter = 1 in
528 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
531 i64imm:$regsavefi, i64imm:$offset,
533 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
534 [(X86vastart_save_xmm_regs GR8:$al,
539 let neverHasSideEffects = 1 in {
540 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
541 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
542 "nopl\t$zero", []>, TB;
546 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int\t3", []>;
547 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
549 // PIC base construction. This expands to code that looks like this:
552 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
553 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
556 //===----------------------------------------------------------------------===//
557 // Control Flow Instructions...
560 // Return instructions.
561 let isTerminator = 1, isReturn = 1, isBarrier = 1,
562 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
563 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
566 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
568 [(X86retflag timm:$amt)]>;
569 def LRET : I <0xCB, RawFrm, (outs), (ins),
571 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
575 // All branches are RawFrm, Void, Branch, and Terminators
576 let isBranch = 1, isTerminator = 1 in
577 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
578 I<opcode, RawFrm, (outs), ins, asm, pattern>;
580 let isBranch = 1, isBarrier = 1 in {
581 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
582 def JMP8 : IBr<0xEB, (ins brtarget8:$dst), "jmp\t$dst", []>;
586 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
587 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
588 [(brind GR32:$dst)]>;
589 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
590 [(brind (loadi32 addr:$dst))]>;
592 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
593 (ins i16imm:$seg, i16imm:$off),
594 "ljmp{w}\t$seg, $off", []>, OpSize;
595 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
596 (ins i16imm:$seg, i32imm:$off),
597 "ljmp{l}\t$seg, $off", []>;
599 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
600 "ljmp{w}\t{*}$dst", []>, OpSize;
601 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
602 "ljmp{l}\t{*}$dst", []>;
605 // Conditional branches
606 let Uses = [EFLAGS] in {
607 // Short conditional jumps
608 def JO8 : IBr<0x70, (ins brtarget8:$dst), "jo\t$dst", []>;
609 def JNO8 : IBr<0x71, (ins brtarget8:$dst), "jno\t$dst", []>;
610 def JB8 : IBr<0x72, (ins brtarget8:$dst), "jb\t$dst", []>;
611 def JAE8 : IBr<0x73, (ins brtarget8:$dst), "jae\t$dst", []>;
612 def JE8 : IBr<0x74, (ins brtarget8:$dst), "je\t$dst", []>;
613 def JNE8 : IBr<0x75, (ins brtarget8:$dst), "jne\t$dst", []>;
614 def JBE8 : IBr<0x76, (ins brtarget8:$dst), "jbe\t$dst", []>;
615 def JA8 : IBr<0x77, (ins brtarget8:$dst), "ja\t$dst", []>;
616 def JS8 : IBr<0x78, (ins brtarget8:$dst), "js\t$dst", []>;
617 def JNS8 : IBr<0x79, (ins brtarget8:$dst), "jns\t$dst", []>;
618 def JP8 : IBr<0x7A, (ins brtarget8:$dst), "jp\t$dst", []>;
619 def JNP8 : IBr<0x7B, (ins brtarget8:$dst), "jnp\t$dst", []>;
620 def JL8 : IBr<0x7C, (ins brtarget8:$dst), "jl\t$dst", []>;
621 def JGE8 : IBr<0x7D, (ins brtarget8:$dst), "jge\t$dst", []>;
622 def JLE8 : IBr<0x7E, (ins brtarget8:$dst), "jle\t$dst", []>;
623 def JG8 : IBr<0x7F, (ins brtarget8:$dst), "jg\t$dst", []>;
625 def JCXZ8 : IBr<0xE3, (ins brtarget8:$dst), "jcxz\t$dst", []>;
627 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
628 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
629 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
630 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
631 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
632 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
633 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
634 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
635 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
636 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
637 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
638 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
640 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
641 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
642 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
643 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
644 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
645 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
646 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
647 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
649 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
650 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
651 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
652 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
653 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
654 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
655 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
656 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
657 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
658 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
659 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
660 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
665 def LOOP : I<0xE2, RawFrm, (ins brtarget8:$dst), (outs), "loop\t$dst", []>;
666 def LOOPE : I<0xE1, RawFrm, (ins brtarget8:$dst), (outs), "loope\t$dst", []>;
667 def LOOPNE : I<0xE0, RawFrm, (ins brtarget8:$dst), (outs), "loopne\t$dst", []>;
669 //===----------------------------------------------------------------------===//
670 // Call Instructions...
673 // All calls clobber the non-callee saved registers. ESP is marked as
674 // a use to prevent stack-pointer assignments that appear immediately
675 // before calls from potentially appearing dead. Uses for argument
676 // registers are added manually.
677 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
678 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
679 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
680 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
682 def CALLpcrel32 : Ii32<0xE8, RawFrm,
683 (outs), (ins i32imm_pcrel:$dst,variable_ops),
685 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
686 "call\t{*}$dst", [(X86call GR32:$dst)]>;
687 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
688 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
690 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
691 (ins i16imm:$seg, i16imm:$off),
692 "lcall{w}\t$seg, $off", []>, OpSize;
693 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
694 (ins i16imm:$seg, i32imm:$off),
695 "lcall{l}\t$seg, $off", []>;
697 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
698 "lcall{w}\t{*}$dst", []>, OpSize;
699 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
700 "lcall{l}\t{*}$dst", []>;
703 // Constructing a stack frame.
705 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
706 "enter\t$len, $lvl", []>;
710 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
711 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
712 "#TC_RETURN $dst $offset",
715 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
716 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
717 "#TC_RETURN $dst $offset",
720 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
722 def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst), "jmp\t$dst # TAILCALL",
724 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
725 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
727 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
728 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
729 "jmp\t{*}$dst # TAILCALL", []>;
731 //===----------------------------------------------------------------------===//
732 // Miscellaneous Instructions...
734 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
735 def LEAVE : I<0xC9, RawFrm,
736 (outs), (ins), "leave", []>;
738 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
740 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
742 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
743 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
745 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
747 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
748 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
751 let mayStore = 1 in {
752 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
754 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
755 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
757 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
759 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
760 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
764 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
765 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
766 "push{l}\t$imm", []>;
767 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
768 "push{l}\t$imm", []>;
769 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
770 "push{l}\t$imm", []>;
773 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
774 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
775 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
776 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
778 let isTwoAddress = 1 in // GR32 = bswap GR32
779 def BSWAP32r : I<0xC8, AddRegFrm,
780 (outs GR32:$dst), (ins GR32:$src),
782 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
785 // Bit scan instructions.
786 let Defs = [EFLAGS] in {
787 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
788 "bsf{w}\t{$src, $dst|$dst, $src}",
789 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
790 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
791 "bsf{w}\t{$src, $dst|$dst, $src}",
792 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
793 (implicit EFLAGS)]>, TB;
794 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
795 "bsf{l}\t{$src, $dst|$dst, $src}",
796 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
797 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
798 "bsf{l}\t{$src, $dst|$dst, $src}",
799 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
800 (implicit EFLAGS)]>, TB;
802 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
803 "bsr{w}\t{$src, $dst|$dst, $src}",
804 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
805 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
806 "bsr{w}\t{$src, $dst|$dst, $src}",
807 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
808 (implicit EFLAGS)]>, TB;
809 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
810 "bsr{l}\t{$src, $dst|$dst, $src}",
811 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
812 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
813 "bsr{l}\t{$src, $dst|$dst, $src}",
814 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
815 (implicit EFLAGS)]>, TB;
818 let neverHasSideEffects = 1 in
819 def LEA16r : I<0x8D, MRMSrcMem,
820 (outs GR16:$dst), (ins i32mem:$src),
821 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
822 let isReMaterializable = 1 in
823 def LEA32r : I<0x8D, MRMSrcMem,
824 (outs GR32:$dst), (ins lea32mem:$src),
825 "lea{l}\t{$src|$dst}, {$dst|$src}",
826 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
828 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
829 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
830 [(X86rep_movs i8)]>, REP;
831 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
832 [(X86rep_movs i16)]>, REP, OpSize;
833 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
834 [(X86rep_movs i32)]>, REP;
837 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
838 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
839 [(X86rep_stos i8)]>, REP;
840 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
841 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
842 [(X86rep_stos i16)]>, REP, OpSize;
843 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
844 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
845 [(X86rep_stos i32)]>, REP;
847 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
848 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
849 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
851 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
852 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
853 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
855 let Defs = [RAX, RDX] in
856 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
859 let isBarrier = 1, hasCtrlDep = 1 in {
860 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
863 def SYSCALL : I<0x05, RawFrm,
864 (outs), (ins), "syscall", []>, TB;
865 def SYSRET : I<0x07, RawFrm,
866 (outs), (ins), "sysret", []>, TB;
867 def SYSENTER : I<0x34, RawFrm,
868 (outs), (ins), "sysenter", []>, TB;
869 def SYSEXIT : I<0x35, RawFrm,
870 (outs), (ins), "sysexit", []>, TB;
872 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
875 //===----------------------------------------------------------------------===//
876 // Input/Output Instructions...
878 let Defs = [AL], Uses = [DX] in
879 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
880 "in{b}\t{%dx, %al|%AL, %DX}", []>;
881 let Defs = [AX], Uses = [DX] in
882 def IN16rr : I<0xED, RawFrm, (outs), (ins),
883 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
884 let Defs = [EAX], Uses = [DX] in
885 def IN32rr : I<0xED, RawFrm, (outs), (ins),
886 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
889 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
890 "in{b}\t{$port, %al|%AL, $port}", []>;
892 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
893 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
895 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
896 "in{l}\t{$port, %eax|%EAX, $port}", []>;
898 let Uses = [DX, AL] in
899 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
900 "out{b}\t{%al, %dx|%DX, %AL}", []>;
901 let Uses = [DX, AX] in
902 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
903 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
904 let Uses = [DX, EAX] in
905 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
906 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
909 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
910 "out{b}\t{%al, $port|$port, %AL}", []>;
912 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
913 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
915 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
916 "out{l}\t{%eax, $port|$port, %EAX}", []>;
918 //===----------------------------------------------------------------------===//
919 // Move Instructions...
921 let neverHasSideEffects = 1 in {
922 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
923 "mov{b}\t{$src, $dst|$dst, $src}", []>;
924 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
925 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
926 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
927 "mov{l}\t{$src, $dst|$dst, $src}", []>;
929 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
930 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
931 "mov{b}\t{$src, $dst|$dst, $src}",
932 [(set GR8:$dst, imm:$src)]>;
933 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
934 "mov{w}\t{$src, $dst|$dst, $src}",
935 [(set GR16:$dst, imm:$src)]>, OpSize;
936 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
937 "mov{l}\t{$src, $dst|$dst, $src}",
938 [(set GR32:$dst, imm:$src)]>;
940 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
941 "mov{b}\t{$src, $dst|$dst, $src}",
942 [(store (i8 imm:$src), addr:$dst)]>;
943 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
944 "mov{w}\t{$src, $dst|$dst, $src}",
945 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
946 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
947 "mov{l}\t{$src, $dst|$dst, $src}",
948 [(store (i32 imm:$src), addr:$dst)]>;
950 def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins i8imm:$src),
951 "mov{b}\t{$src, %al|%al, $src}", []>;
952 def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins i16imm:$src),
953 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
954 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins i32imm:$src),
955 "mov{l}\t{$src, %eax|%eax, $src}", []>;
957 def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs i8imm:$dst), (ins),
958 "mov{b}\t{%al, $dst|$dst, %al}", []>;
959 def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs i16imm:$dst), (ins),
960 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
961 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs i32imm:$dst), (ins),
962 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
964 // Moves to and from segment registers
965 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
966 "mov{w}\t{$src, $dst|$dst, $src}", []>;
967 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
968 "mov{w}\t{$src, $dst|$dst, $src}", []>;
969 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
970 "mov{w}\t{$src, $dst|$dst, $src}", []>;
971 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
972 "mov{w}\t{$src, $dst|$dst, $src}", []>;
974 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
975 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
976 "mov{b}\t{$src, $dst|$dst, $src}",
977 [(set GR8:$dst, (loadi8 addr:$src))]>;
978 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
979 "mov{w}\t{$src, $dst|$dst, $src}",
980 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
981 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
982 "mov{l}\t{$src, $dst|$dst, $src}",
983 [(set GR32:$dst, (loadi32 addr:$src))]>;
986 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
987 "mov{b}\t{$src, $dst|$dst, $src}",
988 [(store GR8:$src, addr:$dst)]>;
989 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
990 "mov{w}\t{$src, $dst|$dst, $src}",
991 [(store GR16:$src, addr:$dst)]>, OpSize;
992 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
993 "mov{l}\t{$src, $dst|$dst, $src}",
994 [(store GR32:$src, addr:$dst)]>;
996 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
997 // that they can be used for copying and storing h registers, which can't be
998 // encoded when a REX prefix is present.
999 let neverHasSideEffects = 1 in
1000 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1001 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1002 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1004 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1005 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1006 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1008 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1009 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1010 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1011 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1013 //===----------------------------------------------------------------------===//
1014 // Fixed-Register Multiplication and Division Instructions...
1017 // Extra precision multiplication
1018 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1019 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1020 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1021 // This probably ought to be moved to a def : Pat<> if the
1022 // syntax can be accepted.
1023 [(set AL, (mul AL, GR8:$src)),
1024 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1026 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1027 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1029 []>, OpSize; // AX,DX = AX*GR16
1031 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1032 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1034 []>; // EAX,EDX = EAX*GR32
1036 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1037 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1039 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1040 // This probably ought to be moved to a def : Pat<> if the
1041 // syntax can be accepted.
1042 [(set AL, (mul AL, (loadi8 addr:$src))),
1043 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1045 let mayLoad = 1, neverHasSideEffects = 1 in {
1046 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1047 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1049 []>, OpSize; // AX,DX = AX*[mem16]
1051 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1052 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1054 []>; // EAX,EDX = EAX*[mem32]
1057 let neverHasSideEffects = 1 in {
1058 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1059 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1061 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1062 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1063 OpSize; // AX,DX = AX*GR16
1064 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1065 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1066 // EAX,EDX = EAX*GR32
1067 let mayLoad = 1 in {
1068 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1069 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1070 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1071 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1072 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1073 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1074 let Defs = [EAX,EDX], Uses = [EAX] in
1075 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1076 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1078 } // neverHasSideEffects
1080 // unsigned division/remainder
1081 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1082 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1083 "div{b}\t$src", []>;
1084 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1085 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1086 "div{w}\t$src", []>, OpSize;
1087 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1088 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1089 "div{l}\t$src", []>;
1090 let mayLoad = 1 in {
1091 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1092 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1093 "div{b}\t$src", []>;
1094 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1095 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1096 "div{w}\t$src", []>, OpSize;
1097 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1098 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
1099 "div{l}\t$src", []>;
1102 // Signed division/remainder.
1103 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1104 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1105 "idiv{b}\t$src", []>;
1106 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1107 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1108 "idiv{w}\t$src", []>, OpSize;
1109 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1110 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1111 "idiv{l}\t$src", []>;
1112 let mayLoad = 1, mayLoad = 1 in {
1113 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1114 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1115 "idiv{b}\t$src", []>;
1116 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1117 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1118 "idiv{w}\t$src", []>, OpSize;
1119 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1120 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
1121 "idiv{l}\t$src", []>;
1124 //===----------------------------------------------------------------------===//
1125 // Two address Instructions.
1127 let isTwoAddress = 1 in {
1129 // Conditional moves
1130 let Uses = [EFLAGS] in {
1132 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1133 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1134 // however that requires promoting the operands, and can induce additional
1135 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1136 // clobber EFLAGS, because if one of the operands is zero, the expansion
1137 // could involve an xor.
1138 let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in
1139 def CMOV_GR8 : I<0, Pseudo,
1140 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1141 "#CMOV_GR8 PSEUDO!",
1142 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1143 imm:$cond, EFLAGS))]>;
1145 let isCommutable = 1 in {
1146 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1147 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1148 "cmovb\t{$src2, $dst|$dst, $src2}",
1149 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1150 X86_COND_B, EFLAGS))]>,
1152 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1153 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1154 "cmovb\t{$src2, $dst|$dst, $src2}",
1155 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1156 X86_COND_B, EFLAGS))]>,
1158 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1159 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1160 "cmovae\t{$src2, $dst|$dst, $src2}",
1161 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1162 X86_COND_AE, EFLAGS))]>,
1164 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1165 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1166 "cmovae\t{$src2, $dst|$dst, $src2}",
1167 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1168 X86_COND_AE, EFLAGS))]>,
1170 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1171 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1172 "cmove\t{$src2, $dst|$dst, $src2}",
1173 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1174 X86_COND_E, EFLAGS))]>,
1176 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1177 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1178 "cmove\t{$src2, $dst|$dst, $src2}",
1179 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1180 X86_COND_E, EFLAGS))]>,
1182 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1183 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1184 "cmovne\t{$src2, $dst|$dst, $src2}",
1185 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1186 X86_COND_NE, EFLAGS))]>,
1188 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1189 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1190 "cmovne\t{$src2, $dst|$dst, $src2}",
1191 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1192 X86_COND_NE, EFLAGS))]>,
1194 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1195 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1196 "cmovbe\t{$src2, $dst|$dst, $src2}",
1197 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1198 X86_COND_BE, EFLAGS))]>,
1200 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1201 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1202 "cmovbe\t{$src2, $dst|$dst, $src2}",
1203 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1204 X86_COND_BE, EFLAGS))]>,
1206 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1207 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1208 "cmova\t{$src2, $dst|$dst, $src2}",
1209 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1210 X86_COND_A, EFLAGS))]>,
1212 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1213 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1214 "cmova\t{$src2, $dst|$dst, $src2}",
1215 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1216 X86_COND_A, EFLAGS))]>,
1218 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1219 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1220 "cmovl\t{$src2, $dst|$dst, $src2}",
1221 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1222 X86_COND_L, EFLAGS))]>,
1224 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1225 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1226 "cmovl\t{$src2, $dst|$dst, $src2}",
1227 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1228 X86_COND_L, EFLAGS))]>,
1230 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1231 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1232 "cmovge\t{$src2, $dst|$dst, $src2}",
1233 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1234 X86_COND_GE, EFLAGS))]>,
1236 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1237 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1238 "cmovge\t{$src2, $dst|$dst, $src2}",
1239 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1240 X86_COND_GE, EFLAGS))]>,
1242 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1243 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1244 "cmovle\t{$src2, $dst|$dst, $src2}",
1245 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1246 X86_COND_LE, EFLAGS))]>,
1248 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1249 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1250 "cmovle\t{$src2, $dst|$dst, $src2}",
1251 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1252 X86_COND_LE, EFLAGS))]>,
1254 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1255 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1256 "cmovg\t{$src2, $dst|$dst, $src2}",
1257 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1258 X86_COND_G, EFLAGS))]>,
1260 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1261 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1262 "cmovg\t{$src2, $dst|$dst, $src2}",
1263 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1264 X86_COND_G, EFLAGS))]>,
1266 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1267 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1268 "cmovs\t{$src2, $dst|$dst, $src2}",
1269 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1270 X86_COND_S, EFLAGS))]>,
1272 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1273 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1274 "cmovs\t{$src2, $dst|$dst, $src2}",
1275 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1276 X86_COND_S, EFLAGS))]>,
1278 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1279 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1280 "cmovns\t{$src2, $dst|$dst, $src2}",
1281 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1282 X86_COND_NS, EFLAGS))]>,
1284 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1285 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1286 "cmovns\t{$src2, $dst|$dst, $src2}",
1287 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1288 X86_COND_NS, EFLAGS))]>,
1290 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1291 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1292 "cmovp\t{$src2, $dst|$dst, $src2}",
1293 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1294 X86_COND_P, EFLAGS))]>,
1296 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1297 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1298 "cmovp\t{$src2, $dst|$dst, $src2}",
1299 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1300 X86_COND_P, EFLAGS))]>,
1302 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1303 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1304 "cmovnp\t{$src2, $dst|$dst, $src2}",
1305 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1306 X86_COND_NP, EFLAGS))]>,
1308 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1309 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1310 "cmovnp\t{$src2, $dst|$dst, $src2}",
1311 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1312 X86_COND_NP, EFLAGS))]>,
1314 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1315 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1316 "cmovo\t{$src2, $dst|$dst, $src2}",
1317 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1318 X86_COND_O, EFLAGS))]>,
1320 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1321 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1322 "cmovo\t{$src2, $dst|$dst, $src2}",
1323 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1324 X86_COND_O, EFLAGS))]>,
1326 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1327 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1328 "cmovno\t{$src2, $dst|$dst, $src2}",
1329 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1330 X86_COND_NO, EFLAGS))]>,
1332 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1333 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1334 "cmovno\t{$src2, $dst|$dst, $src2}",
1335 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1336 X86_COND_NO, EFLAGS))]>,
1338 } // isCommutable = 1
1340 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1341 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1342 "cmovb\t{$src2, $dst|$dst, $src2}",
1343 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1344 X86_COND_B, EFLAGS))]>,
1346 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1347 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1348 "cmovb\t{$src2, $dst|$dst, $src2}",
1349 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1350 X86_COND_B, EFLAGS))]>,
1352 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1353 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1354 "cmovae\t{$src2, $dst|$dst, $src2}",
1355 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1356 X86_COND_AE, EFLAGS))]>,
1358 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1359 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1360 "cmovae\t{$src2, $dst|$dst, $src2}",
1361 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1362 X86_COND_AE, EFLAGS))]>,
1364 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1365 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1366 "cmove\t{$src2, $dst|$dst, $src2}",
1367 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1368 X86_COND_E, EFLAGS))]>,
1370 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1371 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1372 "cmove\t{$src2, $dst|$dst, $src2}",
1373 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1374 X86_COND_E, EFLAGS))]>,
1376 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1377 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1378 "cmovne\t{$src2, $dst|$dst, $src2}",
1379 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1380 X86_COND_NE, EFLAGS))]>,
1382 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1383 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1384 "cmovne\t{$src2, $dst|$dst, $src2}",
1385 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1386 X86_COND_NE, EFLAGS))]>,
1388 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1389 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1390 "cmovbe\t{$src2, $dst|$dst, $src2}",
1391 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1392 X86_COND_BE, EFLAGS))]>,
1394 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1395 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1396 "cmovbe\t{$src2, $dst|$dst, $src2}",
1397 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1398 X86_COND_BE, EFLAGS))]>,
1400 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1401 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1402 "cmova\t{$src2, $dst|$dst, $src2}",
1403 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1404 X86_COND_A, EFLAGS))]>,
1406 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1407 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1408 "cmova\t{$src2, $dst|$dst, $src2}",
1409 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1410 X86_COND_A, EFLAGS))]>,
1412 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1413 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1414 "cmovl\t{$src2, $dst|$dst, $src2}",
1415 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1416 X86_COND_L, EFLAGS))]>,
1418 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1419 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1420 "cmovl\t{$src2, $dst|$dst, $src2}",
1421 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1422 X86_COND_L, EFLAGS))]>,
1424 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1425 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1426 "cmovge\t{$src2, $dst|$dst, $src2}",
1427 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1428 X86_COND_GE, EFLAGS))]>,
1430 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1431 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1432 "cmovge\t{$src2, $dst|$dst, $src2}",
1433 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1434 X86_COND_GE, EFLAGS))]>,
1436 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1437 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1438 "cmovle\t{$src2, $dst|$dst, $src2}",
1439 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1440 X86_COND_LE, EFLAGS))]>,
1442 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1443 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1444 "cmovle\t{$src2, $dst|$dst, $src2}",
1445 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1446 X86_COND_LE, EFLAGS))]>,
1448 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1449 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1450 "cmovg\t{$src2, $dst|$dst, $src2}",
1451 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1452 X86_COND_G, EFLAGS))]>,
1454 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1455 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1456 "cmovg\t{$src2, $dst|$dst, $src2}",
1457 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1458 X86_COND_G, EFLAGS))]>,
1460 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1461 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1462 "cmovs\t{$src2, $dst|$dst, $src2}",
1463 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1464 X86_COND_S, EFLAGS))]>,
1466 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1467 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1468 "cmovs\t{$src2, $dst|$dst, $src2}",
1469 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1470 X86_COND_S, EFLAGS))]>,
1472 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1473 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1474 "cmovns\t{$src2, $dst|$dst, $src2}",
1475 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1476 X86_COND_NS, EFLAGS))]>,
1478 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1479 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1480 "cmovns\t{$src2, $dst|$dst, $src2}",
1481 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1482 X86_COND_NS, EFLAGS))]>,
1484 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1485 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1486 "cmovp\t{$src2, $dst|$dst, $src2}",
1487 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1488 X86_COND_P, EFLAGS))]>,
1490 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1491 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1492 "cmovp\t{$src2, $dst|$dst, $src2}",
1493 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1494 X86_COND_P, EFLAGS))]>,
1496 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1497 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1498 "cmovnp\t{$src2, $dst|$dst, $src2}",
1499 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1500 X86_COND_NP, EFLAGS))]>,
1502 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1503 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1504 "cmovnp\t{$src2, $dst|$dst, $src2}",
1505 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1506 X86_COND_NP, EFLAGS))]>,
1508 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1509 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1510 "cmovo\t{$src2, $dst|$dst, $src2}",
1511 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1512 X86_COND_O, EFLAGS))]>,
1514 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1515 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1516 "cmovo\t{$src2, $dst|$dst, $src2}",
1517 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1518 X86_COND_O, EFLAGS))]>,
1520 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1521 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1522 "cmovno\t{$src2, $dst|$dst, $src2}",
1523 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1524 X86_COND_NO, EFLAGS))]>,
1526 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1527 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1528 "cmovno\t{$src2, $dst|$dst, $src2}",
1529 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1530 X86_COND_NO, EFLAGS))]>,
1532 } // Uses = [EFLAGS]
1535 // unary instructions
1536 let CodeSize = 2 in {
1537 let Defs = [EFLAGS] in {
1538 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1539 [(set GR8:$dst, (ineg GR8:$src)),
1540 (implicit EFLAGS)]>;
1541 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1542 [(set GR16:$dst, (ineg GR16:$src)),
1543 (implicit EFLAGS)]>, OpSize;
1544 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1545 [(set GR32:$dst, (ineg GR32:$src)),
1546 (implicit EFLAGS)]>;
1547 let isTwoAddress = 0 in {
1548 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1549 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1550 (implicit EFLAGS)]>;
1551 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1552 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1553 (implicit EFLAGS)]>, OpSize;
1554 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1555 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1556 (implicit EFLAGS)]>;
1558 } // Defs = [EFLAGS]
1560 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1561 let AddedComplexity = 15 in {
1562 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1563 [(set GR8:$dst, (not GR8:$src))]>;
1564 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1565 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1566 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1567 [(set GR32:$dst, (not GR32:$src))]>;
1569 let isTwoAddress = 0 in {
1570 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1571 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1572 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1573 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1574 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1575 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1579 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1580 let Defs = [EFLAGS] in {
1582 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1583 [(set GR8:$dst, (add GR8:$src, 1)),
1584 (implicit EFLAGS)]>;
1585 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1586 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1587 [(set GR16:$dst, (add GR16:$src, 1)),
1588 (implicit EFLAGS)]>,
1589 OpSize, Requires<[In32BitMode]>;
1590 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1591 [(set GR32:$dst, (add GR32:$src, 1)),
1592 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1594 let isTwoAddress = 0, CodeSize = 2 in {
1595 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1596 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1597 (implicit EFLAGS)]>;
1598 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1599 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1600 (implicit EFLAGS)]>,
1601 OpSize, Requires<[In32BitMode]>;
1602 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1603 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1604 (implicit EFLAGS)]>,
1605 Requires<[In32BitMode]>;
1609 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1610 [(set GR8:$dst, (add GR8:$src, -1)),
1611 (implicit EFLAGS)]>;
1612 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1613 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1614 [(set GR16:$dst, (add GR16:$src, -1)),
1615 (implicit EFLAGS)]>,
1616 OpSize, Requires<[In32BitMode]>;
1617 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1618 [(set GR32:$dst, (add GR32:$src, -1)),
1619 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1622 let isTwoAddress = 0, CodeSize = 2 in {
1623 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1624 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1625 (implicit EFLAGS)]>;
1626 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1627 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1628 (implicit EFLAGS)]>,
1629 OpSize, Requires<[In32BitMode]>;
1630 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1631 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1632 (implicit EFLAGS)]>,
1633 Requires<[In32BitMode]>;
1635 } // Defs = [EFLAGS]
1637 // Logical operators...
1638 let Defs = [EFLAGS] in {
1639 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1640 def AND8rr : I<0x20, MRMDestReg,
1641 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1642 "and{b}\t{$src2, $dst|$dst, $src2}",
1643 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1644 (implicit EFLAGS)]>;
1645 def AND16rr : I<0x21, MRMDestReg,
1646 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1647 "and{w}\t{$src2, $dst|$dst, $src2}",
1648 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1649 (implicit EFLAGS)]>, OpSize;
1650 def AND32rr : I<0x21, MRMDestReg,
1651 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1652 "and{l}\t{$src2, $dst|$dst, $src2}",
1653 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1654 (implicit EFLAGS)]>;
1657 def AND8rm : I<0x22, MRMSrcMem,
1658 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1659 "and{b}\t{$src2, $dst|$dst, $src2}",
1660 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1661 (implicit EFLAGS)]>;
1662 def AND16rm : I<0x23, MRMSrcMem,
1663 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1664 "and{w}\t{$src2, $dst|$dst, $src2}",
1665 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1666 (implicit EFLAGS)]>, OpSize;
1667 def AND32rm : I<0x23, MRMSrcMem,
1668 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1669 "and{l}\t{$src2, $dst|$dst, $src2}",
1670 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1671 (implicit EFLAGS)]>;
1673 def AND8ri : Ii8<0x80, MRM4r,
1674 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1675 "and{b}\t{$src2, $dst|$dst, $src2}",
1676 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1677 (implicit EFLAGS)]>;
1678 def AND16ri : Ii16<0x81, MRM4r,
1679 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1680 "and{w}\t{$src2, $dst|$dst, $src2}",
1681 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1682 (implicit EFLAGS)]>, OpSize;
1683 def AND32ri : Ii32<0x81, MRM4r,
1684 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1685 "and{l}\t{$src2, $dst|$dst, $src2}",
1686 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1687 (implicit EFLAGS)]>;
1688 def AND16ri8 : Ii8<0x83, MRM4r,
1689 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1690 "and{w}\t{$src2, $dst|$dst, $src2}",
1691 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1692 (implicit EFLAGS)]>,
1694 def AND32ri8 : Ii8<0x83, MRM4r,
1695 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1696 "and{l}\t{$src2, $dst|$dst, $src2}",
1697 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1698 (implicit EFLAGS)]>;
1700 let isTwoAddress = 0 in {
1701 def AND8mr : I<0x20, MRMDestMem,
1702 (outs), (ins i8mem :$dst, GR8 :$src),
1703 "and{b}\t{$src, $dst|$dst, $src}",
1704 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1705 (implicit EFLAGS)]>;
1706 def AND16mr : I<0x21, MRMDestMem,
1707 (outs), (ins i16mem:$dst, GR16:$src),
1708 "and{w}\t{$src, $dst|$dst, $src}",
1709 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1710 (implicit EFLAGS)]>,
1712 def AND32mr : I<0x21, MRMDestMem,
1713 (outs), (ins i32mem:$dst, GR32:$src),
1714 "and{l}\t{$src, $dst|$dst, $src}",
1715 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1716 (implicit EFLAGS)]>;
1717 def AND8mi : Ii8<0x80, MRM4m,
1718 (outs), (ins i8mem :$dst, i8imm :$src),
1719 "and{b}\t{$src, $dst|$dst, $src}",
1720 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1721 (implicit EFLAGS)]>;
1722 def AND16mi : Ii16<0x81, MRM4m,
1723 (outs), (ins i16mem:$dst, i16imm:$src),
1724 "and{w}\t{$src, $dst|$dst, $src}",
1725 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1726 (implicit EFLAGS)]>,
1728 def AND32mi : Ii32<0x81, MRM4m,
1729 (outs), (ins i32mem:$dst, i32imm:$src),
1730 "and{l}\t{$src, $dst|$dst, $src}",
1731 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1732 (implicit EFLAGS)]>;
1733 def AND16mi8 : Ii8<0x83, MRM4m,
1734 (outs), (ins i16mem:$dst, i16i8imm :$src),
1735 "and{w}\t{$src, $dst|$dst, $src}",
1736 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1737 (implicit EFLAGS)]>,
1739 def AND32mi8 : Ii8<0x83, MRM4m,
1740 (outs), (ins i32mem:$dst, i32i8imm :$src),
1741 "and{l}\t{$src, $dst|$dst, $src}",
1742 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1743 (implicit EFLAGS)]>;
1745 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1746 "and{b}\t{$src, %al|%al, $src}", []>;
1747 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1748 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1749 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1750 "and{l}\t{$src, %eax|%eax, $src}", []>;
1755 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1756 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1757 "or{b}\t{$src2, $dst|$dst, $src2}",
1758 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1759 (implicit EFLAGS)]>;
1760 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1761 "or{w}\t{$src2, $dst|$dst, $src2}",
1762 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1763 (implicit EFLAGS)]>, OpSize;
1764 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1765 "or{l}\t{$src2, $dst|$dst, $src2}",
1766 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1767 (implicit EFLAGS)]>;
1769 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1770 "or{b}\t{$src2, $dst|$dst, $src2}",
1771 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1772 (implicit EFLAGS)]>;
1773 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1774 "or{w}\t{$src2, $dst|$dst, $src2}",
1775 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1776 (implicit EFLAGS)]>, OpSize;
1777 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1778 "or{l}\t{$src2, $dst|$dst, $src2}",
1779 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1780 (implicit EFLAGS)]>;
1782 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1783 "or{b}\t{$src2, $dst|$dst, $src2}",
1784 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1785 (implicit EFLAGS)]>;
1786 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1787 "or{w}\t{$src2, $dst|$dst, $src2}",
1788 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1789 (implicit EFLAGS)]>, OpSize;
1790 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1791 "or{l}\t{$src2, $dst|$dst, $src2}",
1792 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1793 (implicit EFLAGS)]>;
1795 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1796 "or{w}\t{$src2, $dst|$dst, $src2}",
1797 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1798 (implicit EFLAGS)]>, OpSize;
1799 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1800 "or{l}\t{$src2, $dst|$dst, $src2}",
1801 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1802 (implicit EFLAGS)]>;
1803 let isTwoAddress = 0 in {
1804 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1805 "or{b}\t{$src, $dst|$dst, $src}",
1806 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1807 (implicit EFLAGS)]>;
1808 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1809 "or{w}\t{$src, $dst|$dst, $src}",
1810 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1811 (implicit EFLAGS)]>, OpSize;
1812 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1813 "or{l}\t{$src, $dst|$dst, $src}",
1814 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1815 (implicit EFLAGS)]>;
1816 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1817 "or{b}\t{$src, $dst|$dst, $src}",
1818 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1819 (implicit EFLAGS)]>;
1820 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1821 "or{w}\t{$src, $dst|$dst, $src}",
1822 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1823 (implicit EFLAGS)]>,
1825 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1826 "or{l}\t{$src, $dst|$dst, $src}",
1827 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1828 (implicit EFLAGS)]>;
1829 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1830 "or{w}\t{$src, $dst|$dst, $src}",
1831 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1832 (implicit EFLAGS)]>,
1834 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1835 "or{l}\t{$src, $dst|$dst, $src}",
1836 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1837 (implicit EFLAGS)]>;
1839 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1840 "or{b}\t{$src, %al|%al, $src}", []>;
1841 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1842 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1843 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1844 "or{l}\t{$src, %eax|%eax, $src}", []>;
1845 } // isTwoAddress = 0
1848 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1849 def XOR8rr : I<0x30, MRMDestReg,
1850 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1851 "xor{b}\t{$src2, $dst|$dst, $src2}",
1852 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1853 (implicit EFLAGS)]>;
1854 def XOR16rr : I<0x31, MRMDestReg,
1855 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1856 "xor{w}\t{$src2, $dst|$dst, $src2}",
1857 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1858 (implicit EFLAGS)]>, OpSize;
1859 def XOR32rr : I<0x31, MRMDestReg,
1860 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1861 "xor{l}\t{$src2, $dst|$dst, $src2}",
1862 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1863 (implicit EFLAGS)]>;
1864 } // isCommutable = 1
1866 def XOR8rm : I<0x32, MRMSrcMem ,
1867 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1868 "xor{b}\t{$src2, $dst|$dst, $src2}",
1869 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1870 (implicit EFLAGS)]>;
1871 def XOR16rm : I<0x33, MRMSrcMem ,
1872 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1873 "xor{w}\t{$src2, $dst|$dst, $src2}",
1874 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1875 (implicit EFLAGS)]>,
1877 def XOR32rm : I<0x33, MRMSrcMem ,
1878 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1879 "xor{l}\t{$src2, $dst|$dst, $src2}",
1880 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1881 (implicit EFLAGS)]>;
1883 def XOR8ri : Ii8<0x80, MRM6r,
1884 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1885 "xor{b}\t{$src2, $dst|$dst, $src2}",
1886 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1887 (implicit EFLAGS)]>;
1888 def XOR16ri : Ii16<0x81, MRM6r,
1889 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1890 "xor{w}\t{$src2, $dst|$dst, $src2}",
1891 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
1892 (implicit EFLAGS)]>, OpSize;
1893 def XOR32ri : Ii32<0x81, MRM6r,
1894 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1895 "xor{l}\t{$src2, $dst|$dst, $src2}",
1896 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
1897 (implicit EFLAGS)]>;
1898 def XOR16ri8 : Ii8<0x83, MRM6r,
1899 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1900 "xor{w}\t{$src2, $dst|$dst, $src2}",
1901 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
1902 (implicit EFLAGS)]>,
1904 def XOR32ri8 : Ii8<0x83, MRM6r,
1905 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1906 "xor{l}\t{$src2, $dst|$dst, $src2}",
1907 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
1908 (implicit EFLAGS)]>;
1910 let isTwoAddress = 0 in {
1911 def XOR8mr : I<0x30, MRMDestMem,
1912 (outs), (ins i8mem :$dst, GR8 :$src),
1913 "xor{b}\t{$src, $dst|$dst, $src}",
1914 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1915 (implicit EFLAGS)]>;
1916 def XOR16mr : I<0x31, MRMDestMem,
1917 (outs), (ins i16mem:$dst, GR16:$src),
1918 "xor{w}\t{$src, $dst|$dst, $src}",
1919 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1920 (implicit EFLAGS)]>,
1922 def XOR32mr : I<0x31, MRMDestMem,
1923 (outs), (ins i32mem:$dst, GR32:$src),
1924 "xor{l}\t{$src, $dst|$dst, $src}",
1925 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1926 (implicit EFLAGS)]>;
1927 def XOR8mi : Ii8<0x80, MRM6m,
1928 (outs), (ins i8mem :$dst, i8imm :$src),
1929 "xor{b}\t{$src, $dst|$dst, $src}",
1930 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1931 (implicit EFLAGS)]>;
1932 def XOR16mi : Ii16<0x81, MRM6m,
1933 (outs), (ins i16mem:$dst, i16imm:$src),
1934 "xor{w}\t{$src, $dst|$dst, $src}",
1935 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1936 (implicit EFLAGS)]>,
1938 def XOR32mi : Ii32<0x81, MRM6m,
1939 (outs), (ins i32mem:$dst, i32imm:$src),
1940 "xor{l}\t{$src, $dst|$dst, $src}",
1941 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1942 (implicit EFLAGS)]>;
1943 def XOR16mi8 : Ii8<0x83, MRM6m,
1944 (outs), (ins i16mem:$dst, i16i8imm :$src),
1945 "xor{w}\t{$src, $dst|$dst, $src}",
1946 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1947 (implicit EFLAGS)]>,
1949 def XOR32mi8 : Ii8<0x83, MRM6m,
1950 (outs), (ins i32mem:$dst, i32i8imm :$src),
1951 "xor{l}\t{$src, $dst|$dst, $src}",
1952 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1953 (implicit EFLAGS)]>;
1955 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
1956 "xor{b}\t{$src, %al|%al, $src}", []>;
1957 def XOR16i16 : Ii16 <0x35, RawFrm, (outs), (ins i16imm:$src),
1958 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1959 def XOR32i32 : Ii32 <0x35, RawFrm, (outs), (ins i32imm:$src),
1960 "xor{l}\t{$src, %eax|%eax, $src}", []>;
1961 } // isTwoAddress = 0
1962 } // Defs = [EFLAGS]
1964 // Shift instructions
1965 let Defs = [EFLAGS] in {
1966 let Uses = [CL] in {
1967 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1968 "shl{b}\t{%cl, $dst|$dst, CL}",
1969 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1970 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1971 "shl{w}\t{%cl, $dst|$dst, CL}",
1972 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1973 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1974 "shl{l}\t{%cl, $dst|$dst, CL}",
1975 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1978 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1979 "shl{b}\t{$src2, $dst|$dst, $src2}",
1980 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1981 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1982 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1983 "shl{w}\t{$src2, $dst|$dst, $src2}",
1984 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1985 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1986 "shl{l}\t{$src2, $dst|$dst, $src2}",
1987 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1989 // NOTE: We don't include patterns for shifts of a register by one, because
1990 // 'add reg,reg' is cheaper.
1992 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
1993 "shl{b}\t$dst", []>;
1994 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
1995 "shl{w}\t$dst", []>, OpSize;
1996 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
1997 "shl{l}\t$dst", []>;
1999 } // isConvertibleToThreeAddress = 1
2001 let isTwoAddress = 0 in {
2002 let Uses = [CL] in {
2003 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2004 "shl{b}\t{%cl, $dst|$dst, CL}",
2005 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2006 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2007 "shl{w}\t{%cl, $dst|$dst, CL}",
2008 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2009 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2010 "shl{l}\t{%cl, $dst|$dst, CL}",
2011 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2013 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2014 "shl{b}\t{$src, $dst|$dst, $src}",
2015 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2016 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2017 "shl{w}\t{$src, $dst|$dst, $src}",
2018 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2020 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2021 "shl{l}\t{$src, $dst|$dst, $src}",
2022 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2025 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2027 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2028 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2030 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2032 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2034 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2037 let Uses = [CL] in {
2038 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2039 "shr{b}\t{%cl, $dst|$dst, CL}",
2040 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2041 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2042 "shr{w}\t{%cl, $dst|$dst, CL}",
2043 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2044 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2045 "shr{l}\t{%cl, $dst|$dst, CL}",
2046 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2049 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2050 "shr{b}\t{$src2, $dst|$dst, $src2}",
2051 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2052 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2053 "shr{w}\t{$src2, $dst|$dst, $src2}",
2054 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2055 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2056 "shr{l}\t{$src2, $dst|$dst, $src2}",
2057 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2060 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2062 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2063 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2065 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2066 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2068 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2070 let isTwoAddress = 0 in {
2071 let Uses = [CL] in {
2072 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2073 "shr{b}\t{%cl, $dst|$dst, CL}",
2074 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2075 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2076 "shr{w}\t{%cl, $dst|$dst, CL}",
2077 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2079 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2080 "shr{l}\t{%cl, $dst|$dst, CL}",
2081 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2083 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2084 "shr{b}\t{$src, $dst|$dst, $src}",
2085 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2086 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2087 "shr{w}\t{$src, $dst|$dst, $src}",
2088 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2090 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2091 "shr{l}\t{$src, $dst|$dst, $src}",
2092 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2095 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2097 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2098 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2100 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2101 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2103 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2106 let Uses = [CL] in {
2107 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2108 "sar{b}\t{%cl, $dst|$dst, CL}",
2109 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2110 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2111 "sar{w}\t{%cl, $dst|$dst, CL}",
2112 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2113 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2114 "sar{l}\t{%cl, $dst|$dst, CL}",
2115 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2118 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2119 "sar{b}\t{$src2, $dst|$dst, $src2}",
2120 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2121 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2122 "sar{w}\t{$src2, $dst|$dst, $src2}",
2123 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2125 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2126 "sar{l}\t{$src2, $dst|$dst, $src2}",
2127 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2130 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2132 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2133 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2135 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2136 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2138 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2140 let isTwoAddress = 0 in {
2141 let Uses = [CL] in {
2142 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2143 "sar{b}\t{%cl, $dst|$dst, CL}",
2144 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2145 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2146 "sar{w}\t{%cl, $dst|$dst, CL}",
2147 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2148 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2149 "sar{l}\t{%cl, $dst|$dst, CL}",
2150 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2152 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2153 "sar{b}\t{$src, $dst|$dst, $src}",
2154 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2155 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2156 "sar{w}\t{$src, $dst|$dst, $src}",
2157 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2159 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2160 "sar{l}\t{$src, $dst|$dst, $src}",
2161 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2164 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2166 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2167 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2169 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2171 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2173 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2176 // Rotate instructions
2178 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2179 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2180 def RCL8m1 : I<0xD0, MRM2m, (outs i8mem:$dst), (ins i8mem:$src),
2181 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2182 let Uses = [CL] in {
2183 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2184 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2185 def RCL8mCL : I<0xD2, MRM2m, (outs i8mem:$dst), (ins i8mem:$src),
2186 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2188 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2189 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2190 def RCL8mi : Ii8<0xC0, MRM2m, (outs i8mem:$dst), (ins i8mem:$src, i8imm:$cnt),
2191 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2193 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2194 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2195 def RCL16m1 : I<0xD1, MRM2m, (outs i16mem:$dst), (ins i16mem:$src),
2196 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2197 let Uses = [CL] in {
2198 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2199 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2200 def RCL16mCL : I<0xD3, MRM2m, (outs i16mem:$dst), (ins i16mem:$src),
2201 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2203 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2204 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2205 def RCL16mi : Ii8<0xC1, MRM2m, (outs i16mem:$dst), (ins i16mem:$src, i8imm:$cnt),
2206 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2208 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2209 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2210 def RCL32m1 : I<0xD1, MRM2m, (outs i32mem:$dst), (ins i32mem:$src),
2211 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2212 let Uses = [CL] in {
2213 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2214 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2215 def RCL32mCL : I<0xD3, MRM2m, (outs i32mem:$dst), (ins i32mem:$src),
2216 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2218 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2219 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2220 def RCL32mi : Ii8<0xC1, MRM2m, (outs i32mem:$dst), (ins i32mem:$src, i8imm:$cnt),
2221 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2223 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2224 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2225 def RCR8m1 : I<0xD0, MRM3m, (outs i8mem:$dst), (ins i8mem:$src),
2226 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2227 let Uses = [CL] in {
2228 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2229 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2230 def RCR8mCL : I<0xD2, MRM3m, (outs i8mem:$dst), (ins i8mem:$src),
2231 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2233 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2234 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2235 def RCR8mi : Ii8<0xC0, MRM3m, (outs i8mem:$dst), (ins i8mem:$src, i8imm:$cnt),
2236 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2238 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2239 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2240 def RCR16m1 : I<0xD1, MRM3m, (outs i16mem:$dst), (ins i16mem:$src),
2241 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2242 let Uses = [CL] in {
2243 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2244 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2245 def RCR16mCL : I<0xD3, MRM3m, (outs i16mem:$dst), (ins i16mem:$src),
2246 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2248 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2249 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2250 def RCR16mi : Ii8<0xC1, MRM3m, (outs i16mem:$dst), (ins i16mem:$src, i8imm:$cnt),
2251 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2253 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2254 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2255 def RCR32m1 : I<0xD1, MRM3m, (outs i32mem:$dst), (ins i32mem:$src),
2256 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2257 let Uses = [CL] in {
2258 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2259 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2260 def RCR32mCL : I<0xD3, MRM3m, (outs i32mem:$dst), (ins i32mem:$src),
2261 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2263 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2264 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2265 def RCR32mi : Ii8<0xC1, MRM3m, (outs i32mem:$dst), (ins i32mem:$src, i8imm:$cnt),
2266 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2268 // FIXME: provide shorter instructions when imm8 == 1
2269 let Uses = [CL] in {
2270 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2271 "rol{b}\t{%cl, $dst|$dst, CL}",
2272 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2273 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2274 "rol{w}\t{%cl, $dst|$dst, CL}",
2275 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2276 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2277 "rol{l}\t{%cl, $dst|$dst, CL}",
2278 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2281 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2282 "rol{b}\t{$src2, $dst|$dst, $src2}",
2283 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2284 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2285 "rol{w}\t{$src2, $dst|$dst, $src2}",
2286 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2287 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2288 "rol{l}\t{$src2, $dst|$dst, $src2}",
2289 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2292 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2294 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2295 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2297 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2298 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2300 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2302 let isTwoAddress = 0 in {
2303 let Uses = [CL] in {
2304 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2305 "rol{b}\t{%cl, $dst|$dst, CL}",
2306 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2307 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2308 "rol{w}\t{%cl, $dst|$dst, CL}",
2309 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2310 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2311 "rol{l}\t{%cl, $dst|$dst, CL}",
2312 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2314 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2315 "rol{b}\t{$src, $dst|$dst, $src}",
2316 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2317 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2318 "rol{w}\t{$src, $dst|$dst, $src}",
2319 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2321 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2322 "rol{l}\t{$src, $dst|$dst, $src}",
2323 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2326 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2328 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2329 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2331 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2333 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2335 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2338 let Uses = [CL] in {
2339 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2340 "ror{b}\t{%cl, $dst|$dst, CL}",
2341 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2342 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2343 "ror{w}\t{%cl, $dst|$dst, CL}",
2344 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2345 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2346 "ror{l}\t{%cl, $dst|$dst, CL}",
2347 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2350 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2351 "ror{b}\t{$src2, $dst|$dst, $src2}",
2352 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2353 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2354 "ror{w}\t{$src2, $dst|$dst, $src2}",
2355 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2356 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2357 "ror{l}\t{$src2, $dst|$dst, $src2}",
2358 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2361 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2363 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2364 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2366 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2367 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2369 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2371 let isTwoAddress = 0 in {
2372 let Uses = [CL] in {
2373 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2374 "ror{b}\t{%cl, $dst|$dst, CL}",
2375 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2376 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2377 "ror{w}\t{%cl, $dst|$dst, CL}",
2378 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2379 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2380 "ror{l}\t{%cl, $dst|$dst, CL}",
2381 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2383 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2384 "ror{b}\t{$src, $dst|$dst, $src}",
2385 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2386 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2387 "ror{w}\t{$src, $dst|$dst, $src}",
2388 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2390 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2391 "ror{l}\t{$src, $dst|$dst, $src}",
2392 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2395 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2397 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2398 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2400 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2402 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2404 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2409 // Double shift instructions (generalizations of rotate)
2410 let Uses = [CL] in {
2411 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2412 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2413 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2414 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2415 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2416 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2417 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2418 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2419 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2421 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2422 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2423 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2427 let isCommutable = 1 in { // These instructions commute to each other.
2428 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2429 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2430 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2431 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2434 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2435 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2436 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2437 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2440 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2441 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2442 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2443 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2446 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2447 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2448 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2449 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2454 let isTwoAddress = 0 in {
2455 let Uses = [CL] in {
2456 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2457 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2458 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2460 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2461 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2462 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2465 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2466 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2467 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2468 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2469 (i8 imm:$src3)), addr:$dst)]>,
2471 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2472 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2473 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2474 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2475 (i8 imm:$src3)), addr:$dst)]>,
2478 let Uses = [CL] in {
2479 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2480 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2481 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2482 addr:$dst)]>, TB, OpSize;
2483 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2484 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2485 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2486 addr:$dst)]>, TB, OpSize;
2488 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2489 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2490 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2491 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2492 (i8 imm:$src3)), addr:$dst)]>,
2494 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2495 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2496 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2497 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2498 (i8 imm:$src3)), addr:$dst)]>,
2501 } // Defs = [EFLAGS]
2505 let Defs = [EFLAGS] in {
2506 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2507 // Register-Register Addition
2508 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2509 (ins GR8 :$src1, GR8 :$src2),
2510 "add{b}\t{$src2, $dst|$dst, $src2}",
2511 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2512 (implicit EFLAGS)]>;
2514 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2515 // Register-Register Addition
2516 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2517 (ins GR16:$src1, GR16:$src2),
2518 "add{w}\t{$src2, $dst|$dst, $src2}",
2519 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2520 (implicit EFLAGS)]>, OpSize;
2521 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2522 (ins GR32:$src1, GR32:$src2),
2523 "add{l}\t{$src2, $dst|$dst, $src2}",
2524 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2525 (implicit EFLAGS)]>;
2526 } // end isConvertibleToThreeAddress
2527 } // end isCommutable
2529 // Register-Memory Addition
2530 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2531 (ins GR8 :$src1, i8mem :$src2),
2532 "add{b}\t{$src2, $dst|$dst, $src2}",
2533 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2534 (implicit EFLAGS)]>;
2535 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2536 (ins GR16:$src1, i16mem:$src2),
2537 "add{w}\t{$src2, $dst|$dst, $src2}",
2538 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2539 (implicit EFLAGS)]>, OpSize;
2540 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2541 (ins GR32:$src1, i32mem:$src2),
2542 "add{l}\t{$src2, $dst|$dst, $src2}",
2543 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2544 (implicit EFLAGS)]>;
2546 // Register-Register Addition - Equivalent to the normal rr forms (ADD8rr,
2547 // ADD16rr, and ADD32rr), but differently encoded.
2548 def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2549 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2550 def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2551 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2552 def ADD32mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2553 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2555 // Register-Integer Addition
2556 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2557 "add{b}\t{$src2, $dst|$dst, $src2}",
2558 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2559 (implicit EFLAGS)]>;
2561 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2562 // Register-Integer Addition
2563 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2564 (ins GR16:$src1, i16imm:$src2),
2565 "add{w}\t{$src2, $dst|$dst, $src2}",
2566 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2567 (implicit EFLAGS)]>, OpSize;
2568 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2569 (ins GR32:$src1, i32imm:$src2),
2570 "add{l}\t{$src2, $dst|$dst, $src2}",
2571 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2572 (implicit EFLAGS)]>;
2573 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2574 (ins GR16:$src1, i16i8imm:$src2),
2575 "add{w}\t{$src2, $dst|$dst, $src2}",
2576 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2577 (implicit EFLAGS)]>, OpSize;
2578 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2579 (ins GR32:$src1, i32i8imm:$src2),
2580 "add{l}\t{$src2, $dst|$dst, $src2}",
2581 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2582 (implicit EFLAGS)]>;
2585 let isTwoAddress = 0 in {
2586 // Memory-Register Addition
2587 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2588 "add{b}\t{$src2, $dst|$dst, $src2}",
2589 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2590 (implicit EFLAGS)]>;
2591 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2592 "add{w}\t{$src2, $dst|$dst, $src2}",
2593 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2594 (implicit EFLAGS)]>, OpSize;
2595 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2596 "add{l}\t{$src2, $dst|$dst, $src2}",
2597 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2598 (implicit EFLAGS)]>;
2599 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2600 "add{b}\t{$src2, $dst|$dst, $src2}",
2601 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2602 (implicit EFLAGS)]>;
2603 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2604 "add{w}\t{$src2, $dst|$dst, $src2}",
2605 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2606 (implicit EFLAGS)]>, OpSize;
2607 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2608 "add{l}\t{$src2, $dst|$dst, $src2}",
2609 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2610 (implicit EFLAGS)]>;
2611 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2612 "add{w}\t{$src2, $dst|$dst, $src2}",
2613 [(store (add (load addr:$dst), i16immSExt8:$src2),
2615 (implicit EFLAGS)]>, OpSize;
2616 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2617 "add{l}\t{$src2, $dst|$dst, $src2}",
2618 [(store (add (load addr:$dst), i32immSExt8:$src2),
2620 (implicit EFLAGS)]>;
2623 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2624 "add{b}\t{$src, %al|%al, $src}", []>;
2625 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2626 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2627 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2628 "add{l}\t{$src, %eax|%eax, $src}", []>;
2631 let Uses = [EFLAGS] in {
2632 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2633 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2634 "adc{b}\t{$src2, $dst|$dst, $src2}",
2635 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2636 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2637 (ins GR16:$src1, GR16:$src2),
2638 "adc{w}\t{$src2, $dst|$dst, $src2}",
2639 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2640 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2641 (ins GR32:$src1, GR32:$src2),
2642 "adc{l}\t{$src2, $dst|$dst, $src2}",
2643 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2645 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2646 (ins GR8:$src1, i8mem:$src2),
2647 "adc{b}\t{$src2, $dst|$dst, $src2}",
2648 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2649 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2650 (ins GR16:$src1, i16mem:$src2),
2651 "adc{w}\t{$src2, $dst|$dst, $src2}",
2652 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2654 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2655 (ins GR32:$src1, i32mem:$src2),
2656 "adc{l}\t{$src2, $dst|$dst, $src2}",
2657 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2658 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2659 "adc{b}\t{$src2, $dst|$dst, $src2}",
2660 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2661 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2662 (ins GR16:$src1, i16imm:$src2),
2663 "adc{w}\t{$src2, $dst|$dst, $src2}",
2664 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2665 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2666 (ins GR16:$src1, i16i8imm:$src2),
2667 "adc{w}\t{$src2, $dst|$dst, $src2}",
2668 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2670 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2671 (ins GR32:$src1, i32imm:$src2),
2672 "adc{l}\t{$src2, $dst|$dst, $src2}",
2673 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2674 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2675 (ins GR32:$src1, i32i8imm:$src2),
2676 "adc{l}\t{$src2, $dst|$dst, $src2}",
2677 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2679 let isTwoAddress = 0 in {
2680 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2681 "adc{b}\t{$src2, $dst|$dst, $src2}",
2682 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2683 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2684 "adc{w}\t{$src2, $dst|$dst, $src2}",
2685 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2687 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2688 "adc{l}\t{$src2, $dst|$dst, $src2}",
2689 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2690 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2691 "adc{b}\t{$src2, $dst|$dst, $src2}",
2692 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2693 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2694 "adc{w}\t{$src2, $dst|$dst, $src2}",
2695 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2697 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2698 "adc{w}\t{$src2, $dst|$dst, $src2}",
2699 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2701 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2702 "adc{l}\t{$src2, $dst|$dst, $src2}",
2703 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2704 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2705 "adc{l}\t{$src2, $dst|$dst, $src2}",
2706 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2708 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2709 "adc{b}\t{$src, %al|%al, $src}", []>;
2710 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2711 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2712 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2713 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2715 } // Uses = [EFLAGS]
2717 // Register-Register Subtraction
2718 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2719 "sub{b}\t{$src2, $dst|$dst, $src2}",
2720 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2721 (implicit EFLAGS)]>;
2722 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2723 "sub{w}\t{$src2, $dst|$dst, $src2}",
2724 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2725 (implicit EFLAGS)]>, OpSize;
2726 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2727 "sub{l}\t{$src2, $dst|$dst, $src2}",
2728 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2729 (implicit EFLAGS)]>;
2731 // Register-Memory Subtraction
2732 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2733 (ins GR8 :$src1, i8mem :$src2),
2734 "sub{b}\t{$src2, $dst|$dst, $src2}",
2735 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2736 (implicit EFLAGS)]>;
2737 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2738 (ins GR16:$src1, i16mem:$src2),
2739 "sub{w}\t{$src2, $dst|$dst, $src2}",
2740 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2741 (implicit EFLAGS)]>, OpSize;
2742 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2743 (ins GR32:$src1, i32mem:$src2),
2744 "sub{l}\t{$src2, $dst|$dst, $src2}",
2745 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2746 (implicit EFLAGS)]>;
2748 // Register-Integer Subtraction
2749 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2750 (ins GR8:$src1, i8imm:$src2),
2751 "sub{b}\t{$src2, $dst|$dst, $src2}",
2752 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2753 (implicit EFLAGS)]>;
2754 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2755 (ins GR16:$src1, i16imm:$src2),
2756 "sub{w}\t{$src2, $dst|$dst, $src2}",
2757 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2758 (implicit EFLAGS)]>, OpSize;
2759 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2760 (ins GR32:$src1, i32imm:$src2),
2761 "sub{l}\t{$src2, $dst|$dst, $src2}",
2762 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2763 (implicit EFLAGS)]>;
2764 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2765 (ins GR16:$src1, i16i8imm:$src2),
2766 "sub{w}\t{$src2, $dst|$dst, $src2}",
2767 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2768 (implicit EFLAGS)]>, OpSize;
2769 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2770 (ins GR32:$src1, i32i8imm:$src2),
2771 "sub{l}\t{$src2, $dst|$dst, $src2}",
2772 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2773 (implicit EFLAGS)]>;
2775 let isTwoAddress = 0 in {
2776 // Memory-Register Subtraction
2777 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2778 "sub{b}\t{$src2, $dst|$dst, $src2}",
2779 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2780 (implicit EFLAGS)]>;
2781 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2782 "sub{w}\t{$src2, $dst|$dst, $src2}",
2783 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2784 (implicit EFLAGS)]>, OpSize;
2785 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2786 "sub{l}\t{$src2, $dst|$dst, $src2}",
2787 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2788 (implicit EFLAGS)]>;
2790 // Memory-Integer Subtraction
2791 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2792 "sub{b}\t{$src2, $dst|$dst, $src2}",
2793 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2794 (implicit EFLAGS)]>;
2795 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2796 "sub{w}\t{$src2, $dst|$dst, $src2}",
2797 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2798 (implicit EFLAGS)]>, OpSize;
2799 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2800 "sub{l}\t{$src2, $dst|$dst, $src2}",
2801 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2802 (implicit EFLAGS)]>;
2803 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2804 "sub{w}\t{$src2, $dst|$dst, $src2}",
2805 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2807 (implicit EFLAGS)]>, OpSize;
2808 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2809 "sub{l}\t{$src2, $dst|$dst, $src2}",
2810 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2812 (implicit EFLAGS)]>;
2814 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
2815 "sub{b}\t{$src, %al|%al, $src}", []>;
2816 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
2817 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2818 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
2819 "sub{l}\t{$src, %eax|%eax, $src}", []>;
2822 let Uses = [EFLAGS] in {
2823 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2824 (ins GR8:$src1, GR8:$src2),
2825 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2826 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2827 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2828 (ins GR16:$src1, GR16:$src2),
2829 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2830 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2831 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2832 (ins GR32:$src1, GR32:$src2),
2833 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2834 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2836 let isTwoAddress = 0 in {
2837 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2838 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2839 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2840 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2841 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2842 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
2844 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2845 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2846 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2847 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2848 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2849 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2850 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2851 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2852 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2854 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2855 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2856 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2858 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2859 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2860 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2861 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2862 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2863 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2865 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
2866 "sbb{b}\t{$src, %al|%al, $src}", []>;
2867 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
2868 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2869 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
2870 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
2872 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
2873 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2874 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
2875 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
2876 (ins GR16:$src1, i16mem:$src2),
2877 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2878 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
2880 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
2881 (ins GR32:$src1, i32mem:$src2),
2882 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2883 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2884 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2885 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2886 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
2887 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
2888 (ins GR16:$src1, i16imm:$src2),
2889 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2890 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
2891 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
2892 (ins GR16:$src1, i16i8imm:$src2),
2893 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2894 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
2896 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
2897 (ins GR32:$src1, i32imm:$src2),
2898 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2899 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2900 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
2901 (ins GR32:$src1, i32i8imm:$src2),
2902 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2903 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2904 } // Uses = [EFLAGS]
2905 } // Defs = [EFLAGS]
2907 let Defs = [EFLAGS] in {
2908 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2909 // Register-Register Signed Integer Multiply
2910 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2911 "imul{w}\t{$src2, $dst|$dst, $src2}",
2912 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2913 (implicit EFLAGS)]>, TB, OpSize;
2914 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2915 "imul{l}\t{$src2, $dst|$dst, $src2}",
2916 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2917 (implicit EFLAGS)]>, TB;
2920 // Register-Memory Signed Integer Multiply
2921 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2922 (ins GR16:$src1, i16mem:$src2),
2923 "imul{w}\t{$src2, $dst|$dst, $src2}",
2924 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2925 (implicit EFLAGS)]>, TB, OpSize;
2926 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2927 "imul{l}\t{$src2, $dst|$dst, $src2}",
2928 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2929 (implicit EFLAGS)]>, TB;
2930 } // Defs = [EFLAGS]
2931 } // end Two Address instructions
2933 // Suprisingly enough, these are not two address instructions!
2934 let Defs = [EFLAGS] in {
2935 // Register-Integer Signed Integer Multiply
2936 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2937 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2938 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2939 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2940 (implicit EFLAGS)]>, OpSize;
2941 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2942 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2943 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2944 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2945 (implicit EFLAGS)]>;
2946 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2947 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2948 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2949 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2950 (implicit EFLAGS)]>, OpSize;
2951 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2952 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2953 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2954 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2955 (implicit EFLAGS)]>;
2957 // Memory-Integer Signed Integer Multiply
2958 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2959 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2960 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2961 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2962 (implicit EFLAGS)]>, OpSize;
2963 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2964 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2965 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2966 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2967 (implicit EFLAGS)]>;
2968 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2969 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2970 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2971 [(set GR16:$dst, (mul (load addr:$src1),
2972 i16immSExt8:$src2)),
2973 (implicit EFLAGS)]>, OpSize;
2974 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2975 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2976 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2977 [(set GR32:$dst, (mul (load addr:$src1),
2978 i32immSExt8:$src2)),
2979 (implicit EFLAGS)]>;
2980 } // Defs = [EFLAGS]
2982 //===----------------------------------------------------------------------===//
2983 // Test instructions are just like AND, except they don't generate a result.
2985 let Defs = [EFLAGS] in {
2986 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2987 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2988 "test{b}\t{$src2, $src1|$src1, $src2}",
2989 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2990 (implicit EFLAGS)]>;
2991 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2992 "test{w}\t{$src2, $src1|$src1, $src2}",
2993 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2994 (implicit EFLAGS)]>,
2996 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2997 "test{l}\t{$src2, $src1|$src1, $src2}",
2998 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2999 (implicit EFLAGS)]>;
3002 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3003 "test{b}\t{$src, %al|%al, $src}", []>;
3004 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3005 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3006 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3007 "test{l}\t{$src, %eax|%eax, $src}", []>;
3009 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3010 "test{b}\t{$src2, $src1|$src1, $src2}",
3011 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
3012 (implicit EFLAGS)]>;
3013 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3014 "test{w}\t{$src2, $src1|$src1, $src2}",
3015 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
3016 (implicit EFLAGS)]>, OpSize;
3017 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3018 "test{l}\t{$src2, $src1|$src1, $src2}",
3019 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
3020 (implicit EFLAGS)]>;
3022 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3023 (outs), (ins GR8:$src1, i8imm:$src2),
3024 "test{b}\t{$src2, $src1|$src1, $src2}",
3025 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
3026 (implicit EFLAGS)]>;
3027 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3028 (outs), (ins GR16:$src1, i16imm:$src2),
3029 "test{w}\t{$src2, $src1|$src1, $src2}",
3030 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
3031 (implicit EFLAGS)]>, OpSize;
3032 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3033 (outs), (ins GR32:$src1, i32imm:$src2),
3034 "test{l}\t{$src2, $src1|$src1, $src2}",
3035 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
3036 (implicit EFLAGS)]>;
3038 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3039 (outs), (ins i8mem:$src1, i8imm:$src2),
3040 "test{b}\t{$src2, $src1|$src1, $src2}",
3041 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
3042 (implicit EFLAGS)]>;
3043 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3044 (outs), (ins i16mem:$src1, i16imm:$src2),
3045 "test{w}\t{$src2, $src1|$src1, $src2}",
3046 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
3047 (implicit EFLAGS)]>, OpSize;
3048 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3049 (outs), (ins i32mem:$src1, i32imm:$src2),
3050 "test{l}\t{$src2, $src1|$src1, $src2}",
3051 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
3052 (implicit EFLAGS)]>;
3053 } // Defs = [EFLAGS]
3056 // Condition code ops, incl. set if equal/not equal/...
3057 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3058 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3059 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3060 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3062 let Uses = [EFLAGS] in {
3063 def SETEr : I<0x94, MRM0r,
3064 (outs GR8 :$dst), (ins),
3066 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3068 def SETEm : I<0x94, MRM0m,
3069 (outs), (ins i8mem:$dst),
3071 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3074 def SETNEr : I<0x95, MRM0r,
3075 (outs GR8 :$dst), (ins),
3077 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3079 def SETNEm : I<0x95, MRM0m,
3080 (outs), (ins i8mem:$dst),
3082 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3085 def SETLr : I<0x9C, MRM0r,
3086 (outs GR8 :$dst), (ins),
3088 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3089 TB; // GR8 = < signed
3090 def SETLm : I<0x9C, MRM0m,
3091 (outs), (ins i8mem:$dst),
3093 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3094 TB; // [mem8] = < signed
3096 def SETGEr : I<0x9D, MRM0r,
3097 (outs GR8 :$dst), (ins),
3099 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3100 TB; // GR8 = >= signed
3101 def SETGEm : I<0x9D, MRM0m,
3102 (outs), (ins i8mem:$dst),
3104 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3105 TB; // [mem8] = >= signed
3107 def SETLEr : I<0x9E, MRM0r,
3108 (outs GR8 :$dst), (ins),
3110 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3111 TB; // GR8 = <= signed
3112 def SETLEm : I<0x9E, MRM0m,
3113 (outs), (ins i8mem:$dst),
3115 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3116 TB; // [mem8] = <= signed
3118 def SETGr : I<0x9F, MRM0r,
3119 (outs GR8 :$dst), (ins),
3121 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3122 TB; // GR8 = > signed
3123 def SETGm : I<0x9F, MRM0m,
3124 (outs), (ins i8mem:$dst),
3126 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3127 TB; // [mem8] = > signed
3129 def SETBr : I<0x92, MRM0r,
3130 (outs GR8 :$dst), (ins),
3132 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3133 TB; // GR8 = < unsign
3134 def SETBm : I<0x92, MRM0m,
3135 (outs), (ins i8mem:$dst),
3137 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3138 TB; // [mem8] = < unsign
3140 def SETAEr : I<0x93, MRM0r,
3141 (outs GR8 :$dst), (ins),
3143 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3144 TB; // GR8 = >= unsign
3145 def SETAEm : I<0x93, MRM0m,
3146 (outs), (ins i8mem:$dst),
3148 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3149 TB; // [mem8] = >= unsign
3151 def SETBEr : I<0x96, MRM0r,
3152 (outs GR8 :$dst), (ins),
3154 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3155 TB; // GR8 = <= unsign
3156 def SETBEm : I<0x96, MRM0m,
3157 (outs), (ins i8mem:$dst),
3159 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3160 TB; // [mem8] = <= unsign
3162 def SETAr : I<0x97, MRM0r,
3163 (outs GR8 :$dst), (ins),
3165 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3166 TB; // GR8 = > signed
3167 def SETAm : I<0x97, MRM0m,
3168 (outs), (ins i8mem:$dst),
3170 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3171 TB; // [mem8] = > signed
3173 def SETSr : I<0x98, MRM0r,
3174 (outs GR8 :$dst), (ins),
3176 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3177 TB; // GR8 = <sign bit>
3178 def SETSm : I<0x98, MRM0m,
3179 (outs), (ins i8mem:$dst),
3181 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3182 TB; // [mem8] = <sign bit>
3183 def SETNSr : I<0x99, MRM0r,
3184 (outs GR8 :$dst), (ins),
3186 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3187 TB; // GR8 = !<sign bit>
3188 def SETNSm : I<0x99, MRM0m,
3189 (outs), (ins i8mem:$dst),
3191 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3192 TB; // [mem8] = !<sign bit>
3194 def SETPr : I<0x9A, MRM0r,
3195 (outs GR8 :$dst), (ins),
3197 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3199 def SETPm : I<0x9A, MRM0m,
3200 (outs), (ins i8mem:$dst),
3202 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3203 TB; // [mem8] = parity
3204 def SETNPr : I<0x9B, MRM0r,
3205 (outs GR8 :$dst), (ins),
3207 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3208 TB; // GR8 = not parity
3209 def SETNPm : I<0x9B, MRM0m,
3210 (outs), (ins i8mem:$dst),
3212 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3213 TB; // [mem8] = not parity
3215 def SETOr : I<0x90, MRM0r,
3216 (outs GR8 :$dst), (ins),
3218 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3219 TB; // GR8 = overflow
3220 def SETOm : I<0x90, MRM0m,
3221 (outs), (ins i8mem:$dst),
3223 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3224 TB; // [mem8] = overflow
3225 def SETNOr : I<0x91, MRM0r,
3226 (outs GR8 :$dst), (ins),
3228 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3229 TB; // GR8 = not overflow
3230 def SETNOm : I<0x91, MRM0m,
3231 (outs), (ins i8mem:$dst),
3233 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3234 TB; // [mem8] = not overflow
3235 } // Uses = [EFLAGS]
3238 // Integer comparisons
3239 let Defs = [EFLAGS] in {
3240 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3241 "cmp{b}\t{$src, %al|%al, $src}", []>;
3242 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3243 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3244 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3245 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3247 def CMP8rr : I<0x38, MRMDestReg,
3248 (outs), (ins GR8 :$src1, GR8 :$src2),
3249 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3250 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
3251 def CMP16rr : I<0x39, MRMDestReg,
3252 (outs), (ins GR16:$src1, GR16:$src2),
3253 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3254 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
3255 def CMP32rr : I<0x39, MRMDestReg,
3256 (outs), (ins GR32:$src1, GR32:$src2),
3257 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3258 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
3259 def CMP8mr : I<0x38, MRMDestMem,
3260 (outs), (ins i8mem :$src1, GR8 :$src2),
3261 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3262 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
3263 (implicit EFLAGS)]>;
3264 def CMP16mr : I<0x39, MRMDestMem,
3265 (outs), (ins i16mem:$src1, GR16:$src2),
3266 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3267 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
3268 (implicit EFLAGS)]>, OpSize;
3269 def CMP32mr : I<0x39, MRMDestMem,
3270 (outs), (ins i32mem:$src1, GR32:$src2),
3271 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3272 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
3273 (implicit EFLAGS)]>;
3274 def CMP8rm : I<0x3A, MRMSrcMem,
3275 (outs), (ins GR8 :$src1, i8mem :$src2),
3276 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3277 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
3278 (implicit EFLAGS)]>;
3279 def CMP16rm : I<0x3B, MRMSrcMem,
3280 (outs), (ins GR16:$src1, i16mem:$src2),
3281 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3282 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
3283 (implicit EFLAGS)]>, OpSize;
3284 def CMP32rm : I<0x3B, MRMSrcMem,
3285 (outs), (ins GR32:$src1, i32mem:$src2),
3286 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3287 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
3288 (implicit EFLAGS)]>;
3289 def CMP8mrmrr : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3290 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3291 def CMP16mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3292 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3293 def CMP32mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3294 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3295 def CMP8ri : Ii8<0x80, MRM7r,
3296 (outs), (ins GR8:$src1, i8imm:$src2),
3297 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3298 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
3299 def CMP16ri : Ii16<0x81, MRM7r,
3300 (outs), (ins GR16:$src1, i16imm:$src2),
3301 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3302 [(X86cmp GR16:$src1, imm:$src2),
3303 (implicit EFLAGS)]>, OpSize;
3304 def CMP32ri : Ii32<0x81, MRM7r,
3305 (outs), (ins GR32:$src1, i32imm:$src2),
3306 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3307 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
3308 def CMP8mi : Ii8 <0x80, MRM7m,
3309 (outs), (ins i8mem :$src1, i8imm :$src2),
3310 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3311 [(X86cmp (loadi8 addr:$src1), imm:$src2),
3312 (implicit EFLAGS)]>;
3313 def CMP16mi : Ii16<0x81, MRM7m,
3314 (outs), (ins i16mem:$src1, i16imm:$src2),
3315 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3316 [(X86cmp (loadi16 addr:$src1), imm:$src2),
3317 (implicit EFLAGS)]>, OpSize;
3318 def CMP32mi : Ii32<0x81, MRM7m,
3319 (outs), (ins i32mem:$src1, i32imm:$src2),
3320 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3321 [(X86cmp (loadi32 addr:$src1), imm:$src2),
3322 (implicit EFLAGS)]>;
3323 def CMP16ri8 : Ii8<0x83, MRM7r,
3324 (outs), (ins GR16:$src1, i16i8imm:$src2),
3325 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3326 [(X86cmp GR16:$src1, i16immSExt8:$src2),
3327 (implicit EFLAGS)]>, OpSize;
3328 def CMP16mi8 : Ii8<0x83, MRM7m,
3329 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3330 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3331 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
3332 (implicit EFLAGS)]>, OpSize;
3333 def CMP32mi8 : Ii8<0x83, MRM7m,
3334 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3335 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3336 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
3337 (implicit EFLAGS)]>;
3338 def CMP32ri8 : Ii8<0x83, MRM7r,
3339 (outs), (ins GR32:$src1, i32i8imm:$src2),
3340 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3341 [(X86cmp GR32:$src1, i32immSExt8:$src2),
3342 (implicit EFLAGS)]>;
3343 } // Defs = [EFLAGS]
3346 // TODO: BTC, BTR, and BTS
3347 let Defs = [EFLAGS] in {
3348 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3349 "bt{w}\t{$src2, $src1|$src1, $src2}",
3350 [(X86bt GR16:$src1, GR16:$src2),
3351 (implicit EFLAGS)]>, OpSize, TB;
3352 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3353 "bt{l}\t{$src2, $src1|$src1, $src2}",
3354 [(X86bt GR32:$src1, GR32:$src2),
3355 (implicit EFLAGS)]>, TB;
3357 // Unlike with the register+register form, the memory+register form of the
3358 // bt instruction does not ignore the high bits of the index. From ISel's
3359 // perspective, this is pretty bizarre. Disable these instructions for now.
3360 //def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3361 // "bt{w}\t{$src2, $src1|$src1, $src2}",
3362 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3363 // (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
3364 //def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3365 // "bt{l}\t{$src2, $src1|$src1, $src2}",
3366 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3367 // (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
3369 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3370 "bt{w}\t{$src2, $src1|$src1, $src2}",
3371 [(X86bt GR16:$src1, i16immSExt8:$src2),
3372 (implicit EFLAGS)]>, OpSize, TB;
3373 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3374 "bt{l}\t{$src2, $src1|$src1, $src2}",
3375 [(X86bt GR32:$src1, i32immSExt8:$src2),
3376 (implicit EFLAGS)]>, TB;
3377 // Note that these instructions don't need FastBTMem because that
3378 // only applies when the other operand is in a register. When it's
3379 // an immediate, bt is still fast.
3380 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3381 "bt{w}\t{$src2, $src1|$src1, $src2}",
3382 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3383 (implicit EFLAGS)]>, OpSize, TB;
3384 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3385 "bt{l}\t{$src2, $src1|$src1, $src2}",
3386 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3387 (implicit EFLAGS)]>, TB;
3388 } // Defs = [EFLAGS]
3390 // Sign/Zero extenders
3391 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3392 // of the register here. This has a smaller encoding and avoids a
3393 // partial-register update.
3394 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3395 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3396 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3397 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3398 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3399 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3400 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3401 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3402 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3403 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3404 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3405 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3406 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3407 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3408 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3409 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3411 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3412 // of the register here. This has a smaller encoding and avoids a
3413 // partial-register update.
3414 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3415 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3416 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3417 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3418 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3419 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3420 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3421 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3422 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3423 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3424 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3425 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3426 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3427 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3428 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3429 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3431 // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
3432 // except that they use GR32_NOREX for the output operand register class
3433 // instead of GR32. This allows them to operate on h registers on x86-64.
3434 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3435 (outs GR32_NOREX:$dst), (ins GR8:$src),
3436 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3439 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3440 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3441 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3444 let neverHasSideEffects = 1 in {
3445 let Defs = [AX], Uses = [AL] in
3446 def CBW : I<0x98, RawFrm, (outs), (ins),
3447 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3448 let Defs = [EAX], Uses = [AX] in
3449 def CWDE : I<0x98, RawFrm, (outs), (ins),
3450 "{cwtl|cwde}", []>; // EAX = signext(AX)
3452 let Defs = [AX,DX], Uses = [AX] in
3453 def CWD : I<0x99, RawFrm, (outs), (ins),
3454 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3455 let Defs = [EAX,EDX], Uses = [EAX] in
3456 def CDQ : I<0x99, RawFrm, (outs), (ins),
3457 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3460 //===----------------------------------------------------------------------===//
3461 // Alias Instructions
3462 //===----------------------------------------------------------------------===//
3464 // Alias instructions that map movr0 to xor.
3465 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3466 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3467 isCodeGenOnly = 1 in {
3468 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3469 "xor{b}\t$dst, $dst",
3470 [(set GR8:$dst, 0)]>;
3471 // Use xorl instead of xorw since we don't care about the high 16 bits,
3472 // it's smaller, and it avoids a partial-register update.
3473 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3474 "", [(set GR16:$dst, 0)]>;
3475 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3476 "xor{l}\t$dst, $dst",
3477 [(set GR32:$dst, 0)]>;
3480 //===----------------------------------------------------------------------===//
3481 // Thread Local Storage Instructions
3484 // All calls clobber the non-callee saved registers. ESP is marked as
3485 // a use to prevent stack-pointer assignments that appear immediately
3486 // before calls from potentially appearing dead.
3487 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3488 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3489 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3490 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3492 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3493 "leal\t$sym, %eax; "
3494 "call\t___tls_get_addr@PLT",
3495 [(X86tlsaddr tls32addr:$sym)]>,
3496 Requires<[In32BitMode]>;
3498 let AddedComplexity = 5, isCodeGenOnly = 1 in
3499 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3500 "movl\t%gs:$src, $dst",
3501 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3503 let AddedComplexity = 5, isCodeGenOnly = 1 in
3504 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3505 "movl\t%fs:$src, $dst",
3506 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3508 //===----------------------------------------------------------------------===//
3509 // DWARF Pseudo Instructions
3512 def DWARF_LOC : I<0, Pseudo, (outs),
3513 (ins i32imm:$line, i32imm:$col, i32imm:$file),
3514 ".loc\t$file $line $col",
3515 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
3518 //===----------------------------------------------------------------------===//
3519 // EH Pseudo Instructions
3521 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3522 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3523 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3524 "ret\t#eh_return, addr: $addr",
3525 [(X86ehret GR32:$addr)]>;
3529 //===----------------------------------------------------------------------===//
3533 // Atomic swap. These are just normal xchg instructions. But since a memory
3534 // operand is referenced, the atomicity is ensured.
3535 let Constraints = "$val = $dst" in {
3536 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3537 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3538 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3539 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3540 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3541 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3543 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3544 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3545 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3548 // Atomic compare and swap.
3549 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3550 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3552 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3553 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3555 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3556 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
3559 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3562 let Defs = [AX, EFLAGS], Uses = [AX] in {
3563 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3565 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3566 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3568 let Defs = [AL, EFLAGS], Uses = [AL] in {
3569 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3571 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3572 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3575 // Atomic exchange and add
3576 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3577 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3579 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3580 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3582 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3584 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3585 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3587 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3589 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3590 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3594 // Optimized codegen when the non-memory output is not used.
3595 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3596 let Defs = [EFLAGS] in {
3597 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3599 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3600 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3602 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3603 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3605 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3606 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3608 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3609 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3611 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3612 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3614 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3615 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3617 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3618 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3620 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3622 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3624 "inc{b}\t$dst", []>, LOCK;
3625 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3627 "inc{w}\t$dst", []>, OpSize, LOCK;
3628 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3630 "inc{l}\t$dst", []>, LOCK;
3632 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3634 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3635 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3637 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3638 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3640 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3641 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3643 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3644 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3646 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3647 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3649 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3650 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3652 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3653 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3655 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3657 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3659 "dec{b}\t$dst", []>, LOCK;
3660 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3662 "dec{w}\t$dst", []>, OpSize, LOCK;
3663 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3665 "dec{l}\t$dst", []>, LOCK;
3668 // Atomic exchange, and, or, xor
3669 let Constraints = "$val = $dst", Defs = [EFLAGS],
3670 usesCustomInserter = 1 in {
3671 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3672 "#ATOMAND32 PSEUDO!",
3673 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3674 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3675 "#ATOMOR32 PSEUDO!",
3676 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3677 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3678 "#ATOMXOR32 PSEUDO!",
3679 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3680 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3681 "#ATOMNAND32 PSEUDO!",
3682 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3683 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3684 "#ATOMMIN32 PSEUDO!",
3685 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3686 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3687 "#ATOMMAX32 PSEUDO!",
3688 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3689 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3690 "#ATOMUMIN32 PSEUDO!",
3691 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3692 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3693 "#ATOMUMAX32 PSEUDO!",
3694 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3696 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3697 "#ATOMAND16 PSEUDO!",
3698 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3699 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3700 "#ATOMOR16 PSEUDO!",
3701 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3702 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3703 "#ATOMXOR16 PSEUDO!",
3704 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
3705 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3706 "#ATOMNAND16 PSEUDO!",
3707 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
3708 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3709 "#ATOMMIN16 PSEUDO!",
3710 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
3711 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3712 "#ATOMMAX16 PSEUDO!",
3713 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
3714 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3715 "#ATOMUMIN16 PSEUDO!",
3716 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
3717 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3718 "#ATOMUMAX16 PSEUDO!",
3719 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
3721 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3722 "#ATOMAND8 PSEUDO!",
3723 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
3724 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3726 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
3727 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3728 "#ATOMXOR8 PSEUDO!",
3729 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
3730 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3731 "#ATOMNAND8 PSEUDO!",
3732 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
3735 let Constraints = "$val1 = $dst1, $val2 = $dst2",
3736 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3737 Uses = [EAX, EBX, ECX, EDX],
3738 mayLoad = 1, mayStore = 1,
3739 usesCustomInserter = 1 in {
3740 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3741 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3742 "#ATOMAND6432 PSEUDO!", []>;
3743 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3744 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3745 "#ATOMOR6432 PSEUDO!", []>;
3746 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3747 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3748 "#ATOMXOR6432 PSEUDO!", []>;
3749 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3750 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3751 "#ATOMNAND6432 PSEUDO!", []>;
3752 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3753 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3754 "#ATOMADD6432 PSEUDO!", []>;
3755 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3756 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3757 "#ATOMSUB6432 PSEUDO!", []>;
3758 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3759 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3760 "#ATOMSWAP6432 PSEUDO!", []>;
3763 // Segmentation support instructions.
3765 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
3766 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3767 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
3768 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3770 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
3771 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3772 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
3773 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
3774 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
3776 // String manipulation instructions
3778 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
3779 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
3780 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lodsd", []>;
3782 //===----------------------------------------------------------------------===//
3783 // Non-Instruction Patterns
3784 //===----------------------------------------------------------------------===//
3786 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
3787 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3788 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
3789 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
3790 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3791 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3792 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
3794 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3795 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3796 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3797 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3798 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3799 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3800 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3801 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3802 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
3803 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
3805 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3806 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3807 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3808 (MOV32mi addr:$dst, texternalsym:$src)>;
3809 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
3810 (MOV32mi addr:$dst, tblockaddress:$src)>;
3814 def : Pat<(X86tcret GR32:$dst, imm:$off),
3815 (TCRETURNri GR32:$dst, imm:$off)>;
3817 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3818 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3820 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3821 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3823 // Normal calls, with various flavors of addresses.
3824 def : Pat<(X86call (i32 tglobaladdr:$dst)),
3825 (CALLpcrel32 tglobaladdr:$dst)>;
3826 def : Pat<(X86call (i32 texternalsym:$dst)),
3827 (CALLpcrel32 texternalsym:$dst)>;
3828 def : Pat<(X86call (i32 imm:$dst)),
3829 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
3831 // X86 specific add which produces a flag.
3832 def : Pat<(addc GR32:$src1, GR32:$src2),
3833 (ADD32rr GR32:$src1, GR32:$src2)>;
3834 def : Pat<(addc GR32:$src1, (load addr:$src2)),
3835 (ADD32rm GR32:$src1, addr:$src2)>;
3836 def : Pat<(addc GR32:$src1, imm:$src2),
3837 (ADD32ri GR32:$src1, imm:$src2)>;
3838 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3839 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3841 def : Pat<(subc GR32:$src1, GR32:$src2),
3842 (SUB32rr GR32:$src1, GR32:$src2)>;
3843 def : Pat<(subc GR32:$src1, (load addr:$src2)),
3844 (SUB32rm GR32:$src1, addr:$src2)>;
3845 def : Pat<(subc GR32:$src1, imm:$src2),
3846 (SUB32ri GR32:$src1, imm:$src2)>;
3847 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3848 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3852 // TEST R,R is smaller than CMP R,0
3853 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
3854 (TEST8rr GR8:$src1, GR8:$src1)>;
3855 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
3856 (TEST16rr GR16:$src1, GR16:$src1)>;
3857 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
3858 (TEST32rr GR32:$src1, GR32:$src1)>;
3860 // Conditional moves with folded loads with operands swapped and conditions
3862 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
3863 (CMOVAE16rm GR16:$src2, addr:$src1)>;
3864 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
3865 (CMOVAE32rm GR32:$src2, addr:$src1)>;
3866 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
3867 (CMOVB16rm GR16:$src2, addr:$src1)>;
3868 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
3869 (CMOVB32rm GR32:$src2, addr:$src1)>;
3870 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
3871 (CMOVNE16rm GR16:$src2, addr:$src1)>;
3872 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
3873 (CMOVNE32rm GR32:$src2, addr:$src1)>;
3874 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
3875 (CMOVE16rm GR16:$src2, addr:$src1)>;
3876 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
3877 (CMOVE32rm GR32:$src2, addr:$src1)>;
3878 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
3879 (CMOVA16rm GR16:$src2, addr:$src1)>;
3880 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
3881 (CMOVA32rm GR32:$src2, addr:$src1)>;
3882 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
3883 (CMOVBE16rm GR16:$src2, addr:$src1)>;
3884 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
3885 (CMOVBE32rm GR32:$src2, addr:$src1)>;
3886 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
3887 (CMOVGE16rm GR16:$src2, addr:$src1)>;
3888 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
3889 (CMOVGE32rm GR32:$src2, addr:$src1)>;
3890 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
3891 (CMOVL16rm GR16:$src2, addr:$src1)>;
3892 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
3893 (CMOVL32rm GR32:$src2, addr:$src1)>;
3894 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
3895 (CMOVG16rm GR16:$src2, addr:$src1)>;
3896 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
3897 (CMOVG32rm GR32:$src2, addr:$src1)>;
3898 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
3899 (CMOVLE16rm GR16:$src2, addr:$src1)>;
3900 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
3901 (CMOVLE32rm GR32:$src2, addr:$src1)>;
3902 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
3903 (CMOVNP16rm GR16:$src2, addr:$src1)>;
3904 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
3905 (CMOVNP32rm GR32:$src2, addr:$src1)>;
3906 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
3907 (CMOVP16rm GR16:$src2, addr:$src1)>;
3908 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
3909 (CMOVP32rm GR32:$src2, addr:$src1)>;
3910 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
3911 (CMOVNS16rm GR16:$src2, addr:$src1)>;
3912 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
3913 (CMOVNS32rm GR32:$src2, addr:$src1)>;
3914 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
3915 (CMOVS16rm GR16:$src2, addr:$src1)>;
3916 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
3917 (CMOVS32rm GR32:$src2, addr:$src1)>;
3918 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
3919 (CMOVNO16rm GR16:$src2, addr:$src1)>;
3920 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
3921 (CMOVNO32rm GR32:$src2, addr:$src1)>;
3922 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
3923 (CMOVO16rm GR16:$src2, addr:$src1)>;
3924 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
3925 (CMOVO32rm GR32:$src2, addr:$src1)>;
3927 // zextload bool -> zextload byte
3928 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3929 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3930 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3932 // extload bool -> extload byte
3933 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3934 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3935 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3936 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
3937 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3938 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3940 // anyext. Define these to do an explicit zero-extend to
3941 // avoid partial-register updates.
3942 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
3943 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
3944 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
3946 // (and (i32 load), 255) -> (zextload i8)
3947 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3948 (MOVZX32rm8 addr:$src)>;
3949 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3950 (MOVZX32rm16 addr:$src)>;
3952 //===----------------------------------------------------------------------===//
3954 //===----------------------------------------------------------------------===//
3956 // Odd encoding trick: -128 fits into an 8-bit immediate field while
3957 // +128 doesn't, so in this special case use a sub instead of an add.
3958 def : Pat<(add GR16:$src1, 128),
3959 (SUB16ri8 GR16:$src1, -128)>;
3960 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3961 (SUB16mi8 addr:$dst, -128)>;
3962 def : Pat<(add GR32:$src1, 128),
3963 (SUB32ri8 GR32:$src1, -128)>;
3964 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3965 (SUB32mi8 addr:$dst, -128)>;
3967 // r & (2^16-1) ==> movz
3968 def : Pat<(and GR32:$src1, 0xffff),
3969 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
3970 // r & (2^8-1) ==> movz
3971 def : Pat<(and GR32:$src1, 0xff),
3972 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
3975 Requires<[In32BitMode]>;
3976 // r & (2^8-1) ==> movz
3977 def : Pat<(and GR16:$src1, 0xff),
3978 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
3981 Requires<[In32BitMode]>;
3983 // sext_inreg patterns
3984 def : Pat<(sext_inreg GR32:$src, i16),
3985 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
3986 def : Pat<(sext_inreg GR32:$src, i8),
3987 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
3990 Requires<[In32BitMode]>;
3991 def : Pat<(sext_inreg GR16:$src, i8),
3992 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
3995 Requires<[In32BitMode]>;
3998 def : Pat<(i16 (trunc GR32:$src)),
3999 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
4000 def : Pat<(i8 (trunc GR32:$src)),
4001 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4003 Requires<[In32BitMode]>;
4004 def : Pat<(i8 (trunc GR16:$src)),
4005 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4007 Requires<[In32BitMode]>;
4009 // h-register tricks
4010 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4011 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4012 x86_subreg_8bit_hi)>,
4013 Requires<[In32BitMode]>;
4014 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4015 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4016 x86_subreg_8bit_hi)>,
4017 Requires<[In32BitMode]>;
4018 def : Pat<(srl_su GR16:$src, (i8 8)),
4021 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4022 x86_subreg_8bit_hi)),
4024 Requires<[In32BitMode]>;
4025 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4026 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4027 x86_subreg_8bit_hi))>,
4028 Requires<[In32BitMode]>;
4029 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4030 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4031 x86_subreg_8bit_hi))>,
4032 Requires<[In32BitMode]>;
4033 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4034 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4035 x86_subreg_8bit_hi))>,
4036 Requires<[In32BitMode]>;
4038 // (shl x, 1) ==> (add x, x)
4039 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4040 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4041 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4043 // (shl x (and y, 31)) ==> (shl x, y)
4044 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
4045 (SHL8rCL GR8:$src1)>;
4046 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
4047 (SHL16rCL GR16:$src1)>;
4048 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
4049 (SHL32rCL GR32:$src1)>;
4050 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4051 (SHL8mCL addr:$dst)>;
4052 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4053 (SHL16mCL addr:$dst)>;
4054 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4055 (SHL32mCL addr:$dst)>;
4057 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
4058 (SHR8rCL GR8:$src1)>;
4059 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
4060 (SHR16rCL GR16:$src1)>;
4061 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
4062 (SHR32rCL GR32:$src1)>;
4063 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4064 (SHR8mCL addr:$dst)>;
4065 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4066 (SHR16mCL addr:$dst)>;
4067 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4068 (SHR32mCL addr:$dst)>;
4070 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
4071 (SAR8rCL GR8:$src1)>;
4072 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
4073 (SAR16rCL GR16:$src1)>;
4074 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
4075 (SAR32rCL GR32:$src1)>;
4076 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4077 (SAR8mCL addr:$dst)>;
4078 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4079 (SAR16mCL addr:$dst)>;
4080 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4081 (SAR32mCL addr:$dst)>;
4083 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
4084 def : Pat<(or (srl GR32:$src1, CL:$amt),
4085 (shl GR32:$src2, (sub 32, CL:$amt))),
4086 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4088 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
4089 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4090 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4092 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
4093 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4094 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4096 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4097 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4099 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4101 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
4102 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4104 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
4105 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
4106 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4108 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
4109 def : Pat<(or (shl GR32:$src1, CL:$amt),
4110 (srl GR32:$src2, (sub 32, CL:$amt))),
4111 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4113 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
4114 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4115 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4117 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
4118 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4119 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4121 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4122 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4124 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4126 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
4127 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4129 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
4130 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
4131 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4133 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
4134 def : Pat<(or (srl GR16:$src1, CL:$amt),
4135 (shl GR16:$src2, (sub 16, CL:$amt))),
4136 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4138 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
4139 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4140 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4142 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
4143 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4144 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4146 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4147 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4149 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4151 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
4152 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4154 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
4155 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
4156 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4158 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
4159 def : Pat<(or (shl GR16:$src1, CL:$amt),
4160 (srl GR16:$src2, (sub 16, CL:$amt))),
4161 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4163 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
4164 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4165 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4167 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
4168 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4169 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4171 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4172 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4174 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4176 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
4177 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4179 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
4180 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
4181 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4183 //===----------------------------------------------------------------------===//
4184 // EFLAGS-defining Patterns
4185 //===----------------------------------------------------------------------===//
4187 // Register-Register Addition with EFLAGS result
4188 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
4190 (ADD8rr GR8:$src1, GR8:$src2)>;
4191 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
4193 (ADD16rr GR16:$src1, GR16:$src2)>;
4194 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
4196 (ADD32rr GR32:$src1, GR32:$src2)>;
4198 // Register-Memory Addition with EFLAGS result
4199 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
4201 (ADD8rm GR8:$src1, addr:$src2)>;
4202 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
4204 (ADD16rm GR16:$src1, addr:$src2)>;
4205 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
4207 (ADD32rm GR32:$src1, addr:$src2)>;
4209 // Register-Integer Addition with EFLAGS result
4210 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
4212 (ADD8ri GR8:$src1, imm:$src2)>;
4213 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
4215 (ADD16ri GR16:$src1, imm:$src2)>;
4216 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
4218 (ADD32ri GR32:$src1, imm:$src2)>;
4219 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
4221 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4222 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
4224 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4226 // Memory-Register Addition with EFLAGS result
4227 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
4230 (ADD8mr addr:$dst, GR8:$src2)>;
4231 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
4234 (ADD16mr addr:$dst, GR16:$src2)>;
4235 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
4238 (ADD32mr addr:$dst, GR32:$src2)>;
4240 // Memory-Integer Addition with EFLAGS result
4241 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
4244 (ADD8mi addr:$dst, imm:$src2)>;
4245 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
4248 (ADD16mi addr:$dst, imm:$src2)>;
4249 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
4252 (ADD32mi addr:$dst, imm:$src2)>;
4253 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4256 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
4257 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4260 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
4262 // Register-Register Subtraction with EFLAGS result
4263 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
4265 (SUB8rr GR8:$src1, GR8:$src2)>;
4266 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
4268 (SUB16rr GR16:$src1, GR16:$src2)>;
4269 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
4271 (SUB32rr GR32:$src1, GR32:$src2)>;
4273 // Register-Memory Subtraction with EFLAGS result
4274 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
4276 (SUB8rm GR8:$src1, addr:$src2)>;
4277 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
4279 (SUB16rm GR16:$src1, addr:$src2)>;
4280 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
4282 (SUB32rm GR32:$src1, addr:$src2)>;
4284 // Register-Integer Subtraction with EFLAGS result
4285 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
4287 (SUB8ri GR8:$src1, imm:$src2)>;
4288 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
4290 (SUB16ri GR16:$src1, imm:$src2)>;
4291 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
4293 (SUB32ri GR32:$src1, imm:$src2)>;
4294 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
4296 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4297 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
4299 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4301 // Memory-Register Subtraction with EFLAGS result
4302 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
4305 (SUB8mr addr:$dst, GR8:$src2)>;
4306 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
4309 (SUB16mr addr:$dst, GR16:$src2)>;
4310 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
4313 (SUB32mr addr:$dst, GR32:$src2)>;
4315 // Memory-Integer Subtraction with EFLAGS result
4316 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
4319 (SUB8mi addr:$dst, imm:$src2)>;
4320 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
4323 (SUB16mi addr:$dst, imm:$src2)>;
4324 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
4327 (SUB32mi addr:$dst, imm:$src2)>;
4328 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4331 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
4332 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4335 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
4338 // Register-Register Signed Integer Multiply with EFLAGS result
4339 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
4341 (IMUL16rr GR16:$src1, GR16:$src2)>;
4342 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
4344 (IMUL32rr GR32:$src1, GR32:$src2)>;
4346 // Register-Memory Signed Integer Multiply with EFLAGS result
4347 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
4349 (IMUL16rm GR16:$src1, addr:$src2)>;
4350 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
4352 (IMUL32rm GR32:$src1, addr:$src2)>;
4354 // Register-Integer Signed Integer Multiply with EFLAGS result
4355 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
4357 (IMUL16rri GR16:$src1, imm:$src2)>;
4358 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
4360 (IMUL32rri GR32:$src1, imm:$src2)>;
4361 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
4363 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4364 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
4366 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4368 // Memory-Integer Signed Integer Multiply with EFLAGS result
4369 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
4371 (IMUL16rmi addr:$src1, imm:$src2)>;
4372 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
4374 (IMUL32rmi addr:$src1, imm:$src2)>;
4375 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
4377 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4378 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
4380 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4382 // Optimize multiply by 2 with EFLAGS result.
4383 let AddedComplexity = 2 in {
4384 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
4386 (ADD16rr GR16:$src1, GR16:$src1)>;
4388 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
4390 (ADD32rr GR32:$src1, GR32:$src1)>;
4393 // INC and DEC with EFLAGS result. Note that these do not set CF.
4394 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4396 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4399 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4401 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4405 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
4406 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4407 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4409 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
4410 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
4411 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4412 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4414 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
4416 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
4417 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4418 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4420 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
4421 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
4422 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4423 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4425 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
4427 // Register-Register Or with EFLAGS result
4428 def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2),
4430 (OR8rr GR8:$src1, GR8:$src2)>;
4431 def : Pat<(parallel (X86or_flag GR16:$src1, GR16:$src2),
4433 (OR16rr GR16:$src1, GR16:$src2)>;
4434 def : Pat<(parallel (X86or_flag GR32:$src1, GR32:$src2),
4436 (OR32rr GR32:$src1, GR32:$src2)>;
4438 // Register-Memory Or with EFLAGS result
4439 def : Pat<(parallel (X86or_flag GR8:$src1, (loadi8 addr:$src2)),
4441 (OR8rm GR8:$src1, addr:$src2)>;
4442 def : Pat<(parallel (X86or_flag GR16:$src1, (loadi16 addr:$src2)),
4444 (OR16rm GR16:$src1, addr:$src2)>;
4445 def : Pat<(parallel (X86or_flag GR32:$src1, (loadi32 addr:$src2)),
4447 (OR32rm GR32:$src1, addr:$src2)>;
4449 // Register-Integer Or with EFLAGS result
4450 def : Pat<(parallel (X86or_flag GR8:$src1, imm:$src2),
4452 (OR8ri GR8:$src1, imm:$src2)>;
4453 def : Pat<(parallel (X86or_flag GR16:$src1, imm:$src2),
4455 (OR16ri GR16:$src1, imm:$src2)>;
4456 def : Pat<(parallel (X86or_flag GR32:$src1, imm:$src2),
4458 (OR32ri GR32:$src1, imm:$src2)>;
4459 def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2),
4461 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4462 def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2),
4464 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4466 // Memory-Register Or with EFLAGS result
4467 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2),
4470 (OR8mr addr:$dst, GR8:$src2)>;
4471 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), GR16:$src2),
4474 (OR16mr addr:$dst, GR16:$src2)>;
4475 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), GR32:$src2),
4478 (OR32mr addr:$dst, GR32:$src2)>;
4480 // Memory-Integer Or with EFLAGS result
4481 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), imm:$src2),
4484 (OR8mi addr:$dst, imm:$src2)>;
4485 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), imm:$src2),
4488 (OR16mi addr:$dst, imm:$src2)>;
4489 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), imm:$src2),
4492 (OR32mi addr:$dst, imm:$src2)>;
4493 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4496 (OR16mi8 addr:$dst, i16immSExt8:$src2)>;
4497 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4500 (OR32mi8 addr:$dst, i32immSExt8:$src2)>;
4502 // Register-Register XOr with EFLAGS result
4503 def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2),
4505 (XOR8rr GR8:$src1, GR8:$src2)>;
4506 def : Pat<(parallel (X86xor_flag GR16:$src1, GR16:$src2),
4508 (XOR16rr GR16:$src1, GR16:$src2)>;
4509 def : Pat<(parallel (X86xor_flag GR32:$src1, GR32:$src2),
4511 (XOR32rr GR32:$src1, GR32:$src2)>;
4513 // Register-Memory XOr with EFLAGS result
4514 def : Pat<(parallel (X86xor_flag GR8:$src1, (loadi8 addr:$src2)),
4516 (XOR8rm GR8:$src1, addr:$src2)>;
4517 def : Pat<(parallel (X86xor_flag GR16:$src1, (loadi16 addr:$src2)),
4519 (XOR16rm GR16:$src1, addr:$src2)>;
4520 def : Pat<(parallel (X86xor_flag GR32:$src1, (loadi32 addr:$src2)),
4522 (XOR32rm GR32:$src1, addr:$src2)>;
4524 // Register-Integer XOr with EFLAGS result
4525 def : Pat<(parallel (X86xor_flag GR8:$src1, imm:$src2),
4527 (XOR8ri GR8:$src1, imm:$src2)>;
4528 def : Pat<(parallel (X86xor_flag GR16:$src1, imm:$src2),
4530 (XOR16ri GR16:$src1, imm:$src2)>;
4531 def : Pat<(parallel (X86xor_flag GR32:$src1, imm:$src2),
4533 (XOR32ri GR32:$src1, imm:$src2)>;
4534 def : Pat<(parallel (X86xor_flag GR16:$src1, i16immSExt8:$src2),
4536 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4537 def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2),
4539 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4541 // Memory-Register XOr with EFLAGS result
4542 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2),
4545 (XOR8mr addr:$dst, GR8:$src2)>;
4546 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), GR16:$src2),
4549 (XOR16mr addr:$dst, GR16:$src2)>;
4550 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), GR32:$src2),
4553 (XOR32mr addr:$dst, GR32:$src2)>;
4555 // Memory-Integer XOr with EFLAGS result
4556 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), imm:$src2),
4559 (XOR8mi addr:$dst, imm:$src2)>;
4560 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), imm:$src2),
4563 (XOR16mi addr:$dst, imm:$src2)>;
4564 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), imm:$src2),
4567 (XOR32mi addr:$dst, imm:$src2)>;
4568 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4571 (XOR16mi8 addr:$dst, i16immSExt8:$src2)>;
4572 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4575 (XOR32mi8 addr:$dst, i32immSExt8:$src2)>;
4577 // Register-Register And with EFLAGS result
4578 def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
4580 (AND8rr GR8:$src1, GR8:$src2)>;
4581 def : Pat<(parallel (X86and_flag GR16:$src1, GR16:$src2),
4583 (AND16rr GR16:$src1, GR16:$src2)>;
4584 def : Pat<(parallel (X86and_flag GR32:$src1, GR32:$src2),
4586 (AND32rr GR32:$src1, GR32:$src2)>;
4588 // Register-Memory And with EFLAGS result
4589 def : Pat<(parallel (X86and_flag GR8:$src1, (loadi8 addr:$src2)),
4591 (AND8rm GR8:$src1, addr:$src2)>;
4592 def : Pat<(parallel (X86and_flag GR16:$src1, (loadi16 addr:$src2)),
4594 (AND16rm GR16:$src1, addr:$src2)>;
4595 def : Pat<(parallel (X86and_flag GR32:$src1, (loadi32 addr:$src2)),
4597 (AND32rm GR32:$src1, addr:$src2)>;
4599 // Register-Integer And with EFLAGS result
4600 def : Pat<(parallel (X86and_flag GR8:$src1, imm:$src2),
4602 (AND8ri GR8:$src1, imm:$src2)>;
4603 def : Pat<(parallel (X86and_flag GR16:$src1, imm:$src2),
4605 (AND16ri GR16:$src1, imm:$src2)>;
4606 def : Pat<(parallel (X86and_flag GR32:$src1, imm:$src2),
4608 (AND32ri GR32:$src1, imm:$src2)>;
4609 def : Pat<(parallel (X86and_flag GR16:$src1, i16immSExt8:$src2),
4611 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
4612 def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2),
4614 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
4616 // Memory-Register And with EFLAGS result
4617 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2),
4620 (AND8mr addr:$dst, GR8:$src2)>;
4621 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), GR16:$src2),
4624 (AND16mr addr:$dst, GR16:$src2)>;
4625 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), GR32:$src2),
4628 (AND32mr addr:$dst, GR32:$src2)>;
4630 // Memory-Integer And with EFLAGS result
4631 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), imm:$src2),
4634 (AND8mi addr:$dst, imm:$src2)>;
4635 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), imm:$src2),
4638 (AND16mi addr:$dst, imm:$src2)>;
4639 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), imm:$src2),
4642 (AND32mi addr:$dst, imm:$src2)>;
4643 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4646 (AND16mi8 addr:$dst, i16immSExt8:$src2)>;
4647 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4650 (AND32mi8 addr:$dst, i32immSExt8:$src2)>;
4652 // -disable-16bit support.
4653 def : Pat<(truncstorei16 (i32 imm:$src), addr:$dst),
4654 (MOV16mi addr:$dst, imm:$src)>;
4655 def : Pat<(truncstorei16 GR32:$src, addr:$dst),
4656 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4657 def : Pat<(i32 (sextloadi16 addr:$dst)),
4658 (MOVSX32rm16 addr:$dst)>;
4659 def : Pat<(i32 (zextloadi16 addr:$dst)),
4660 (MOVZX32rm16 addr:$dst)>;
4661 def : Pat<(i32 (extloadi16 addr:$dst)),
4662 (MOVZX32rm16 addr:$dst)>;
4664 //===----------------------------------------------------------------------===//
4665 // Floating Point Stack Support
4666 //===----------------------------------------------------------------------===//
4668 include "X86InstrFPStack.td"
4670 //===----------------------------------------------------------------------===//
4672 //===----------------------------------------------------------------------===//
4674 include "X86Instr64bit.td"
4676 //===----------------------------------------------------------------------===//
4677 // XMM Floating point support (requires SSE / SSE2)
4678 //===----------------------------------------------------------------------===//
4680 include "X86InstrSSE.td"
4682 //===----------------------------------------------------------------------===//
4683 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4684 //===----------------------------------------------------------------------===//
4686 include "X86InstrMMX.td"