1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/ErrorHandling.h"
44 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
45 const TargetInstrInfo &tii)
46 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
47 X86::ADJCALLSTACKDOWN64 :
48 X86::ADJCALLSTACKDOWN32,
49 tm.getSubtarget<X86Subtarget>().is64Bit() ?
50 X86::ADJCALLSTACKUP64 :
51 X86::ADJCALLSTACKUP32),
53 // Cache some information.
54 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
55 Is64Bit = Subtarget->is64Bit();
56 IsWin64 = Subtarget->isTargetWin64();
57 StackAlign = TM.getFrameInfo()->getStackAlignment();
70 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
71 /// specific numbering, used in debug info and exception tables.
72 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
73 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
74 unsigned Flavour = DWARFFlavour::X86_64;
76 if (!Subtarget->is64Bit()) {
77 if (Subtarget->isTargetDarwin()) {
79 Flavour = DWARFFlavour::X86_32_DarwinEH;
81 Flavour = DWARFFlavour::X86_32_Generic;
82 } else if (Subtarget->isTargetCygMing()) {
83 // Unsupported by now, just quick fallback
84 Flavour = DWARFFlavour::X86_32_Generic;
86 Flavour = DWARFFlavour::X86_32_Generic;
90 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
93 /// getX86RegNum - This function maps LLVM register identifiers to their X86
94 /// specific numbering, which is used in various places encoding instructions.
95 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
97 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
98 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
99 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
100 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
101 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
103 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
105 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
107 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
110 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
112 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
114 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
116 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
118 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
120 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
122 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
124 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
127 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
128 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
129 return RegNo-X86::ST0;
131 case X86::XMM0: case X86::XMM8: case X86::MM0:
133 case X86::XMM1: case X86::XMM9: case X86::MM1:
135 case X86::XMM2: case X86::XMM10: case X86::MM2:
137 case X86::XMM3: case X86::XMM11: case X86::MM3:
139 case X86::XMM4: case X86::XMM12: case X86::MM4:
141 case X86::XMM5: case X86::XMM13: case X86::MM5:
143 case X86::XMM6: case X86::XMM14: case X86::MM6:
145 case X86::XMM7: case X86::XMM15: case X86::MM7:
149 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
150 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
155 const TargetRegisterClass *
156 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
157 const TargetRegisterClass *B,
158 unsigned SubIdx) const {
163 if (B == &X86::GR8RegClass) {
164 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
166 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
167 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
168 A == &X86::GR64_NOREXRegClass ||
169 A == &X86::GR64_NOSPRegClass ||
170 A == &X86::GR64_NOREX_NOSPRegClass)
171 return &X86::GR64_ABCDRegClass;
172 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
173 A == &X86::GR32_NOREXRegClass ||
174 A == &X86::GR32_NOSPRegClass)
175 return &X86::GR32_ABCDRegClass;
176 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
177 A == &X86::GR16_NOREXRegClass)
178 return &X86::GR16_ABCDRegClass;
179 } else if (B == &X86::GR8_NOREXRegClass) {
180 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
181 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
182 return &X86::GR64_NOREXRegClass;
183 else if (A == &X86::GR64_ABCDRegClass)
184 return &X86::GR64_ABCDRegClass;
185 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
186 A == &X86::GR32_NOSPRegClass)
187 return &X86::GR32_NOREXRegClass;
188 else if (A == &X86::GR32_ABCDRegClass)
189 return &X86::GR32_ABCDRegClass;
190 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
191 return &X86::GR16_NOREXRegClass;
192 else if (A == &X86::GR16_ABCDRegClass)
193 return &X86::GR16_ABCDRegClass;
198 if (B == &X86::GR8_ABCD_HRegClass) {
199 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
200 A == &X86::GR64_NOREXRegClass ||
201 A == &X86::GR64_NOSPRegClass ||
202 A == &X86::GR64_NOREX_NOSPRegClass)
203 return &X86::GR64_ABCDRegClass;
204 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
205 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
206 return &X86::GR32_ABCDRegClass;
207 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
208 A == &X86::GR16_NOREXRegClass)
209 return &X86::GR16_ABCDRegClass;
214 if (B == &X86::GR16RegClass) {
215 if (A->getSize() == 4 || A->getSize() == 8)
217 } else if (B == &X86::GR16_ABCDRegClass) {
218 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
219 A == &X86::GR64_NOREXRegClass ||
220 A == &X86::GR64_NOSPRegClass ||
221 A == &X86::GR64_NOREX_NOSPRegClass)
222 return &X86::GR64_ABCDRegClass;
223 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
224 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
225 return &X86::GR32_ABCDRegClass;
226 } else if (B == &X86::GR16_NOREXRegClass) {
227 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
228 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
229 return &X86::GR64_NOREXRegClass;
230 else if (A == &X86::GR64_ABCDRegClass)
231 return &X86::GR64_ABCDRegClass;
232 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
233 A == &X86::GR32_NOSPRegClass)
234 return &X86::GR32_NOREXRegClass;
235 else if (A == &X86::GR32_ABCDRegClass)
236 return &X86::GR64_ABCDRegClass;
241 if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
242 if (A->getSize() == 8)
244 } else if (B == &X86::GR32_ABCDRegClass) {
245 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
246 A == &X86::GR64_NOREXRegClass ||
247 A == &X86::GR64_NOSPRegClass ||
248 A == &X86::GR64_NOREX_NOSPRegClass)
249 return &X86::GR64_ABCDRegClass;
250 } else if (B == &X86::GR32_NOREXRegClass) {
251 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
252 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
253 return &X86::GR64_NOREXRegClass;
254 else if (A == &X86::GR64_ABCDRegClass)
255 return &X86::GR64_ABCDRegClass;
262 const TargetRegisterClass *
263 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
265 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
266 case 0: // Normal GPRs.
267 if (TM.getSubtarget<X86Subtarget>().is64Bit())
268 return &X86::GR64RegClass;
269 return &X86::GR32RegClass;
270 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
271 if (TM.getSubtarget<X86Subtarget>().is64Bit())
272 return &X86::GR64_NOSPRegClass;
273 return &X86::GR32_NOSPRegClass;
277 const TargetRegisterClass *
278 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
279 if (RC == &X86::CCRRegClass) {
281 return &X86::GR64RegClass;
283 return &X86::GR32RegClass;
289 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
290 bool callsEHReturn = false;
293 const MachineFrameInfo *MFI = MF->getFrameInfo();
294 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
295 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
298 static const unsigned CalleeSavedRegs32Bit[] = {
299 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
302 static const unsigned CalleeSavedRegs32EHRet[] = {
303 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
306 static const unsigned CalleeSavedRegs64Bit[] = {
307 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
310 static const unsigned CalleeSavedRegs64EHRet[] = {
311 X86::RAX, X86::RDX, X86::RBX, X86::R12,
312 X86::R13, X86::R14, X86::R15, X86::RBP, 0
315 static const unsigned CalleeSavedRegsWin64[] = {
316 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
317 X86::R12, X86::R13, X86::R14, X86::R15,
318 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
319 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
320 X86::XMM14, X86::XMM15, 0
325 return CalleeSavedRegsWin64;
327 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
329 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
333 const TargetRegisterClass* const*
334 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
335 bool callsEHReturn = false;
338 const MachineFrameInfo *MFI = MF->getFrameInfo();
339 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
340 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
343 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
344 &X86::GR32RegClass, &X86::GR32RegClass,
345 &X86::GR32RegClass, &X86::GR32RegClass, 0
347 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
348 &X86::GR32RegClass, &X86::GR32RegClass,
349 &X86::GR32RegClass, &X86::GR32RegClass,
350 &X86::GR32RegClass, &X86::GR32RegClass, 0
352 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
353 &X86::GR64RegClass, &X86::GR64RegClass,
354 &X86::GR64RegClass, &X86::GR64RegClass,
355 &X86::GR64RegClass, &X86::GR64RegClass, 0
357 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
358 &X86::GR64RegClass, &X86::GR64RegClass,
359 &X86::GR64RegClass, &X86::GR64RegClass,
360 &X86::GR64RegClass, &X86::GR64RegClass,
361 &X86::GR64RegClass, &X86::GR64RegClass, 0
363 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
364 &X86::GR64RegClass, &X86::GR64RegClass,
365 &X86::GR64RegClass, &X86::GR64RegClass,
366 &X86::GR64RegClass, &X86::GR64RegClass,
367 &X86::GR64RegClass, &X86::GR64RegClass,
368 &X86::VR128RegClass, &X86::VR128RegClass,
369 &X86::VR128RegClass, &X86::VR128RegClass,
370 &X86::VR128RegClass, &X86::VR128RegClass,
371 &X86::VR128RegClass, &X86::VR128RegClass,
372 &X86::VR128RegClass, &X86::VR128RegClass, 0
377 return CalleeSavedRegClassesWin64;
379 return (callsEHReturn ?
380 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
382 return (callsEHReturn ?
383 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
387 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
388 BitVector Reserved(getNumRegs());
389 // Set the stack-pointer register and its aliases as reserved.
390 Reserved.set(X86::RSP);
391 Reserved.set(X86::ESP);
392 Reserved.set(X86::SP);
393 Reserved.set(X86::SPL);
395 // Set the instruction pointer register and its aliases as reserved.
396 Reserved.set(X86::RIP);
397 Reserved.set(X86::EIP);
398 Reserved.set(X86::IP);
400 // Set the frame-pointer register and its aliases as reserved if needed.
402 Reserved.set(X86::RBP);
403 Reserved.set(X86::EBP);
404 Reserved.set(X86::BP);
405 Reserved.set(X86::BPL);
408 // Mark the x87 stack registers as reserved, since they don't behave normally
409 // with respect to liveness. We don't fully model the effects of x87 stack
410 // pushes and pops after stackification.
411 Reserved.set(X86::ST0);
412 Reserved.set(X86::ST1);
413 Reserved.set(X86::ST2);
414 Reserved.set(X86::ST3);
415 Reserved.set(X86::ST4);
416 Reserved.set(X86::ST5);
417 Reserved.set(X86::ST6);
418 Reserved.set(X86::ST7);
422 //===----------------------------------------------------------------------===//
423 // Stack Frame Processing methods
424 //===----------------------------------------------------------------------===//
426 /// hasFP - Return true if the specified function should have a dedicated frame
427 /// pointer register. This is true if the function has variable sized allocas
428 /// or if frame pointer elimination is disabled.
429 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
430 const MachineFrameInfo *MFI = MF.getFrameInfo();
431 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
433 return (NoFramePointerElim ||
434 needsStackRealignment(MF) ||
435 MFI->hasVarSizedObjects() ||
436 MFI->isFrameAddressTaken() ||
437 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
438 (MMI && MMI->callsUnwindInit()));
441 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
442 const MachineFrameInfo *MFI = MF.getFrameInfo();
443 bool requiresRealignment =
444 RealignStack && (MFI->getMaxAlignment() > StackAlign);
446 // FIXME: Currently we don't support stack realignment for functions with
447 // variable-sized allocas.
448 // FIXME: Temporary disable the error - it seems to be too conservative.
449 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
451 "Stack realignment in presense of dynamic allocas is not supported");
453 return (requiresRealignment && !MFI->hasVarSizedObjects());
456 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
457 return !MF.getFrameInfo()->hasVarSizedObjects();
460 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
461 int &FrameIdx) const {
462 if (Reg == FramePtr && hasFP(MF)) {
463 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
470 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
471 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
472 MachineFrameInfo *MFI = MF.getFrameInfo();
473 int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
474 uint64_t StackSize = MFI->getStackSize();
476 if (needsStackRealignment(MF)) {
478 // Skip the saved EBP.
481 unsigned Align = MFI->getObjectAlignment(FI);
482 assert( (-(Offset + StackSize)) % Align == 0);
484 return Offset + StackSize;
486 // FIXME: Support tail calls
489 return Offset + StackSize;
491 // Skip the saved EBP.
494 // Skip the RETADDR move area
495 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
496 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
497 if (TailCallReturnAddrDelta < 0)
498 Offset -= TailCallReturnAddrDelta;
504 void X86RegisterInfo::
505 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
506 MachineBasicBlock::iterator I) const {
507 if (!hasReservedCallFrame(MF)) {
508 // If the stack pointer can be changed after prologue, turn the
509 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
510 // adjcallstackdown instruction into 'add ESP, <amt>'
511 // TODO: consider using push / pop instead of sub + store / add
512 MachineInstr *Old = I;
513 uint64_t Amount = Old->getOperand(0).getImm();
515 // We need to keep the stack aligned properly. To do this, we round the
516 // amount of space needed for the outgoing arguments up to the next
517 // alignment boundary.
518 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
520 MachineInstr *New = 0;
521 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
522 New = BuildMI(MF, Old->getDebugLoc(),
523 TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
528 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
530 // Factor out the amount the callee already popped.
531 uint64_t CalleeAmt = Old->getOperand(1).getImm();
535 unsigned Opc = (Amount < 128) ?
536 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
537 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
538 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
545 // The EFLAGS implicit def is dead.
546 New->getOperand(3).setIsDead();
548 // Replace the pseudo instruction with a new instruction.
552 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
553 // If we are performing frame pointer elimination and if the callee pops
554 // something off the stack pointer, add it back. We do this until we have
555 // more advanced stack pointer tracking ability.
556 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
557 unsigned Opc = (CalleeAmt < 128) ?
558 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
559 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
560 MachineInstr *Old = I;
562 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
567 // The EFLAGS implicit def is dead.
568 New->getOperand(3).setIsDead();
577 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
578 int SPAdj, int *Value,
579 RegScavenger *RS) const{
580 assert(SPAdj == 0 && "Unexpected");
583 MachineInstr &MI = *II;
584 MachineFunction &MF = *MI.getParent()->getParent();
586 while (!MI.getOperand(i).isFI()) {
588 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
591 int FrameIndex = MI.getOperand(i).getIndex();
594 // DEBUG_VALUE has a special representation, and is only robust enough to
595 // represent SP(or BP) +- offset addressing modes. We rewrite the
596 // FrameIndex to be a constant; implicitly positive constants are relative
597 // to ESP and negative ones to EBP.
598 if (MI.getOpcode()==TargetInstrInfo::DEBUG_VALUE) {
599 MI.getOperand(i).ChangeToImmediate(getFrameIndexOffset(MF, FrameIndex));
603 if (needsStackRealignment(MF))
604 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
606 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
608 // This must be part of a four operand memory reference. Replace the
609 // FrameIndex with base register with EBP. Add an offset to the offset.
610 MI.getOperand(i).ChangeToRegister(BasePtr, false);
612 // Now add the frame object offset to the offset from EBP.
613 if (MI.getOperand(i+3).isImm()) {
614 // Offset is a 32-bit integer.
615 int Offset = getFrameIndexOffset(MF, FrameIndex) +
616 (int)(MI.getOperand(i + 3).getImm());
618 MI.getOperand(i + 3).ChangeToImmediate(Offset);
620 // Offset is symbolic. This is extremely rare.
621 uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
622 (uint64_t)MI.getOperand(i+3).getOffset();
623 MI.getOperand(i+3).setOffset(Offset);
629 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
630 RegScavenger *RS) const {
631 MachineFrameInfo *MFI = MF.getFrameInfo();
633 // Calculate and set max stack object alignment early, so we can decide
634 // whether we will need stack realignment (and thus FP).
635 MFI->calculateMaxStackAlignment();
637 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
638 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
640 if (TailCallReturnAddrDelta < 0) {
641 // create RETURNADDR area
650 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
651 (-1U*SlotSize)+TailCallReturnAddrDelta,
656 assert((TailCallReturnAddrDelta <= 0) &&
657 "The Delta should always be zero or negative");
658 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
660 // Create a frame entry for the EBP register that must be saved.
661 int FrameIdx = MFI->CreateFixedObject(SlotSize,
663 TFI.getOffsetOfLocalArea() +
664 TailCallReturnAddrDelta,
666 assert(FrameIdx == MFI->getObjectIndexBegin() &&
667 "Slot for EBP register must be last in order to be found!");
672 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
673 /// stack pointer by a constant value.
675 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
676 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
677 const TargetInstrInfo &TII) {
678 bool isSub = NumBytes < 0;
679 uint64_t Offset = isSub ? -NumBytes : NumBytes;
682 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
683 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
685 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
686 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
687 uint64_t Chunk = (1LL << 31) - 1;
688 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
689 DebugLoc::getUnknownLoc());
692 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
694 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
697 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
702 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
704 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
705 unsigned StackPtr, uint64_t *NumBytes = NULL) {
706 if (MBBI == MBB.begin()) return;
708 MachineBasicBlock::iterator PI = prior(MBBI);
709 unsigned Opc = PI->getOpcode();
710 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
711 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
712 PI->getOperand(0).getReg() == StackPtr) {
714 *NumBytes += PI->getOperand(2).getImm();
716 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
717 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
718 PI->getOperand(0).getReg() == StackPtr) {
720 *NumBytes -= PI->getOperand(2).getImm();
725 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
727 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
728 MachineBasicBlock::iterator &MBBI,
729 unsigned StackPtr, uint64_t *NumBytes = NULL) {
730 // FIXME: THIS ISN'T RUN!!!
733 if (MBBI == MBB.end()) return;
735 MachineBasicBlock::iterator NI = llvm::next(MBBI);
736 if (NI == MBB.end()) return;
738 unsigned Opc = NI->getOpcode();
739 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
740 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
741 NI->getOperand(0).getReg() == StackPtr) {
743 *NumBytes -= NI->getOperand(2).getImm();
746 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
747 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
748 NI->getOperand(0).getReg() == StackPtr) {
750 *NumBytes += NI->getOperand(2).getImm();
756 /// mergeSPUpdates - Checks the instruction before/after the passed
757 /// instruction. If it is an ADD/SUB instruction it is deleted argument and the
758 /// stack adjustment is returned as a positive value for ADD and a negative for
760 static int mergeSPUpdates(MachineBasicBlock &MBB,
761 MachineBasicBlock::iterator &MBBI,
763 bool doMergeWithPrevious) {
764 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
765 (!doMergeWithPrevious && MBBI == MBB.end()))
768 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
769 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
770 unsigned Opc = PI->getOpcode();
773 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
774 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
775 PI->getOperand(0).getReg() == StackPtr){
776 Offset += PI->getOperand(2).getImm();
778 if (!doMergeWithPrevious) MBBI = NI;
779 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
780 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
781 PI->getOperand(0).getReg() == StackPtr) {
782 Offset -= PI->getOperand(2).getImm();
784 if (!doMergeWithPrevious) MBBI = NI;
790 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
792 unsigned FramePtr) const {
793 MachineFrameInfo *MFI = MF.getFrameInfo();
794 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
797 // Add callee saved registers to move list.
798 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
799 if (CSI.empty()) return;
801 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
802 const TargetData *TD = MF.getTarget().getTargetData();
803 bool HasFP = hasFP(MF);
805 // Calculate amount of bytes used for return address storing.
807 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
808 TargetFrameInfo::StackGrowsUp ?
809 TD->getPointerSize() : -TD->getPointerSize());
811 // FIXME: This is dirty hack. The code itself is pretty mess right now.
812 // It should be rewritten from scratch and generalized sometimes.
814 // Determine maximum offset (minumum due to stack growth).
815 int64_t MaxOffset = 0;
816 for (std::vector<CalleeSavedInfo>::const_iterator
817 I = CSI.begin(), E = CSI.end(); I != E; ++I)
818 MaxOffset = std::min(MaxOffset,
819 MFI->getObjectOffset(I->getFrameIdx()));
821 // Calculate offsets.
822 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
823 for (std::vector<CalleeSavedInfo>::const_iterator
824 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
825 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
826 unsigned Reg = I->getReg();
827 Offset = MaxOffset - Offset + saveAreaOffset;
829 // Don't output a new machine move if we're re-saving the frame
830 // pointer. This happens when the PrologEpilogInserter has inserted an extra
831 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
832 // generates one when frame pointers are used. If we generate a "machine
833 // move" for this extra "PUSH", the linker will lose track of the fact that
834 // the frame pointer should have the value of the first "PUSH" when it's
837 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
838 // another bug. I.e., one where we generate a prolog like this:
846 // The immediate re-push of EBP is unnecessary. At the least, it's an
847 // optimization bug. EBP can be used as a scratch register in certain
848 // cases, but probably not when we have a frame pointer.
849 if (HasFP && FramePtr == Reg)
852 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
853 MachineLocation CSSrc(Reg);
854 Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
858 /// emitPrologue - Push callee-saved registers onto the stack, which
859 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
860 /// space for local variables. Also emit labels used by the exception handler to
861 /// generate the exception handling frames.
862 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
863 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
864 MachineBasicBlock::iterator MBBI = MBB.begin();
865 MachineFrameInfo *MFI = MF.getFrameInfo();
866 const Function *Fn = MF.getFunction();
867 const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
868 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
869 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
870 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
871 !Fn->doesNotThrow() || UnwindTablesMandatory;
872 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
873 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
874 bool HasFP = hasFP(MF);
877 // Add RETADDR move area to callee saved frame size.
878 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
879 if (TailCallReturnAddrDelta < 0)
880 X86FI->setCalleeSavedFrameSize(
881 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
883 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
884 // function, and use up to 128 bytes of stack space, don't have a frame
885 // pointer, calls, or dynamic alloca then we do not need to adjust the
886 // stack pointer (we fit in the Red Zone).
887 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
888 !needsStackRealignment(MF) &&
889 !MFI->hasVarSizedObjects() && // No dynamic alloca.
890 !MFI->hasCalls() && // No calls.
891 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
892 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
893 if (HasFP) MinSize += SlotSize;
894 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
895 MFI->setStackSize(StackSize);
896 } else if (Subtarget->isTargetWin64()) {
897 // We need to always allocate 32 bytes as register spill area.
898 // FIXME: We might reuse these 32 bytes for leaf functions.
900 MFI->setStackSize(StackSize);
903 // Insert stack pointer adjustment for later moving of return addr. Only
904 // applies to tail call optimized functions where the callee argument stack
905 // size is bigger than the callers.
906 if (TailCallReturnAddrDelta < 0) {
908 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
911 .addImm(-TailCallReturnAddrDelta);
912 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
915 // Mapping for machine moves:
917 // DST: VirtualFP AND
918 // SRC: VirtualFP => DW_CFA_def_cfa_offset
919 // ELSE => DW_CFA_def_cfa
921 // SRC: VirtualFP AND
922 // DST: Register => DW_CFA_def_cfa_register
925 // OFFSET < 0 => DW_CFA_offset_extended_sf
926 // REG < 64 => DW_CFA_offset + Reg
927 // ELSE => DW_CFA_offset_extended
929 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
930 const TargetData *TD = MF.getTarget().getTargetData();
931 uint64_t NumBytes = 0;
933 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
934 TargetFrameInfo::StackGrowsUp ?
935 TD->getPointerSize() : -TD->getPointerSize());
938 // Calculate required stack adjustment.
939 uint64_t FrameSize = StackSize - SlotSize;
940 if (needsStackRealignment(MF))
941 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
943 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
945 // Get the offset of the stack slot for the EBP register, which is
946 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
947 // Update the frame offset adjustment.
948 MFI->setOffsetAdjustment(-NumBytes);
950 // Save EBP/RBP into the appropriate stack slot.
951 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
952 .addReg(FramePtr, RegState::Kill);
954 if (needsFrameMoves) {
955 // Mark the place where EBP/RBP was saved.
956 unsigned FrameLabelId = MMI->NextLabelID();
957 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
959 // Define the current CFA rule to use the provided offset.
961 MachineLocation SPDst(MachineLocation::VirtualFP);
962 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
963 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
965 // FIXME: Verify & implement for FP
966 MachineLocation SPDst(StackPtr);
967 MachineLocation SPSrc(StackPtr, stackGrowth);
968 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
971 // Change the rule for the FramePtr to be an "offset" rule.
972 MachineLocation FPDst(MachineLocation::VirtualFP,
974 MachineLocation FPSrc(FramePtr);
975 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
978 // Update EBP with the new base value...
979 BuildMI(MBB, MBBI, DL,
980 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
983 if (needsFrameMoves) {
984 // Mark effective beginning of when frame pointer becomes valid.
985 unsigned FrameLabelId = MMI->NextLabelID();
986 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
988 // Define the current CFA to use the EBP/RBP register.
989 MachineLocation FPDst(FramePtr);
990 MachineLocation FPSrc(MachineLocation::VirtualFP);
991 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
994 // Mark the FramePtr as live-in in every block except the entry.
995 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
997 I->addLiveIn(FramePtr);
1000 if (needsStackRealignment(MF)) {
1002 BuildMI(MBB, MBBI, DL,
1003 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1004 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1006 // The EFLAGS implicit def is dead.
1007 MI->getOperand(3).setIsDead();
1010 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1013 // Skip the callee-saved push instructions.
1014 bool PushedRegs = false;
1015 int StackOffset = 2 * stackGrowth;
1017 while (MBBI != MBB.end() &&
1018 (MBBI->getOpcode() == X86::PUSH32r ||
1019 MBBI->getOpcode() == X86::PUSH64r)) {
1023 if (!HasFP && needsFrameMoves) {
1024 // Mark callee-saved push instruction.
1025 unsigned LabelId = MMI->NextLabelID();
1026 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1028 // Define the current CFA rule to use the provided offset.
1029 unsigned Ptr = StackSize ?
1030 MachineLocation::VirtualFP : StackPtr;
1031 MachineLocation SPDst(Ptr);
1032 MachineLocation SPSrc(Ptr, StackOffset);
1033 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1034 StackOffset += stackGrowth;
1038 if (MBBI != MBB.end())
1039 DL = MBBI->getDebugLoc();
1041 // Adjust stack pointer: ESP -= numbytes.
1042 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1043 // Check, whether EAX is livein for this function.
1044 bool isEAXAlive = false;
1045 for (MachineRegisterInfo::livein_iterator
1046 II = MF.getRegInfo().livein_begin(),
1047 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1048 unsigned Reg = II->first;
1049 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1050 Reg == X86::AH || Reg == X86::AL);
1053 // Function prologue calls _alloca to probe the stack when allocating more
1054 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1055 // to ensure that the guard pages used by the OS virtual memory manager are
1056 // allocated in correct sequence.
1058 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1060 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1061 .addExternalSymbol("_alloca");
1064 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1065 .addReg(X86::EAX, RegState::Kill);
1067 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1068 // allocated bytes for EAX.
1069 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1070 .addImm(NumBytes - 4);
1071 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1072 .addExternalSymbol("_alloca");
1075 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1077 StackPtr, false, NumBytes - 4);
1078 MBB.insert(MBBI, MI);
1080 } else if (NumBytes) {
1081 // If there is an SUB32ri of ESP immediately before this instruction, merge
1082 // the two. This can be the case when tail call elimination is enabled and
1083 // the callee has more arguments then the caller.
1084 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1086 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1087 // instruction, merge the two instructions.
1088 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1091 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1094 if ((NumBytes || PushedRegs) && needsFrameMoves) {
1095 // Mark end of stack pointer adjustment.
1096 unsigned LabelId = MMI->NextLabelID();
1097 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1099 if (!HasFP && NumBytes) {
1100 // Define the current CFA rule to use the provided offset.
1102 MachineLocation SPDst(MachineLocation::VirtualFP);
1103 MachineLocation SPSrc(MachineLocation::VirtualFP,
1104 -StackSize + stackGrowth);
1105 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1107 // FIXME: Verify & implement for FP
1108 MachineLocation SPDst(StackPtr);
1109 MachineLocation SPSrc(StackPtr, stackGrowth);
1110 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1114 // Emit DWARF info specifying the offsets of the callee-saved registers.
1116 emitCalleeSavedFrameMoves(MF, LabelId, HasFP ? FramePtr : StackPtr);
1120 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1121 MachineBasicBlock &MBB) const {
1122 const MachineFrameInfo *MFI = MF.getFrameInfo();
1123 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1124 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1125 unsigned RetOpcode = MBBI->getOpcode();
1126 DebugLoc DL = MBBI->getDebugLoc();
1128 switch (RetOpcode) {
1130 llvm_unreachable("Can only insert epilog into returning blocks");
1133 case X86::TCRETURNdi:
1134 case X86::TCRETURNri:
1135 case X86::TCRETURNri64:
1136 case X86::TCRETURNdi64:
1137 case X86::EH_RETURN:
1138 case X86::EH_RETURN64:
1142 break; // These are ok
1145 // Get the number of bytes to allocate from the FrameInfo.
1146 uint64_t StackSize = MFI->getStackSize();
1147 uint64_t MaxAlign = MFI->getMaxAlignment();
1148 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1149 uint64_t NumBytes = 0;
1152 // Calculate required stack adjustment.
1153 uint64_t FrameSize = StackSize - SlotSize;
1154 if (needsStackRealignment(MF))
1155 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1157 NumBytes = FrameSize - CSSize;
1160 BuildMI(MBB, MBBI, DL,
1161 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1163 NumBytes = StackSize - CSSize;
1166 // Skip the callee-saved pop instructions.
1167 MachineBasicBlock::iterator LastCSPop = MBBI;
1168 while (MBBI != MBB.begin()) {
1169 MachineBasicBlock::iterator PI = prior(MBBI);
1170 unsigned Opc = PI->getOpcode();
1172 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1173 !PI->getDesc().isTerminator())
1179 DL = MBBI->getDebugLoc();
1181 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1182 // instruction, merge the two instructions.
1183 if (NumBytes || MFI->hasVarSizedObjects())
1184 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1186 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1187 // slot before popping them off! Same applies for the case, when stack was
1189 if (needsStackRealignment(MF)) {
1190 // We cannot use LEA here, because stack pointer was realigned. We need to
1191 // deallocate local frame back.
1193 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1194 MBBI = prior(LastCSPop);
1197 BuildMI(MBB, MBBI, DL,
1198 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1199 StackPtr).addReg(FramePtr);
1200 } else if (MFI->hasVarSizedObjects()) {
1202 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1204 addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1205 FramePtr, false, -CSSize);
1206 MBB.insert(MBBI, MI);
1208 BuildMI(MBB, MBBI, DL,
1209 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1212 } else if (NumBytes) {
1213 // Adjust stack pointer back: ESP += numbytes.
1214 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1217 // We're returning from function via eh_return.
1218 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1219 MBBI = prior(MBB.end());
1220 MachineOperand &DestAddr = MBBI->getOperand(0);
1221 assert(DestAddr.isReg() && "Offset should be in register!");
1222 BuildMI(MBB, MBBI, DL,
1223 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1224 StackPtr).addReg(DestAddr.getReg());
1225 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1226 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1227 // Tail call return: adjust the stack pointer and jump to callee.
1228 MBBI = prior(MBB.end());
1229 MachineOperand &JumpTarget = MBBI->getOperand(0);
1230 MachineOperand &StackAdjust = MBBI->getOperand(1);
1231 assert(StackAdjust.isImm() && "Expecting immediate value.");
1233 // Adjust stack pointer.
1234 int StackAdj = StackAdjust.getImm();
1235 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1237 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1239 // Incoporate the retaddr area.
1240 Offset = StackAdj-MaxTCDelta;
1241 assert(Offset >= 0 && "Offset should never be negative");
1244 // Check for possible merge with preceeding ADD instruction.
1245 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1246 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1249 // Jump to label or value in register.
1250 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1251 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1252 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1253 else if (RetOpcode== X86::TCRETURNri64)
1254 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1256 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1258 // Delete the pseudo instruction TCRETURN.
1260 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1261 (X86FI->getTCReturnAddrDelta() < 0)) {
1262 // Add the return addr area delta back since we are not tail calling.
1263 int delta = -1*X86FI->getTCReturnAddrDelta();
1264 MBBI = prior(MBB.end());
1266 // Check for possible merge with preceeding ADD instruction.
1267 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1268 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1272 unsigned X86RegisterInfo::getRARegister() const {
1273 return Is64Bit ? X86::RIP // Should have dwarf #16.
1274 : X86::EIP; // Should have dwarf #8.
1277 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1278 return hasFP(MF) ? FramePtr : StackPtr;
1282 X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1283 // Calculate amount of bytes used for return address storing
1284 int stackGrowth = (Is64Bit ? -8 : -4);
1286 // Initial state of the frame pointer is esp+4.
1287 MachineLocation Dst(MachineLocation::VirtualFP);
1288 MachineLocation Src(StackPtr, stackGrowth);
1289 Moves.push_back(MachineMove(0, Dst, Src));
1291 // Add return address to move list
1292 MachineLocation CSDst(StackPtr, stackGrowth);
1293 MachineLocation CSSrc(getRARegister());
1294 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1297 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1298 llvm_unreachable("What is the exception register");
1302 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1303 llvm_unreachable("What is the exception handler register");
1308 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1309 switch (VT.getSimpleVT().SimpleTy) {
1310 default: return Reg;
1315 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1317 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1319 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1321 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1327 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1329 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1331 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1333 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1335 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1337 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1339 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1341 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1343 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1345 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1347 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1349 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1351 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1353 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1355 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1357 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1363 default: return Reg;
1364 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1366 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1368 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1370 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1372 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1374 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1376 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1378 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1380 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1382 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1384 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1386 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1388 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1390 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1392 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1394 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1399 default: return Reg;
1400 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1402 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1404 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1406 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1408 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1410 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1412 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1414 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1416 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1418 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1420 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1422 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1424 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1426 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1428 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1430 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1435 default: return Reg;
1436 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1438 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1440 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1442 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1444 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1446 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1448 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1450 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1452 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1454 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1456 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1458 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1460 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1462 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1464 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1466 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1475 #include "X86GenRegisterInfo.inc"