1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86SelectionDAGInfo.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
24 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
25 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
26 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
27 #include "llvm/CodeGen/TargetSubtargetInfo.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/MC/MCInstrItineraries.h"
30 #include "llvm/Target/TargetMachine.h"
33 #define GET_SUBTARGETINFO_HEADER
34 #include "X86GenSubtargetInfo.inc"
40 /// The X86 backend supports a number of different styles of PIC.
45 StubPIC, // Used on i386-darwin in pic mode.
46 GOT, // Used on 32 bit elf on when in pic mode.
47 RIPRel, // Used on X86-64 when in pic mode.
48 None // Set when not in pic mode.
51 } // end namespace PICStyles
53 class X86Subtarget final : public X86GenSubtargetInfo {
55 enum X86ProcFamilyEnum {
71 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
75 NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
78 /// X86 processor family: Intel Atom, and others
79 X86ProcFamilyEnum X86ProcFamily;
81 /// Which PIC style to use
82 PICStyles::Style PICStyle;
84 const TargetMachine &TM;
86 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
87 X86SSEEnum X86SSELevel;
89 /// MMX, 3DNow, 3DNow Athlon, or none supported.
90 X863DNowEnum X863DNowLevel;
92 /// True if the processor supports X87 instructions.
95 /// True if this processor has conditional move instructions
96 /// (generally pentium pro+).
99 /// True if the processor supports X86-64 instructions.
102 /// True if the processor supports POPCNT.
105 /// True if the processor supports SSE4A instructions.
108 /// Target has AES instructions
112 /// Target has FXSAVE/FXRESTOR instructions
115 /// Target has XSAVE instructions
118 /// Target has XSAVEOPT instructions
121 /// Target has XSAVEC instructions
124 /// Target has XSAVES instructions
127 /// Target has carry-less multiplication
131 /// Target has Galois Field Arithmetic instructions
134 /// Target has 3-operand fused multiply-add
137 /// Target has 4-operand fused multiply-add
140 /// Target has XOP instructions
143 /// Target has TBM instructions.
146 /// Target has LWP instructions
149 /// True if the processor has the MOVBE instruction.
152 /// True if the processor has the RDRAND instruction.
155 /// Processor has 16-bit floating point conversion instructions.
158 /// Processor has FS/GS base insturctions.
161 /// Processor has LZCNT instruction.
164 /// Processor has BMI1 instructions.
167 /// Processor has BMI2 instructions.
170 /// Processor has VBMI instructions.
173 /// Processor has VBMI2 instructions.
176 /// Processor has Integer Fused Multiply Add
179 /// Processor has RTM instructions.
182 /// Processor has ADX instructions.
185 /// Processor has SHA instructions.
188 /// Processor has PRFCHW instructions.
191 /// Processor has RDSEED instructions.
194 /// Processor has LAHF/SAHF instructions.
197 /// Processor has MONITORX/MWAITX instructions.
200 /// Processor has Cache Line Zero instruction
203 /// Processor has Prefetch with intent to Write instruction
206 /// True if SHLD instructions are slow.
209 /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
213 /// True if unaligned memory accesses of 16-bytes are slow.
216 /// True if unaligned memory accesses of 32-bytes are slow.
219 /// True if SSE operations can have unaligned memory operands.
220 /// This may require setting a configuration bit in the processor.
221 bool HasSSEUnalignedMem;
223 /// True if this processor has the CMPXCHG16B instruction;
224 /// this is true for most x86-64 chips, but not the first AMD chips.
227 /// True if the LEA instruction should be used for adjusting
228 /// the stack pointer. This is an optimization for Intel Atom processors.
231 /// True if its preferable to combine to a single shuffle using a variable
232 /// mask over multiple fixed shuffles.
233 bool HasFastVariableShuffle;
235 /// True if there is no performance penalty to writing only the lower parts
236 /// of a YMM or ZMM register without clearing the upper part.
237 bool HasFastPartialYMMorZMMWrite;
239 /// True if gather is reasonably fast. This is true for Skylake client and
240 /// all AVX-512 CPUs.
243 /// True if hardware SQRTSS instruction is at least as fast (latency) as
244 /// RSQRTSS followed by a Newton-Raphson iteration.
245 bool HasFastScalarFSQRT;
247 /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
248 /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
249 bool HasFastVectorFSQRT;
251 /// True if 8-bit divisions are significantly faster than
252 /// 32-bit divisions and should be used when possible.
253 bool HasSlowDivide32;
255 /// True if 32-bit divides are significantly faster than
256 /// 64-bit divisions and should be used when possible.
257 bool HasSlowDivide64;
259 /// True if LZCNT instruction is fast.
262 /// True if SHLD based rotate is fast.
263 bool HasFastSHLDRotate;
265 /// True if the processor supports macrofusion.
268 /// True if the processor has enhanced REP MOVSB/STOSB.
271 /// True if the short functions should be padded to prevent
272 /// a stall when returning too early.
273 bool PadShortFunctions;
275 /// True if two memory operand instructions should use a temporary register
279 /// True if the LEA instruction inputs have to be ready at address generation
283 /// True if the LEA instruction with certain arguments is slow
286 /// True if the LEA instruction has all three source operands: base, index,
287 /// and offset or if the LEA instruction uses base and index registers where
288 /// the base is EBP, RBP,or R13
291 /// True if INC and DEC instructions are slow when writing to flags
294 /// Processor has AVX-512 PreFetch Instructions
297 /// Processor has AVX-512 Exponential and Reciprocal Instructions
300 /// Processor has AVX-512 Conflict Detection Instructions
303 /// Processor has AVX-512 population count Instructions
306 /// Processor has AVX-512 Doubleword and Quadword instructions
309 /// Processor has AVX-512 Byte and Word instructions
312 /// Processor has AVX-512 Vector Length eXtenstions
315 /// Processor has PKU extenstions
318 /// Processor has AVX-512 Vector Neural Network Instructions
321 /// Processor has AVX-512 Bit Algorithms instructions
324 /// Processor supports MPX - Memory Protection Extensions
327 /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
328 /// using Shadow Stack
331 /// Processor supports CET IBT - Control-Flow Enforcement Technology
332 /// using Indirect Branch Tracking
335 /// Processor has Software Guard Extensions
338 /// Processor supports Flush Cache Line instruction
341 /// Processor supports Cache Line Write Back instruction
344 /// Use software floating point for code generation.
347 /// The minimum alignment known to hold of the stack frame on
348 /// entry to the function and which must be maintained by every function.
349 unsigned stackAlignment;
351 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
353 unsigned MaxInlineSizeThreshold;
355 /// What processor and OS we're targeting.
358 /// Instruction itineraries for scheduling
359 InstrItineraryData InstrItins;
361 /// GlobalISel related APIs.
362 std::unique_ptr<CallLowering> CallLoweringInfo;
363 std::unique_ptr<LegalizerInfo> Legalizer;
364 std::unique_ptr<RegisterBankInfo> RegBankInfo;
365 std::unique_ptr<InstructionSelector> InstSelector;
368 /// Override the stack alignment.
369 unsigned StackAlignOverride;
371 /// True if compiling for 64-bit, false for 16-bit or 32-bit.
374 /// True if compiling for 32-bit, false for 16-bit or 64-bit.
377 /// True if compiling for 16-bit, false for 32-bit or 64-bit.
380 /// Contains the Overhead of gather\scatter instructions
384 X86SelectionDAGInfo TSInfo;
385 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
386 // X86TargetLowering needs.
387 X86InstrInfo InstrInfo;
388 X86TargetLowering TLInfo;
389 X86FrameLowering FrameLowering;
392 /// This constructor initializes the data members to match that
393 /// of the specified triple.
395 X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
396 const X86TargetMachine &TM, unsigned StackAlignOverride);
398 const X86TargetLowering *getTargetLowering() const override {
402 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
404 const X86FrameLowering *getFrameLowering() const override {
405 return &FrameLowering;
408 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
412 const X86RegisterInfo *getRegisterInfo() const override {
413 return &getInstrInfo()->getRegisterInfo();
416 /// Returns the minimum alignment known to hold of the
417 /// stack frame on entry to the function and which must be maintained by every
418 /// function for this subtarget.
419 unsigned getStackAlignment() const { return stackAlignment; }
421 /// Returns the maximum memset / memcpy size
422 /// that still makes it profitable to inline the call.
423 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
425 /// ParseSubtargetFeatures - Parses features string setting specified
426 /// subtarget options. Definition of function is auto generated by tblgen.
427 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
429 /// Methods used by Global ISel
430 const CallLowering *getCallLowering() const override;
431 const InstructionSelector *getInstructionSelector() const override;
432 const LegalizerInfo *getLegalizerInfo() const override;
433 const RegisterBankInfo *getRegBankInfo() const override;
436 /// Initialize the full set of dependencies so we can use an initializer
437 /// list for X86Subtarget.
438 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
439 void initializeEnvironment();
440 void initSubtargetFeatures(StringRef CPU, StringRef FS);
443 /// Is this x86_64? (disregarding specific ABI / programming model)
444 bool is64Bit() const {
448 bool is32Bit() const {
452 bool is16Bit() const {
456 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
457 bool isTarget64BitILP32() const {
458 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
459 TargetTriple.isOSNaCl());
462 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
463 bool isTarget64BitLP64() const {
464 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
465 !TargetTriple.isOSNaCl());
468 PICStyles::Style getPICStyle() const { return PICStyle; }
469 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
471 bool hasX87() const { return HasX87; }
472 bool hasCMov() const { return HasCMov; }
473 bool hasSSE1() const { return X86SSELevel >= SSE1; }
474 bool hasSSE2() const { return X86SSELevel >= SSE2; }
475 bool hasSSE3() const { return X86SSELevel >= SSE3; }
476 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
477 bool hasSSE41() const { return X86SSELevel >= SSE41; }
478 bool hasSSE42() const { return X86SSELevel >= SSE42; }
479 bool hasAVX() const { return X86SSELevel >= AVX; }
480 bool hasAVX2() const { return X86SSELevel >= AVX2; }
481 bool hasAVX512() const { return X86SSELevel >= AVX512F; }
482 bool hasFp256() const { return hasAVX(); }
483 bool hasInt256() const { return hasAVX2(); }
484 bool hasSSE4A() const { return HasSSE4A; }
485 bool hasMMX() const { return X863DNowLevel >= MMX; }
486 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
487 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
488 bool hasPOPCNT() const { return HasPOPCNT; }
489 bool hasAES() const { return HasAES; }
490 bool hasVAES() const { return HasVAES; }
491 bool hasFXSR() const { return HasFXSR; }
492 bool hasXSAVE() const { return HasXSAVE; }
493 bool hasXSAVEOPT() const { return HasXSAVEOPT; }
494 bool hasXSAVEC() const { return HasXSAVEC; }
495 bool hasXSAVES() const { return HasXSAVES; }
496 bool hasPCLMUL() const { return HasPCLMUL; }
497 bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; }
498 bool hasGFNI() const { return HasGFNI; }
499 // Prefer FMA4 to FMA - its better for commutation/memory folding and
500 // has equal or better performance on all supported targets.
501 bool hasFMA() const { return HasFMA; }
502 bool hasFMA4() const { return HasFMA4; }
503 bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
504 bool hasXOP() const { return HasXOP; }
505 bool hasTBM() const { return HasTBM; }
506 bool hasLWP() const { return HasLWP; }
507 bool hasMOVBE() const { return HasMOVBE; }
508 bool hasRDRAND() const { return HasRDRAND; }
509 bool hasF16C() const { return HasF16C; }
510 bool hasFSGSBase() const { return HasFSGSBase; }
511 bool hasLZCNT() const { return HasLZCNT; }
512 bool hasBMI() const { return HasBMI; }
513 bool hasBMI2() const { return HasBMI2; }
514 bool hasVBMI() const { return HasVBMI; }
515 bool hasVBMI2() const { return HasVBMI2; }
516 bool hasIFMA() const { return HasIFMA; }
517 bool hasRTM() const { return HasRTM; }
518 bool hasADX() const { return HasADX; }
519 bool hasSHA() const { return HasSHA; }
520 bool hasPRFCHW() const { return HasPRFCHW || HasPREFETCHWT1; }
521 bool hasPREFETCHWT1() const { return HasPREFETCHWT1; }
522 bool hasSSEPrefetch() const {
523 // We implicitly enable these when we have a write prefix supporting cache
524 // level OR if we have prfchw, but don't already have a read prefetch from
526 return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1();
528 bool hasRDSEED() const { return HasRDSEED; }
529 bool hasLAHFSAHF() const { return HasLAHFSAHF; }
530 bool hasMWAITX() const { return HasMWAITX; }
531 bool hasCLZERO() const { return HasCLZERO; }
532 bool isSHLDSlow() const { return IsSHLDSlow; }
533 bool isPMULLDSlow() const { return IsPMULLDSlow; }
534 bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
535 bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
536 int getGatherOverhead() const { return GatherOverhead; }
537 int getScatterOverhead() const { return ScatterOverhead; }
538 bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
539 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
540 bool useLeaForSP() const { return UseLeaForSP; }
541 bool hasFastVariableShuffle() const {
542 return HasFastVariableShuffle;
544 bool hasFastPartialYMMorZMMWrite() const {
545 return HasFastPartialYMMorZMMWrite;
547 bool hasFastGather() const { return HasFastGather; }
548 bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
549 bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
550 bool hasFastLZCNT() const { return HasFastLZCNT; }
551 bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
552 bool hasMacroFusion() const { return HasMacroFusion; }
553 bool hasERMSB() const { return HasERMSB; }
554 bool hasSlowDivide32() const { return HasSlowDivide32; }
555 bool hasSlowDivide64() const { return HasSlowDivide64; }
556 bool padShortFunctions() const { return PadShortFunctions; }
557 bool slowTwoMemOps() const { return SlowTwoMemOps; }
558 bool LEAusesAG() const { return LEAUsesAG; }
559 bool slowLEA() const { return SlowLEA; }
560 bool slow3OpsLEA() const { return Slow3OpsLEA; }
561 bool slowIncDec() const { return SlowIncDec; }
562 bool hasCDI() const { return HasCDI; }
563 bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
564 bool hasPFI() const { return HasPFI; }
565 bool hasERI() const { return HasERI; }
566 bool hasDQI() const { return HasDQI; }
567 bool hasBWI() const { return HasBWI; }
568 bool hasVLX() const { return HasVLX; }
569 bool hasPKU() const { return HasPKU; }
570 bool hasVNNI() const { return HasVNNI; }
571 bool hasBITALG() const { return HasBITALG; }
572 bool hasMPX() const { return HasMPX; }
573 bool hasSHSTK() const { return HasSHSTK; }
574 bool hasIBT() const { return HasIBT; }
575 bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
576 bool hasCLWB() const { return HasCLWB; }
578 bool isXRaySupported() const override { return is64Bit(); }
580 X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; }
582 /// TODO: to be removed later and replaced with suitable properties
583 bool isAtom() const { return X86ProcFamily == IntelAtom; }
584 bool isSLM() const { return X86ProcFamily == IntelSLM; }
585 bool useSoftFloat() const { return UseSoftFloat; }
587 /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
588 /// no-sse2). There isn't any reason to disable it if the target processor
590 bool hasMFence() const { return hasSSE2() || is64Bit(); }
592 const Triple &getTargetTriple() const { return TargetTriple; }
594 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
595 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
596 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
597 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
598 bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
600 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
601 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
602 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
604 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
605 bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
606 bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
607 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
608 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
609 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
610 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
611 bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
612 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
614 bool isTargetWindowsMSVC() const {
615 return TargetTriple.isWindowsMSVCEnvironment();
618 bool isTargetKnownWindowsMSVC() const {
619 return TargetTriple.isKnownWindowsMSVCEnvironment();
622 bool isTargetWindowsCoreCLR() const {
623 return TargetTriple.isWindowsCoreCLREnvironment();
626 bool isTargetWindowsCygwin() const {
627 return TargetTriple.isWindowsCygwinEnvironment();
630 bool isTargetWindowsGNU() const {
631 return TargetTriple.isWindowsGNUEnvironment();
634 bool isTargetWindowsItanium() const {
635 return TargetTriple.isWindowsItaniumEnvironment();
638 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
640 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
642 bool isTargetWin64() const { return In64BitMode && isOSWindows(); }
644 bool isTargetWin32() const { return !In64BitMode && isOSWindows(); }
646 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
647 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
649 bool isPICStyleStubPIC() const {
650 return PICStyle == PICStyles::StubPIC;
653 bool isPositionIndependent() const { return TM.isPositionIndependent(); }
655 bool isCallingConvWin64(CallingConv::ID CC) const {
657 // On Win64, all these conventions just use the default convention.
659 case CallingConv::Fast:
660 case CallingConv::Swift:
661 case CallingConv::X86_FastCall:
662 case CallingConv::X86_StdCall:
663 case CallingConv::X86_ThisCall:
664 case CallingConv::X86_VectorCall:
665 case CallingConv::Intel_OCL_BI:
666 return isTargetWin64();
667 // This convention allows using the Win64 convention on other targets.
668 case CallingConv::Win64:
670 // This convention allows using the SysV convention on Windows targets.
671 case CallingConv::X86_64_SysV:
673 // Otherwise, who knows what this is.
679 /// Classify a global variable reference for the current subtarget according
680 /// to how we should reference it in a non-pcrel context.
681 unsigned char classifyLocalReference(const GlobalValue *GV) const;
683 unsigned char classifyGlobalReference(const GlobalValue *GV,
684 const Module &M) const;
685 unsigned char classifyGlobalReference(const GlobalValue *GV) const;
687 /// Classify a global function reference for the current subtarget.
688 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
689 const Module &M) const;
690 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
692 /// Classify a blockaddress reference for the current subtarget according to
693 /// how we should reference it in a non-pcrel context.
694 unsigned char classifyBlockAddressReference() const;
696 /// Return true if the subtarget allows calls to immediate address.
697 bool isLegalToCallImmediateAddr() const;
699 /// Enable the MachineScheduler pass for all X86 subtargets.
700 bool enableMachineScheduler() const override { return true; }
702 // TODO: Update the regression tests and return true.
703 bool supportPrintSchedInfo() const override { return false; }
705 bool enableEarlyIfConversion() const override;
707 /// Return the instruction itineraries based on the subtarget selection.
708 const InstrItineraryData *getInstrItineraryData() const override {
712 AntiDepBreakMode getAntiDepBreakMode() const override {
713 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
716 bool enableAdvancedRASplitCost() const override { return true; }
719 } // end namespace llvm
721 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H