2 // Copyright (c) 2000, Intel Corporation
3 // All rights reserved.
5 // Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
6 // Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
11 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
12 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
13 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
14 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
15 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
16 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
17 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
18 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
19 // OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
20 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
21 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 // Intel Corporation is the author of this code, and requests that all
24 // problem reports or change requests be submitted to it directly at
25 // http://developer.intel.com/opensource.
28 #include <machine/asm.h>
29 __FBSDID("$FreeBSD$");
36 // general registers used: r31, r32, r33, r34
37 // predicate registers used: p6
38 // floating-point registers used: f6, f7, f8
41 // load a, the first argument, in f6
46 // load b, the second argument, in f7
51 // BEGIN SINGLE PRECISION LATENCY-OPTIMIZED DIVIDE ALGORITHM
62 (p6) fma.s1 f6=f6,f8,f0
67 // e0 = 1 - b * y0 in f7
68 (p6) fnma.s1 f7=f7,f8,f1
73 // q1 = q0 + e0 * q0 in f6
74 (p6) fma.s1 f6=f7,f6,f6
80 (p6) fma.s1 f7=f7,f7,f0
85 // q2 = q1 + e1 * q1 in f6
86 (p6) fma.s1 f6=f7,f6,f6
92 (p6) fma.s1 f7=f7,f7,f0
97 // q3 = q2 + e2 * q2 in f6
98 (p6) fma.d.s1 f6=f7,f6,f6
104 (p6) fma.s.s0 f8=f6,f1,f0
107 // END SINGLE PRECISION LATENCY-OPTIMIZED DIVIDE ALGORITHM