2 * Copyright (c) 1992, 1993
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5 * This software was developed by the Computer Systems Engineering group
6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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38 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93
39 * $NetBSD: fpu_explode.c,v 1.5 2000/08/03 18:32:08 eeh Exp $
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
46 * FPU subroutines: `explode' the machine's `packed binary' format numbers
47 * into our internal format.
50 #include <sys/param.h>
56 #include <machine/frame.h>
57 #include <machine/fp.h>
58 #include <machine/fsr.h>
59 #include <machine/ieee.h>
60 #include <machine/instr.h>
62 #include "fpu_arith.h"
64 #include "fpu_extern.h"
65 #include "__sparc_utrap_private.h"
68 * N.B.: in all of the following, we assume the FP format is
70 * ---------------------------
71 * | s | exponent | fraction |
72 * ---------------------------
74 * (which represents -1**s * 1.fraction * 2**exponent), so that the
75 * sign bit is way at the top (bit 31), the exponent is next, and
76 * then the remaining bits mark the fraction. A zero exponent means
77 * zero or denormalized (0.fraction rather than 1.fraction), and the
78 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN.
80 * Since the sign bit is always the topmost bit---this holds even for
81 * integers---we set that outside all the *tof functions. Each function
82 * returns the class code for the new number (but note that we use
83 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate).
98 * The value FP_1 represents 2^FP_LG, so set the exponent
99 * there and let normalization fix it up. Convert negative
100 * numbers to sign-and-magnitude. Note that this relies on
101 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
105 * The sign bit decides whether i should be interpreted as
106 * a signed or unsigned entity.
108 if (fp->fp_sign && (int)i < 0)
131 * The value FP_1 represents 2^FP_LG, so set the exponent
132 * there and let normalization fix it up. Convert negative
133 * numbers to sign-and-magnitude. Note that this relies on
134 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
138 * The sign bit decides whether i should be interpreted as
139 * a signed or unsigned entity.
141 if (fp->fp_sign && (int64_t)i < 0)
142 *((int64_t *)fp->fp_mant) = -i;
144 *((int64_t *)fp->fp_mant) = i;
151 #define mask(nbits) ((1L << (nbits)) - 1)
154 * All external floating formats convert to internal in the same manner,
155 * as defined here. Note that only normals get an implied 1.0 inserted.
157 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \
161 fp->fp_exp = 1 - expbias; \
162 fp->fp_mant[0] = f0; \
163 fp->fp_mant[1] = f1; \
164 fp->fp_mant[2] = f2; \
165 fp->fp_mant[3] = f3; \
169 if (exp == (2 * expbias + 1)) { \
172 fp->fp_mant[0] = f0; \
173 fp->fp_mant[1] = f1; \
174 fp->fp_mant[2] = f2; \
175 fp->fp_mant[3] = f3; \
178 fp->fp_exp = exp - expbias; \
179 fp->fp_mant[0] = FP_1 | f0; \
180 fp->fp_mant[1] = f1; \
181 fp->fp_mant[2] = f2; \
182 fp->fp_mant[3] = f3; \
186 * 32-bit single precision -> fpn.
187 * We assume a single occupies at most (64-FP_LG) bits in the internal
188 * format: i.e., needs at most fp_mant[0] and fp_mant[1].
197 #define SNG_SHIFT (SNG_FRACBITS - FP_LG)
199 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS);
200 frac = i & mask(SNG_FRACBITS);
201 f0 = frac >> SNG_SHIFT;
202 f1 = frac << (32 - SNG_SHIFT);
203 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0);
207 * 64-bit double -> fpn.
208 * We assume this uses at most (96-FP_LG) bits.
216 u_int frac, f0, f1, f2;
217 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG)
219 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS);
220 frac = i & mask(DBL_FRACBITS - 32);
221 f0 = frac >> DBL_SHIFT;
222 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT);
223 f2 = j << (32 - DBL_SHIFT);
225 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0);
229 * 128-bit extended -> fpn.
232 __fpu_qtof(fp, i, j, k, l)
237 u_int frac, f0, f1, f2, f3;
238 #define EXT_SHIFT (-(EXT_FRACBITS - 3 * 32 - FP_LG)) /* left shift! */
241 * Note that ext and fpn `line up', hence no shifting needed.
243 exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS);
244 frac = i & mask(EXT_FRACBITS - 3 * 32);
245 f0 = (frac << EXT_SHIFT) | (j >> (32 - EXT_SHIFT));
246 f1 = (j << EXT_SHIFT) | (k >> (32 - EXT_SHIFT));
247 f2 = (k << EXT_SHIFT) | (l >> (32 - EXT_SHIFT));
250 FP_TOF(exp, EXT_EXP_BIAS, frac, f0, f1, f2, f3);
254 * Explode the contents of a / regpair / regquad.
255 * If the input is a signalling NaN, an NV (invalid) exception
256 * will be set. (Note that nothing but NV can occur until ALU
257 * operations are performed.)
260 __fpu_explode(fe, fp, type, reg)
268 if (type == FTYPE_LNG || type == FTYPE_DBL || type == FTYPE_EXT) {
269 l0 = __fpu_getreg64(reg & ~1);
270 fp->fp_sign = l0 >> 63;
272 s = __fpu_getreg(reg);
273 fp->fp_sign = s >> 31;
278 s = __fpu_xtof(fp, l0);
282 s = __fpu_itof(fp, s);
286 s = __fpu_stof(fp, s);
290 s = __fpu_dtof(fp, l0 >> 32, l0 & 0xffffffff);
294 l1 = __fpu_getreg64((reg & ~1) + 2);
295 s = __fpu_qtof(fp, l0 >> 32, l0 & 0xffffffff, l1 >> 32,
300 __utrap_panic("fpu_explode");
303 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) {
305 * Input is a signalling NaN. All operations that return
306 * an input NaN operand put it through a ``NaN conversion'',
307 * which basically just means ``turn on the quiet bit''.
308 * We do this here so that all NaNs internally look quiet
309 * (we can tell signalling ones by their class).
311 fp->fp_mant[0] |= FP_QUIETBIT;
312 fe->fe_cx = FSR_NV; /* assert invalid operand */
316 DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' :
317 ((type == FTYPE_INT) ? 'i' :
318 ((type == FTYPE_SNG) ? 's' :
319 ((type == FTYPE_DBL) ? 'd' :
320 ((type == FTYPE_EXT) ? 'q' : '?')))),
322 DUMPFPN(FPE_REG, fp);
323 DPRINTF(FPE_REG, ("\n"));