2 * Copyright (c) 1992, 1993
3 * The Regents of the University of California. All rights reserved.
5 * This software was developed by the Computer Systems Engineering group
6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
7 * contributed to Berkeley.
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11 * This product includes software developed by the University of
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38 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93
39 * $NetBSD: fpu_implode.c,v 1.8 2001/08/26 05:44:46 eeh Exp $
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
46 * FPU subroutines: `implode' internal format numbers into the machine's
47 * `packed binary' format.
50 #include <sys/param.h>
52 #include <machine/frame.h>
53 #include <machine/fp.h>
54 #include <machine/fsr.h>
55 #include <machine/ieee.h>
56 #include <machine/instr.h>
58 #include "fpu_arith.h"
60 #include "fpu_extern.h"
61 #include "__sparc_utrap_private.h"
63 static int fpround(struct fpemu *, struct fpn *);
64 static int toinf(struct fpemu *, int);
67 * Round a number (algorithm from Motorola MC68882 manual, modified for
68 * our internal format). Set inexact exception if rounding is required.
69 * Return true iff we rounded up.
71 * After rounding, we discard the guard and round bits by shifting right
72 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky).
73 * This saves effort later.
75 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's
76 * responsibility to fix this if necessary.
79 fpround(struct fpemu *fe, struct fpn *fp)
92 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG));
93 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG));
94 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG));
97 if ((gr | s) == 0) /* result is exact: no rounding needed */
100 fe->fe_cx |= FSR_NX; /* inexact */
102 /* Go to rounddown to round down; break to round up. */
103 switch (FSR_GET_RD(fe->fe_fsr)) {
107 * Round only if guard is set (gr & 2). If guard is set,
108 * but round & sticky both clear, then we want to round
109 * but have a tie, so round to even, i.e., add 1 iff odd.
113 if ((gr & 1) || fp->fp_sticky || (m3 & 1))
118 /* Round towards zero, i.e., down. */
122 /* Round towards -Inf: up if negative, down if positive. */
128 /* Round towards +Inf: up if positive, down otherwise. */
134 /* Bump low bit of mantissa, with carry. */
136 FPU_ADDCS(m2, m2, 0);
137 FPU_ADDCS(m1, m1, 0);
154 * For overflow: return true if overflow is to go to +/-Inf, according
155 * to the sign of the overflowing result. If false, overflow is to go
156 * to the largest magnitude value instead.
159 toinf(struct fpemu *fe, int sign)
163 /* look at rounding direction */
164 switch (FSR_GET_RD(fe->fe_fsr)) {
166 case FSR_RD_N: /* the nearest value is always Inf */
170 case FSR_RD_Z: /* toward 0 => never towards Inf */
174 case FSR_RD_PINF: /* toward +Inf iff positive */
178 case FSR_RD_NINF: /* toward -Inf iff negative */
186 * fpn -> int (int value returned as return value).
188 * N.B.: this conversion always rounds towards zero (this is a peculiarity
189 * of the SPARC instruction set).
200 switch (fp->fp_class) {
207 * If exp >= 2^32, overflow. Otherwise shift value right
208 * into last mantissa word (this will not exceed 0xffffffff),
209 * shifting any guard and round bits out into the sticky
210 * bit. Then ``round'' towards zero, i.e., just set an
211 * inexact exception if sticky is set (see round()).
212 * If the result is > 0x80000000, or is positive and equals
213 * 0x80000000, overflow; otherwise the last fraction word
216 if ((exp = fp->fp_exp) >= 32)
218 /* NB: the following includes exp < 0 cases */
219 if (__fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
222 if (i >= ((u_int)0x80000000 + sign))
224 return (sign ? -i : i);
226 default: /* Inf, qNaN, sNaN */
229 /* overflow: replace any inexact exception with invalid */
230 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV;
231 return (0x7fffffff + sign);
235 * fpn -> extended int (high bits of int value returned as return value).
237 * N.B.: this conversion always rounds towards zero (this is a peculiarity
238 * of the SPARC instruction set).
241 __fpu_ftox(fe, fp, res)
250 switch (fp->fp_class) {
258 * If exp >= 2^64, overflow. Otherwise shift value
259 * right into last mantissa word (this will not exceed
260 * 0xffffffffffffffff), shifting any guard and round
261 * bits out into the sticky bit. Then ``round'' towards
262 * zero, i.e., just set an inexact exception if sticky
263 * is set (see round()).
264 * If the result is > 0x8000000000000000, or is positive
265 * and equals 0x8000000000000000, overflow; otherwise
266 * the last fraction word is the result.
268 if ((exp = fp->fp_exp) >= 64)
270 /* NB: the following includes exp < 0 cases */
271 if (__fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
273 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3];
274 if (i >= ((u_int64_t)0x8000000000000000LL + sign))
281 default: /* Inf, qNaN, sNaN */
284 /* overflow: replace any inexact exception with invalid */
285 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV;
286 return (0x7fffffffffffffffLL + sign);
290 * fpn -> single (32 bit single returned as return value).
291 * We assume <= 29 bits in a single-precision fraction (1.f part).
298 u_int sign = fp->fp_sign << 31;
301 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */
302 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */
304 /* Take care of non-numbers first. */
307 * Preserve upper bits of NaN, per SPARC V8 appendix N.
308 * Note that fp->fp_mant[0] has the quiet bit set,
309 * even if it is classified as a signalling NaN.
311 (void) __fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS);
312 exp = SNG_EXP_INFNAN;
316 return (sign | SNG_EXP(SNG_EXP_INFNAN));
321 * Normals (including subnormals). Drop all the fraction bits
322 * (including the explicit ``implied'' 1 bit) down into the
323 * single-precision range. If the number is subnormal, move
324 * the ``implied'' 1 into the explicit range as well, and shift
325 * right to introduce leading zeroes. Rounding then acts
326 * differently for normals and subnormals: the largest subnormal
327 * may round to the smallest normal (1.0 x 2^minexp), or may
328 * remain subnormal. In the latter case, signal an underflow
329 * if the result was inexact or if underflow traps are enabled.
331 * Rounding a normal, on the other hand, always produces another
332 * normal (although either way the result might be too big for
333 * single precision, and cause an overflow). If rounding a
334 * normal produces 2.0 in the fraction, we need not adjust that
335 * fraction at all, since both 1.0 and 2.0 are zero under the
338 * Note that the guard and round bits vanish from the number after
341 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */
342 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */
343 (void) __fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp);
344 if (fpround(fe, fp) && fp->fp_mant[3] == SNG_EXP(1))
345 return (sign | SNG_EXP(1) | 0);
346 if ((fe->fe_cx & FSR_NX) ||
347 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
349 return (sign | SNG_EXP(0) | fp->fp_mant[3]);
351 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */
352 (void) __fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS);
354 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0)
355 __utrap_panic("fpu_ftos");
357 if (fpround(fe, fp) && fp->fp_mant[3] == SNG_EXP(2))
359 if (exp >= SNG_EXP_INFNAN) {
360 /* overflow to inf or to max single */
361 fe->fe_cx |= FSR_OF | FSR_NX;
363 return (sign | SNG_EXP(SNG_EXP_INFNAN));
364 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK);
368 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK));
372 * fpn -> double (32 bit high-order result returned; 32-bit low order result
373 * left in res[1]). Assumes <= 61 bits in double precision fraction.
375 * This code mimics fpu_ftos; see it for comments.
378 __fpu_ftod(fe, fp, res)
383 u_int sign = fp->fp_sign << 31;
386 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31))
387 #define DBL_MASK (DBL_EXP(1) - 1)
390 (void) __fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS);
391 exp = DBL_EXP_INFNAN;
395 sign |= DBL_EXP(DBL_EXP_INFNAN);
403 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) {
404 (void) __fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp);
405 if (fpround(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) {
407 return (sign | DBL_EXP(1) | 0);
409 if ((fe->fe_cx & FSR_NX) ||
410 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
415 (void) __fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS);
416 if (fpround(fe, fp) && fp->fp_mant[2] == DBL_EXP(2))
418 if (exp >= DBL_EXP_INFNAN) {
419 fe->fe_cx |= FSR_OF | FSR_NX;
420 if (toinf(fe, sign)) {
422 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0);
425 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK);
428 res[1] = fp->fp_mant[3];
429 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK));
433 * fpn -> extended (32 bit high-order result returned; low-order fraction
434 * words left in res[1]..res[3]). Like ftod, which is like ftos ... but
435 * our internal format *is* extended precision, plus 2 bits for guard/round,
436 * so we can avoid a small bit of work.
439 __fpu_ftoq(fe, fp, res)
444 u_int sign = fp->fp_sign << 31;
447 #define EXT_EXP(e) ((e) << (EXT_FRACBITS & 31))
448 #define EXT_MASK (EXT_EXP(1) - 1)
451 (void) __fpu_shr(fp, 2); /* since we are not rounding */
452 exp = EXT_EXP_INFNAN;
456 sign |= EXT_EXP(EXT_EXP_INFNAN);
460 zero: res[1] = res[2] = res[3] = 0;
464 if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) {
465 (void) __fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp);
466 if (fpround(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) {
467 res[1] = res[2] = res[3] = 0;
468 return (sign | EXT_EXP(1) | 0);
470 if ((fe->fe_cx & FSR_NX) ||
471 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
476 /* Since internal == extended, no need to shift here. */
477 if (fpround(fe, fp) && fp->fp_mant[0] == EXT_EXP(2))
479 if (exp >= EXT_EXP_INFNAN) {
480 fe->fe_cx |= FSR_OF | FSR_NX;
481 if (toinf(fe, sign)) {
482 res[1] = res[2] = res[3] = 0;
483 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0);
485 res[1] = res[2] = res[3] = ~0;
486 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK);
489 res[1] = fp->fp_mant[1];
490 res[2] = fp->fp_mant[2];
491 res[3] = fp->fp_mant[3];
492 return (sign | EXT_EXP(exp) | (fp->fp_mant[0] & EXT_MASK));
496 * Implode an fpn, writing the result into the given space.
499 __fpu_implode(fe, fp, type, space)
509 space[0] = __fpu_ftox(fe, fp, space);
513 space[0] = __fpu_ftoi(fe, fp);
517 space[0] = __fpu_ftos(fe, fp);
521 space[0] = __fpu_ftod(fe, fp, space);
525 /* funky rounding precision options ?? */
526 space[0] = __fpu_ftoq(fe, fp, space);
530 __utrap_panic("fpu_implode");
532 DPRINTF(FPE_REG, ("fpu_implode: %x %x %x %x\n",
533 space[0], space[1], space[2], space[3]));