3 CRTARCH= ${MACHINE_CPUARCH:C/amd64/x86_64/}
5 CRTSRC= ${SRCTOP}/contrib/llvm-project/compiler-rt/lib/builtins
7 .PATH: ${CRTSRC}/${CRTARCH}
16 SRCF+= apple_versioning
42 SRCF+= enable_execute_stack
111 SRCF+= trampoline_setup
126 # Avoid using SSE2 instructions on i386, if unsupported.
127 .if ${MACHINE_CPUARCH} == "i386" && empty(MACHINE_CPU:Msse2)
143 # __cpu_model support, only used on x86
144 .if ${MACHINE_CPUARCH} == "amd64" || ${MACHINE_CPUARCH} == "i386"
148 # The fp_mode implementation for amd64 and i386 is shared, while other
149 # architectures use the regular approach.
150 .if ${MACHINE_CPUARCH} == "amd64" || ${MACHINE_CPUARCH} == "i386"
151 SRCS+= i386/fp_mode.c
157 # 128-bit quad precision long double support,
158 # only used on some architectures.
160 .if ${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "riscv"
182 # These are already shipped by libc.a on some architectures.
183 .if ${MACHINE_CPUARCH} != "arm" && ${MACHINE_CPUARCH} != "mips" && \
184 ${MACHINE_CPUARCH} != "riscv"
201 .if ${MACHINE_CPUARCH} != "arm" && ${MACHINE_CPUARCH} != "mips"
206 # FreeBSD-specific atomic intrinsics.
207 .if ${MACHINE_CPUARCH} == "arm"
208 .PATH: ${SRCTOP}/sys/arm/arm
211 CFLAGS+= -DEMIT_SYNC_ATOMICS
212 .elif ${MACHINE_CPUARCH} == "mips"
213 .PATH: ${SRCTOP}/sys/mips/mips
219 .if ${MACHINE_ARCH:Marmv[67]*} && (!defined(CPUTYPE) || ${CPUTYPE:M*soft*} == "") \
220 && exists(${CRTSRC}/${CRTARCH}/${file}vfp.S)
222 . elif exists(${CRTSRC}/${CRTARCH}/${file}.S)
229 .if ${MACHINE_CPUARCH} == "arm"
231 SRCS+= aeabi_idivmod.S
232 SRCS+= aeabi_ldivmod.S
233 SRCS+= aeabi_memcmp.S
234 SRCS+= aeabi_memcpy.S
235 SRCS+= aeabi_memmove.S
236 SRCS+= aeabi_memset.S
237 SRCS+= aeabi_uidivmod.S
238 SRCS+= aeabi_uldivmod.S
243 SRCS+= sync_synchronize.S
246 .if ${MACHINE_ARCH:Mriscv*sf}
247 CFLAGS+= -D__SOFT_FP__