3 CRTARCH= ${MACHINE_CPUARCH:C/amd64/x86_64/}
5 CRTSRC= ${SRCTOP}/contrib/llvm-project/compiler-rt/lib/builtins
7 .PATH: ${CRTSRC}/${CRTARCH}
16 SRCF+= apple_versioning
42 SRCF+= enable_execute_stack
110 SRCF+= trampoline_setup
125 # Enable compiler-rt's atomic implementation only for clang, as it uses clang
126 # specific builtins, and gcc packages usually come with their own libatomic.
127 # Exclude arm which has its own implementations of atomic functions, below.
128 .if "${COMPILER_TYPE}" == "clang" && ${MACHINE_CPUARCH} != "arm"
132 # Avoid using SSE2 instructions on i386, if unsupported.
133 .if ${MACHINE_CPUARCH} == "i386" && empty(MACHINE_CPU:Msse2)
149 # __cpu_model support, only used on aarch64 and x86
150 .if ${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "amd64" || \
151 ${MACHINE_CPUARCH} == "i386"
155 # The fp_mode implementation for amd64 and i386 is shared, while other
156 # architectures use the regular approach.
157 .if ${MACHINE_CPUARCH} == "amd64" || ${MACHINE_CPUARCH} == "i386"
158 SRCS+= i386/fp_mode.c
164 # 128-bit quad precision long double support,
165 # only used on some architectures.
167 .if ${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "riscv"
191 # These are already shipped by libc.a on some architectures.
192 .if ${MACHINE_CPUARCH} != "arm" && ${MACHINE_CPUARCH} != "mips" && \
193 ${MACHINE_CPUARCH} != "riscv"
210 .if ${MACHINE_CPUARCH} != "arm" && ${MACHINE_CPUARCH} != "mips"
215 # FreeBSD-specific atomic intrinsics.
216 .if ${MACHINE_CPUARCH} == "arm"
217 .PATH: ${SRCTOP}/sys/arm/arm
220 CFLAGS+= -DEMIT_SYNC_ATOMICS
221 .elif ${MACHINE_CPUARCH} == "mips"
222 .PATH: ${SRCTOP}/sys/mips/mips
228 .if ${MACHINE_CPUARCH} == "arm" && (!defined(CPUTYPE) || ${CPUTYPE:M*soft*} == "") \
229 && exists(${CRTSRC}/${CRTARCH}/${file}vfp.S)
231 . elif exists(${CRTSRC}/${CRTARCH}/${file}.S)
238 .if ${MACHINE_CPUARCH} == "arm"
240 SRCS+= aeabi_idivmod.S
241 SRCS+= aeabi_ldivmod.S
242 SRCS+= aeabi_memcmp.S
243 SRCS+= aeabi_memcpy.S
244 SRCS+= aeabi_memmove.S
245 SRCS+= aeabi_memset.S
246 SRCS+= aeabi_uidivmod.S
247 SRCS+= aeabi_uldivmod.S
252 SRCS+= sync_synchronize.S
255 .if ${MACHINE_ARCH:Mriscv*sf}
256 CFLAGS+= -D__SOFT_FP__