3 CRTARCH= ${MACHINE_CPUARCH:C/amd64/x86_64/}
5 CRTSRC= ${SRCTOP}/contrib/llvm-project/compiler-rt/lib/builtins
7 .PATH: ${CRTSRC}/${CRTARCH}
16 SRCF+= apple_versioning
42 SRCF+= enable_execute_stack
111 SRCF+= trampoline_setup
126 # Enable compiler-rt's atomic implementation only for clang, as it uses clang
127 # specific builtins, and gcc packages usually come with their own libatomic.
128 # Exclude arm which has its own implementations of atomic functions, below.
129 .if "${COMPILER_TYPE}" == "clang" && ${MACHINE_CPUARCH} != "arm"
133 # Avoid using SSE2 instructions on i386, if unsupported.
134 .if ${MACHINE_CPUARCH} == "i386" && empty(MACHINE_CPU:Msse2)
150 # __cpu_model support, only used on aarch64 and x86
151 .if ${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "amd64" || \
152 ${MACHINE_CPUARCH} == "i386"
156 # The fp_mode implementation for amd64 and i386 is shared, while other
157 # architectures use the regular approach.
158 .if ${MACHINE_CPUARCH} == "amd64" || ${MACHINE_CPUARCH} == "i386"
159 SRCS+= i386/fp_mode.c
165 # 128-bit quad precision long double support,
166 # only used on some architectures.
168 .if ${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "riscv"
192 # These are already shipped by libc.a on some architectures.
193 .if ${MACHINE_CPUARCH} != "arm" && ${MACHINE_CPUARCH} != "mips" && \
194 ${MACHINE_CPUARCH} != "riscv"
211 .if ${MACHINE_CPUARCH} != "arm" && ${MACHINE_CPUARCH} != "mips"
216 # FreeBSD-specific atomic intrinsics.
217 .if ${MACHINE_CPUARCH} == "arm"
218 .PATH: ${SRCTOP}/sys/arm/arm
221 CFLAGS+= -DEMIT_SYNC_ATOMICS
222 .elif ${MACHINE_CPUARCH} == "mips"
223 .PATH: ${SRCTOP}/sys/mips/mips
229 .if ${MACHINE_ARCH:Marmv[67]*} && (!defined(CPUTYPE) || ${CPUTYPE:M*soft*} == "") \
230 && exists(${CRTSRC}/${CRTARCH}/${file}vfp.S)
232 . elif exists(${CRTSRC}/${CRTARCH}/${file}.S)
239 .if ${MACHINE_CPUARCH} == "arm"
241 SRCS+= aeabi_idivmod.S
242 SRCS+= aeabi_ldivmod.S
243 SRCS+= aeabi_memcmp.S
244 SRCS+= aeabi_memcpy.S
245 SRCS+= aeabi_memmove.S
246 SRCS+= aeabi_memset.S
247 SRCS+= aeabi_uidivmod.S
248 SRCS+= aeabi_uldivmod.S
253 SRCS+= sync_synchronize.S
256 .if ${MACHINE_ARCH:Mriscv*sf}
257 CFLAGS+= -D__SOFT_FP__