2 * Copyright (c) 2015 John H. Baldwin <jhb@FreeBSD.org>
4 * Copyright (c) 2019 Mitchell Horne
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef __KVM_RISCV_H__
31 #define __KVM_RISCV_H__
34 #include <machine/pte.h>
37 typedef uint64_t riscv_physaddr_t;
38 typedef uint64_t riscv_pt_entry_t;
40 #define RISCV_PAGE_SHIFT 12
41 #define RISCV_PAGE_SIZE (1 << RISCV_PAGE_SHIFT)
42 #define RISCV_PAGE_MASK (RISCV_PAGE_SIZE - 1)
44 /* Source: sys/riscv/include/pte.h */
45 #define RISCV_L3_SHIFT 12
46 #define RISCV_L3_SIZE (1 << L3_SHIFT)
47 #define RISCV_L3_OFFSET (L3_SIZE - 1)
49 #define RISCV_PTE_SW_MANAGED (1 << 9)
50 #define RISCV_PTE_SW_WIRED (1 << 8)
51 #define RISCV_PTE_D (1 << 7) /* Dirty */
52 #define RISCV_PTE_A (1 << 6) /* Accessed */
53 #define RISCV_PTE_G (1 << 5) /* Global */
54 #define RISCV_PTE_U (1 << 4) /* User */
55 #define RISCV_PTE_X (1 << 3) /* Execute */
56 #define RISCV_PTE_W (1 << 2) /* Write */
57 #define RISCV_PTE_R (1 << 1) /* Read */
58 #define RISCV_PTE_V (1 << 0) /* Valid */
59 #define RISCV_PTE_RWX (RISCV_PTE_R | RISCV_PTE_W | RISCV_PTE_X)
61 #define RISCV_PTE_PPN0_S 10
64 _Static_assert(sizeof(pt_entry_t) == sizeof(riscv_pt_entry_t),
65 "pt_entry_t size mismatch");
67 _Static_assert(PAGE_SHIFT == RISCV_PAGE_SHIFT, "PAGE_SHIFT mismatch");
68 _Static_assert(PAGE_SIZE == RISCV_PAGE_SIZE, "PAGE_SIZE mismatch");
69 _Static_assert(PAGE_MASK == RISCV_PAGE_MASK, "PAGE_MASK mismatch");
71 _Static_assert(L3_SHIFT == RISCV_L3_SHIFT, "L3_SHIFT mismatch");
72 _Static_assert(L3_SIZE == RISCV_L3_SIZE, "L3_SIZE mismatch");
73 _Static_assert(L3_OFFSET == RISCV_L3_OFFSET, "L3_OFFSET mismatch");
74 _Static_assert(PTE_PPN0_S == RISCV_PTE_PPN0_S, "PTE_PPN0_S mismatch");
76 _Static_assert(PTE_SW_MANAGED == RISCV_PTE_SW_MANAGED,
77 "PTE_SW_MANAGED mismatch");
78 _Static_assert(PTE_SW_WIRED == RISCV_PTE_SW_WIRED, "PTE_SW_WIRED mismatch");
79 _Static_assert(PTE_D == RISCV_PTE_D, "PTE_D mismatch");
80 _Static_assert(PTE_A == RISCV_PTE_A, "PTE_A mismatch");
81 _Static_assert(PTE_G == RISCV_PTE_G, "PTE_G mismatch");
82 _Static_assert(PTE_U == RISCV_PTE_U, "PTE_U mismatch");
83 _Static_assert(PTE_X == RISCV_PTE_X, "PTE_X mismatch");
84 _Static_assert(PTE_W == RISCV_PTE_W, "PTE_W mismatch");
85 _Static_assert(PTE_R == RISCV_PTE_R, "PTE_R mismatch");
86 _Static_assert(PTE_V == RISCV_PTE_V, "PTE_V mismatch");
87 _Static_assert(PTE_RWX == RISCV_PTE_RWX, "PTE_RWX mismatch");
90 #endif /* !__KVM_RISCV_H__ */