2 * Copyright (c) 2003-2008 Joseph Koshy
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/types.h>
31 #include <sys/module.h>
33 #include <sys/syscall.h>
45 #include "libpmcinternal.h"
47 /* Function prototypes */
49 static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
50 struct pmc_op_pmcallocate *_pmc_config);
52 #if defined(__amd64__) || defined(__i386__)
53 static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
54 struct pmc_op_pmcallocate *_pmc_config);
55 static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
56 struct pmc_op_pmcallocate *_pmc_config);
57 static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
58 struct pmc_op_pmcallocate *_pmc_config);
59 static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
60 struct pmc_op_pmcallocate *_pmc_config);
61 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
62 struct pmc_op_pmcallocate *_pmc_config);
63 static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
64 struct pmc_op_pmcallocate *_pmc_config);
67 static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
68 struct pmc_op_pmcallocate *_pmc_config);
69 static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
70 struct pmc_op_pmcallocate *_pmc_config);
72 #if defined(__amd64__) || defined(__i386__)
73 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
74 struct pmc_op_pmcallocate *_pmc_config);
78 static int mips24k_allocate_pmc(enum pmc_event _pe, char* ctrspec,
79 struct pmc_op_pmcallocate *_pmc_config);
83 #define PMC_CALL(cmd, params) \
84 syscall(pmc_syscall, PMC_OP_##cmd, (params))
87 * Event aliases provide a way for the user to ask for generic events
88 * like "cache-misses", or "instructions-retired". These aliases are
89 * mapped to the appropriate canonical event descriptions using a
92 struct pmc_event_alias {
97 static const struct pmc_event_alias *pmc_mdep_event_aliases;
100 * The pmc_event_descr structure maps symbolic names known to the user
101 * to integer codes used by the PMC KLD.
103 struct pmc_event_descr {
104 const char *pm_ev_name;
105 enum pmc_event pm_ev_code;
109 * The pmc_class_descr structure maps class name prefixes for
110 * event names to event tables and other PMC class data.
112 struct pmc_class_descr {
113 const char *pm_evc_name;
114 size_t pm_evc_name_size;
115 enum pmc_class pm_evc_class;
116 const struct pmc_event_descr *pm_evc_event_table;
117 size_t pm_evc_event_table_size;
118 int (*pm_evc_allocate_pmc)(enum pmc_event _pe,
119 char *_ctrspec, struct pmc_op_pmcallocate *_pa);
122 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0]))
123 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table)
126 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N },
129 * PMC_CLASSDEP_TABLE(NAME, CLASS)
131 * Define a table mapping event names and aliases to HWPMC event IDs.
133 #define PMC_CLASSDEP_TABLE(N, C) \
134 static const struct pmc_event_descr N##_event_table[] = \
139 PMC_CLASSDEP_TABLE(iaf, IAF);
140 PMC_CLASSDEP_TABLE(k7, K7);
141 PMC_CLASSDEP_TABLE(k8, K8);
142 PMC_CLASSDEP_TABLE(p4, P4);
143 PMC_CLASSDEP_TABLE(p5, P5);
144 PMC_CLASSDEP_TABLE(p6, P6);
145 PMC_CLASSDEP_TABLE(ucf, UCF);
146 PMC_CLASSDEP_TABLE(mips24k, MIPS24K);
148 #undef __PMC_EV_ALIAS
149 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE },
151 static const struct pmc_event_descr atom_event_table[] =
153 __PMC_EV_ALIAS_ATOM()
156 static const struct pmc_event_descr core_event_table[] =
158 __PMC_EV_ALIAS_CORE()
162 static const struct pmc_event_descr core2_event_table[] =
164 __PMC_EV_ALIAS_CORE2()
167 static const struct pmc_event_descr corei7_event_table[] =
169 __PMC_EV_ALIAS_COREI7()
172 static const struct pmc_event_descr westmere_event_table[] =
174 __PMC_EV_ALIAS_WESTMERE()
177 static const struct pmc_event_descr corei7uc_event_table[] =
179 __PMC_EV_ALIAS_COREI7UC()
182 static const struct pmc_event_descr westmereuc_event_table[] =
184 __PMC_EV_ALIAS_WESTMEREUC()
188 * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...)
190 * Map a CPU to the PMC classes it supports.
192 #define PMC_MDEP_TABLE(N,C,...) \
193 static const enum pmc_class N##_pmc_classes[] = { \
194 PMC_CLASS_##C, __VA_ARGS__ \
197 PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC);
198 PMC_MDEP_TABLE(core, IAP, PMC_CLASS_TSC);
199 PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC);
200 PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
201 PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
202 PMC_MDEP_TABLE(k7, K7, PMC_CLASS_TSC);
203 PMC_MDEP_TABLE(k8, K8, PMC_CLASS_TSC);
204 PMC_MDEP_TABLE(p4, P4, PMC_CLASS_TSC);
205 PMC_MDEP_TABLE(p5, P5, PMC_CLASS_TSC);
206 PMC_MDEP_TABLE(p6, P6, PMC_CLASS_TSC);
207 PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_MIPS24K);
209 static const struct pmc_event_descr tsc_event_table[] =
214 #undef PMC_CLASS_TABLE_DESC
215 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \
216 static const struct pmc_class_descr NAME##_class_table_descr = \
218 .pm_evc_name = #CLASS "-", \
219 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \
220 .pm_evc_class = PMC_CLASS_##CLASS , \
221 .pm_evc_event_table = EVENTS##_event_table , \
222 .pm_evc_event_table_size = \
223 PMC_EVENT_TABLE_SIZE(EVENTS), \
224 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \
227 #if defined(__i386__) || defined(__amd64__)
228 PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf);
229 PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap);
230 PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
231 PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
232 PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
233 PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
234 PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
235 PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
236 PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp);
238 #if defined(__i386__)
239 PMC_CLASS_TABLE_DESC(k7, K7, k7, k7);
241 #if defined(__i386__) || defined(__amd64__)
242 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
243 PMC_CLASS_TABLE_DESC(p4, P4, p4, p4);
245 #if defined(__i386__)
246 PMC_CLASS_TABLE_DESC(p5, P5, p5, p5);
247 PMC_CLASS_TABLE_DESC(p6, P6, p6, p6);
249 #if defined(__i386__) || defined(__amd64__)
250 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);
253 #if defined(__mips__)
254 PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips24k);
255 #endif /* __mips__ */
257 #undef PMC_CLASS_TABLE_DESC
259 static const struct pmc_class_descr **pmc_class_table;
260 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass
262 static const enum pmc_class *pmc_mdep_class_list;
263 static size_t pmc_mdep_class_list_size;
266 * Mapping tables, mapping enumeration values to human readable
270 static const char * pmc_capability_names[] = {
272 #define __PMC_CAP(N,V,D) #N ,
276 static const char * pmc_class_names[] = {
278 #define __PMC_CLASS(C) #C ,
282 struct pmc_cputype_map {
283 enum pmc_class pm_cputype;
287 static const struct pmc_cputype_map pmc_cputype_names[] = {
289 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } ,
293 static const char * pmc_disposition_names[] = {
295 #define __PMC_DISP(D) #D ,
299 static const char * pmc_mode_names[] = {
301 #define __PMC_MODE(M,N) #M ,
305 static const char * pmc_state_names[] = {
307 #define __PMC_STATE(S) #S ,
311 static int pmc_syscall = -1; /* filled in by pmc_init() */
313 static struct pmc_cpuinfo cpu_info; /* filled in by pmc_init() */
315 /* Event masks for events */
318 const uint32_t pm_value;
320 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) }
321 #define NULLMASK { .pm_name = NULL }
323 #if defined(__amd64__) || defined(__i386__)
325 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint32_t *evmask)
327 const struct pmc_masks *pm;
331 if (pmask == NULL) /* no mask keywords */
333 q = strchr(p, '='); /* skip '=' */
334 if (*++q == '\0') /* no more data */
336 c = 0; /* count of mask keywords seen */
337 while ((r = strsep(&q, "+")) != NULL) {
338 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name);
341 if (pm->pm_name == NULL) /* not found */
343 *evmask |= pm->pm_value;
350 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0)
351 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0)
352 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S }
354 #if defined(__i386__)
357 * AMD K7 (Athlon) CPUs.
360 static struct pmc_event_alias k7_aliases[] = {
361 EV_ALIAS("branches", "k7-retired-branches"),
362 EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"),
363 EV_ALIAS("cycles", "tsc"),
364 EV_ALIAS("dc-misses", "k7-dc-misses"),
365 EV_ALIAS("ic-misses", "k7-ic-misses"),
366 EV_ALIAS("instructions", "k7-retired-instructions"),
367 EV_ALIAS("interrupts", "k7-hardware-interrupts"),
371 #define K7_KW_COUNT "count"
372 #define K7_KW_EDGE "edge"
373 #define K7_KW_INV "inv"
374 #define K7_KW_OS "os"
375 #define K7_KW_UNITMASK "unitmask"
376 #define K7_KW_USR "usr"
379 k7_allocate_pmc(enum pmc_event pe, char *ctrspec,
380 struct pmc_op_pmcallocate *pmc_config)
384 uint32_t count, unitmask;
386 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
387 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
389 if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 ||
390 pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM ||
391 pe == PMC_EV_K7_DC_WRITEBACKS) {
393 unitmask = AMD_PMC_UNITMASK_MOESI;
395 unitmask = has_unitmask = 0;
397 while ((p = strsep(&ctrspec, ",")) != NULL) {
398 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) {
400 if (*++q == '\0') /* skip '=' */
403 count = strtol(q, &e, 0);
404 if (e == q || *e != '\0')
407 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
408 pmc_config->pm_md.pm_amd.pm_amd_config |=
409 AMD_PMC_TO_COUNTER(count);
411 } else if (KWMATCH(p, K7_KW_EDGE)) {
412 pmc_config->pm_caps |= PMC_CAP_EDGE;
413 } else if (KWMATCH(p, K7_KW_INV)) {
414 pmc_config->pm_caps |= PMC_CAP_INVERT;
415 } else if (KWMATCH(p, K7_KW_OS)) {
416 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
417 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) {
418 if (has_unitmask == 0)
422 if (*++q == '\0') /* skip '=' */
425 while ((c = tolower(*q++)) != 0)
427 unitmask |= AMD_PMC_UNITMASK_M;
429 unitmask |= AMD_PMC_UNITMASK_O;
431 unitmask |= AMD_PMC_UNITMASK_E;
433 unitmask |= AMD_PMC_UNITMASK_S;
435 unitmask |= AMD_PMC_UNITMASK_I;
444 } else if (KWMATCH(p, K7_KW_USR)) {
445 pmc_config->pm_caps |= PMC_CAP_USER;
451 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
452 pmc_config->pm_md.pm_amd.pm_amd_config |=
453 AMD_PMC_TO_UNITMASK(unitmask);
462 #if defined(__amd64__) || defined(__i386__)
465 * Intel Core (Family 6, Model E) PMCs.
468 static struct pmc_event_alias core_aliases[] = {
469 EV_ALIAS("branches", "iap-br-instr-ret"),
470 EV_ALIAS("branch-mispredicts", "iap-br-mispred-ret"),
471 EV_ALIAS("cycles", "tsc-tsc"),
472 EV_ALIAS("ic-misses", "iap-icache-misses"),
473 EV_ALIAS("instructions", "iap-instr-ret"),
474 EV_ALIAS("interrupts", "iap-core-hw-int-rx"),
475 EV_ALIAS("unhalted-cycles", "iap-unhalted-core-cycles"),
480 * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H)
481 * and Atom (Family 6, model 1CH) PMCs.
483 * We map aliases to events on the fixed-function counters if these
484 * are present. Note that not all CPUs in this family contain fixed-function
488 static struct pmc_event_alias core2_aliases[] = {
489 EV_ALIAS("branches", "iap-br-inst-retired.any"),
490 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"),
491 EV_ALIAS("cycles", "tsc-tsc"),
492 EV_ALIAS("ic-misses", "iap-l1i-misses"),
493 EV_ALIAS("instructions", "iaf-instr-retired.any"),
494 EV_ALIAS("interrupts", "iap-hw-int-rcv"),
495 EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"),
499 static struct pmc_event_alias core2_aliases_without_iaf[] = {
500 EV_ALIAS("branches", "iap-br-inst-retired.any"),
501 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"),
502 EV_ALIAS("cycles", "tsc-tsc"),
503 EV_ALIAS("ic-misses", "iap-l1i-misses"),
504 EV_ALIAS("instructions", "iap-inst-retired.any_p"),
505 EV_ALIAS("interrupts", "iap-hw-int-rcv"),
506 EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"),
510 #define atom_aliases core2_aliases
511 #define atom_aliases_without_iaf core2_aliases_without_iaf
512 #define corei7_aliases core2_aliases
513 #define corei7_aliases_without_iaf core2_aliases_without_iaf
514 #define westmere_aliases core2_aliases
515 #define westmere_aliases_without_iaf core2_aliases_without_iaf
517 #define IAF_KW_OS "os"
518 #define IAF_KW_USR "usr"
519 #define IAF_KW_ANYTHREAD "anythread"
522 * Parse an event specifier for Intel fixed function counters.
525 iaf_allocate_pmc(enum pmc_event pe, char *ctrspec,
526 struct pmc_op_pmcallocate *pmc_config)
532 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
533 pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0;
535 while ((p = strsep(&ctrspec, ",")) != NULL) {
536 if (KWMATCH(p, IAF_KW_OS))
537 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
538 else if (KWMATCH(p, IAF_KW_USR))
539 pmc_config->pm_caps |= PMC_CAP_USER;
540 else if (KWMATCH(p, IAF_KW_ANYTHREAD))
541 pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY;
550 * Core/Core2 support.
553 #define IAP_KW_AGENT "agent"
554 #define IAP_KW_ANYTHREAD "anythread"
555 #define IAP_KW_CACHESTATE "cachestate"
556 #define IAP_KW_CMASK "cmask"
557 #define IAP_KW_CORE "core"
558 #define IAP_KW_EDGE "edge"
559 #define IAP_KW_INV "inv"
560 #define IAP_KW_OS "os"
561 #define IAP_KW_PREFETCH "prefetch"
562 #define IAP_KW_SNOOPRESPONSE "snoopresponse"
563 #define IAP_KW_SNOOPTYPE "snooptype"
564 #define IAP_KW_TRANSITION "trans"
565 #define IAP_KW_USR "usr"
566 #define IAP_KW_RSP "rsp"
568 static struct pmc_masks iap_core_mask[] = {
569 PMCMASK(all, (0x3 << 14)),
570 PMCMASK(this, (0x1 << 14)),
574 static struct pmc_masks iap_agent_mask[] = {
576 PMCMASK(any, (0x1 << 13)),
580 static struct pmc_masks iap_prefetch_mask[] = {
581 PMCMASK(both, (0x3 << 12)),
582 PMCMASK(only, (0x1 << 12)),
587 static struct pmc_masks iap_cachestate_mask[] = {
588 PMCMASK(i, (1 << 8)),
589 PMCMASK(s, (1 << 9)),
590 PMCMASK(e, (1 << 10)),
591 PMCMASK(m, (1 << 11)),
595 static struct pmc_masks iap_snoopresponse_mask[] = {
596 PMCMASK(clean, (1 << 8)),
597 PMCMASK(hit, (1 << 9)),
598 PMCMASK(hitm, (1 << 11)),
602 static struct pmc_masks iap_snooptype_mask[] = {
603 PMCMASK(cmp2s, (1 << 8)),
604 PMCMASK(cmp2i, (1 << 9)),
608 static struct pmc_masks iap_transition_mask[] = {
610 PMCMASK(frequency, 0x10),
614 static struct pmc_masks iap_rsp_mask[] = {
615 PMCMASK(DMND_DATA_RD, (1 << 0)),
616 PMCMASK(DMND_RFO, (1 << 1)),
617 PMCMASK(DMND_IFETCH, (1 << 2)),
618 PMCMASK(WB, (1 << 3)),
619 PMCMASK(PF_DATA_RD, (1 << 4)),
620 PMCMASK(PF_RFO, (1 << 5)),
621 PMCMASK(PF_IFETCH, (1 << 6)),
622 PMCMASK(OTHER, (1 << 7)),
623 PMCMASK(UNCORE_HIT, (1 << 8)),
624 PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)),
625 PMCMASK(OTHER_CORE_HITM, (1 << 10)),
626 PMCMASK(REMOTE_CACHE_FWD, (1 << 12)),
627 PMCMASK(REMOTE_DRAM, (1 << 13)),
628 PMCMASK(LOCAL_DRAM, (1 << 14)),
629 PMCMASK(NON_DRAM, (1 << 15)),
634 iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
635 struct pmc_op_pmcallocate *pmc_config)
638 uint32_t cachestate, evmask, rsp;
641 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
643 pmc_config->pm_md.pm_iap.pm_iap_config = 0;
645 cachestate = evmask = rsp = 0;
647 /* Parse additional modifiers if present */
648 while ((p = strsep(&ctrspec, ",")) != NULL) {
651 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) {
653 if (*++q == '\0') /* skip '=' */
655 count = strtol(q, &e, 0);
656 if (e == q || *e != '\0')
658 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
659 pmc_config->pm_md.pm_iap.pm_iap_config |=
661 } else if (KWMATCH(p, IAP_KW_EDGE)) {
662 pmc_config->pm_caps |= PMC_CAP_EDGE;
663 } else if (KWMATCH(p, IAP_KW_INV)) {
664 pmc_config->pm_caps |= PMC_CAP_INVERT;
665 } else if (KWMATCH(p, IAP_KW_OS)) {
666 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
667 } else if (KWMATCH(p, IAP_KW_USR)) {
668 pmc_config->pm_caps |= PMC_CAP_USER;
669 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) {
670 pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY;
671 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) {
672 n = pmc_parse_mask(iap_core_mask, p, &evmask);
675 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) {
676 n = pmc_parse_mask(iap_agent_mask, p, &evmask);
679 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) {
680 n = pmc_parse_mask(iap_prefetch_mask, p, &evmask);
683 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) {
684 n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate);
685 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE &&
686 KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) {
687 n = pmc_parse_mask(iap_transition_mask, p, &evmask);
690 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM ||
691 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 ||
692 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) {
693 if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) {
694 n = pmc_parse_mask(iap_snoopresponse_mask, p,
696 } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) {
697 n = pmc_parse_mask(iap_snooptype_mask, p,
701 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 ||
702 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) {
703 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
704 n = pmc_parse_mask(iap_rsp_mask, p, &rsp);
710 if (n < 0) /* Parsing failed. */
714 pmc_config->pm_md.pm_iap.pm_iap_config |= evmask;
717 * If the event requires a 'cachestate' qualifier but was not
718 * specified by the user, use a sensible default.
721 case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */
722 case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */
723 case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */
724 case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */
725 case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */
726 case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */
727 case PMC_EV_IAP_EVENT_32H: /* Core */
728 case PMC_EV_IAP_EVENT_40H: /* Core */
729 case PMC_EV_IAP_EVENT_41H: /* Core */
730 case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */
732 cachestate = (0xF << 8);
734 case PMC_EV_IAP_EVENT_77H: /* Atom */
735 /* IAP_EVENT_77H only accepts a cachestate qualifier on the
738 if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0)
739 cachestate = (0xF << 8);
745 pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate;
746 pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp;
756 ucf_allocate_pmc(enum pmc_event pe, char *ctrspec,
757 struct pmc_op_pmcallocate *pmc_config)
762 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
763 pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0;
768 #define UCP_KW_CMASK "cmask"
769 #define UCP_KW_EDGE "edge"
770 #define UCP_KW_INV "inv"
773 ucp_allocate_pmc(enum pmc_event pe, char *ctrspec,
774 struct pmc_op_pmcallocate *pmc_config)
781 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
783 pmc_config->pm_md.pm_ucp.pm_ucp_config = 0;
785 /* Parse additional modifiers if present */
786 while ((p = strsep(&ctrspec, ",")) != NULL) {
789 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) {
791 if (*++q == '\0') /* skip '=' */
793 count = strtol(q, &e, 0);
794 if (e == q || *e != '\0')
796 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
797 pmc_config->pm_md.pm_ucp.pm_ucp_config |=
799 } else if (KWMATCH(p, UCP_KW_EDGE)) {
800 pmc_config->pm_caps |= PMC_CAP_EDGE;
801 } else if (KWMATCH(p, UCP_KW_INV)) {
802 pmc_config->pm_caps |= PMC_CAP_INVERT;
806 if (n < 0) /* Parsing failed. */
816 * These are very similar to AMD K7 PMCs, but support more kinds of
820 static struct pmc_event_alias k8_aliases[] = {
821 EV_ALIAS("branches", "k8-fr-retired-taken-branches"),
822 EV_ALIAS("branch-mispredicts",
823 "k8-fr-retired-taken-branches-mispredicted"),
824 EV_ALIAS("cycles", "tsc"),
825 EV_ALIAS("dc-misses", "k8-dc-miss"),
826 EV_ALIAS("ic-misses", "k8-ic-miss"),
827 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"),
828 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"),
829 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"),
833 #define __K8MASK(N,V) PMCMASK(N,(1 << (V)))
839 /* fp dispatched fpu ops */
840 static const struct pmc_masks k8_mask_fdfo[] = {
841 __K8MASK(add-pipe-excluding-junk-ops, 0),
842 __K8MASK(multiply-pipe-excluding-junk-ops, 1),
843 __K8MASK(store-pipe-excluding-junk-ops, 2),
844 __K8MASK(add-pipe-junk-ops, 3),
845 __K8MASK(multiply-pipe-junk-ops, 4),
846 __K8MASK(store-pipe-junk-ops, 5),
850 /* ls segment register loads */
851 static const struct pmc_masks k8_mask_lsrl[] = {
862 /* ls locked operation */
863 static const struct pmc_masks k8_mask_llo[] = {
864 __K8MASK(locked-instructions, 0),
865 __K8MASK(cycles-in-request, 1),
866 __K8MASK(cycles-to-complete, 2),
870 /* dc refill from {l2,system} and dc copyback */
871 static const struct pmc_masks k8_mask_dc[] = {
872 __K8MASK(invalid, 0),
874 __K8MASK(exclusive, 2),
876 __K8MASK(modified, 4),
880 /* dc one bit ecc error */
881 static const struct pmc_masks k8_mask_dobee[] = {
882 __K8MASK(scrubber, 0),
883 __K8MASK(piggyback, 1),
887 /* dc dispatched prefetch instructions */
888 static const struct pmc_masks k8_mask_ddpi[] = {
895 /* dc dcache accesses by locks */
896 static const struct pmc_masks k8_mask_dabl[] = {
897 __K8MASK(accesses, 0),
902 /* bu internal l2 request */
903 static const struct pmc_masks k8_mask_bilr[] = {
904 __K8MASK(ic-fill, 0),
905 __K8MASK(dc-fill, 1),
906 __K8MASK(tlb-reload, 2),
907 __K8MASK(tag-snoop, 3),
908 __K8MASK(cancelled, 4),
912 /* bu fill request l2 miss */
913 static const struct pmc_masks k8_mask_bfrlm[] = {
914 __K8MASK(ic-fill, 0),
915 __K8MASK(dc-fill, 1),
916 __K8MASK(tlb-reload, 2),
920 /* bu fill into l2 */
921 static const struct pmc_masks k8_mask_bfil[] = {
922 __K8MASK(dirty-l2-victim, 0),
923 __K8MASK(victim-from-l2, 1),
927 /* fr retired fpu instructions */
928 static const struct pmc_masks k8_mask_frfi[] = {
930 __K8MASK(mmx-3dnow, 1),
931 __K8MASK(packed-sse-sse2, 2),
932 __K8MASK(scalar-sse-sse2, 3),
936 /* fr retired fastpath double op instructions */
937 static const struct pmc_masks k8_mask_frfdoi[] = {
938 __K8MASK(low-op-pos-0, 0),
939 __K8MASK(low-op-pos-1, 1),
940 __K8MASK(low-op-pos-2, 2),
944 /* fr fpu exceptions */
945 static const struct pmc_masks k8_mask_ffe[] = {
946 __K8MASK(x87-reclass-microfaults, 0),
947 __K8MASK(sse-retype-microfaults, 1),
948 __K8MASK(sse-reclass-microfaults, 2),
949 __K8MASK(sse-and-x87-microtraps, 3),
953 /* nb memory controller page access event */
954 static const struct pmc_masks k8_mask_nmcpae[] = {
955 __K8MASK(page-hit, 0),
956 __K8MASK(page-miss, 1),
957 __K8MASK(page-conflict, 2),
961 /* nb memory controller turnaround */
962 static const struct pmc_masks k8_mask_nmct[] = {
963 __K8MASK(dimm-turnaround, 0),
964 __K8MASK(read-to-write-turnaround, 1),
965 __K8MASK(write-to-read-turnaround, 2),
969 /* nb memory controller bypass saturation */
970 static const struct pmc_masks k8_mask_nmcbs[] = {
971 __K8MASK(memory-controller-hi-pri-bypass, 0),
972 __K8MASK(memory-controller-lo-pri-bypass, 1),
973 __K8MASK(dram-controller-interface-bypass, 2),
974 __K8MASK(dram-controller-queue-bypass, 3),
978 /* nb sized commands */
979 static const struct pmc_masks k8_mask_nsc[] = {
980 __K8MASK(nonpostwrszbyte, 0),
981 __K8MASK(nonpostwrszdword, 1),
982 __K8MASK(postwrszbyte, 2),
983 __K8MASK(postwrszdword, 3),
984 __K8MASK(rdszbyte, 4),
985 __K8MASK(rdszdword, 5),
986 __K8MASK(rdmodwr, 6),
990 /* nb probe result */
991 static const struct pmc_masks k8_mask_npr[] = {
992 __K8MASK(probe-miss, 0),
993 __K8MASK(probe-hit, 1),
994 __K8MASK(probe-hit-dirty-no-memory-cancel, 2),
995 __K8MASK(probe-hit-dirty-with-memory-cancel, 3),
999 /* nb hypertransport bus bandwidth */
1000 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */
1001 __K8MASK(command, 0),
1003 __K8MASK(buffer-release, 2),
1010 #define K8_KW_COUNT "count"
1011 #define K8_KW_EDGE "edge"
1012 #define K8_KW_INV "inv"
1013 #define K8_KW_MASK "mask"
1014 #define K8_KW_OS "os"
1015 #define K8_KW_USR "usr"
1018 k8_allocate_pmc(enum pmc_event pe, char *ctrspec,
1019 struct pmc_op_pmcallocate *pmc_config)
1023 uint32_t count, evmask;
1024 const struct pmc_masks *pm, *pmask;
1026 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1027 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
1032 #define __K8SETMASK(M) pmask = k8_mask_##M
1034 /* setup parsing tables */
1036 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1039 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD:
1042 case PMC_EV_K8_LS_LOCKED_OPERATION:
1045 case PMC_EV_K8_DC_REFILL_FROM_L2:
1046 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM:
1047 case PMC_EV_K8_DC_COPYBACK:
1050 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR:
1053 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS:
1056 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1059 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST:
1062 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS:
1065 case PMC_EV_K8_BU_FILL_INTO_L2:
1068 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1071 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1072 __K8SETMASK(frfdoi);
1074 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1077 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT:
1078 __K8SETMASK(nmcpae);
1080 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND:
1083 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION:
1086 case PMC_EV_K8_NB_SIZED_COMMANDS:
1089 case PMC_EV_K8_NB_PROBE_RESULT:
1092 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH:
1093 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH:
1094 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH:
1099 break; /* no options defined */
1102 while ((p = strsep(&ctrspec, ",")) != NULL) {
1103 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) {
1105 if (*++q == '\0') /* skip '=' */
1108 count = strtol(q, &e, 0);
1109 if (e == q || *e != '\0')
1112 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1113 pmc_config->pm_md.pm_amd.pm_amd_config |=
1114 AMD_PMC_TO_COUNTER(count);
1116 } else if (KWMATCH(p, K8_KW_EDGE)) {
1117 pmc_config->pm_caps |= PMC_CAP_EDGE;
1118 } else if (KWMATCH(p, K8_KW_INV)) {
1119 pmc_config->pm_caps |= PMC_CAP_INVERT;
1120 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) {
1121 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1123 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1124 } else if (KWMATCH(p, K8_KW_OS)) {
1125 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1126 } else if (KWMATCH(p, K8_KW_USR)) {
1127 pmc_config->pm_caps |= PMC_CAP_USER;
1132 /* other post processing */
1134 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1135 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED:
1136 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS:
1137 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1138 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1139 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1140 /* XXX only available in rev B and later */
1142 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1143 /* XXX only available in rev C and later */
1145 case PMC_EV_K8_LS_LOCKED_OPERATION:
1146 /* XXX CPU Rev A,B evmask is to be zero */
1147 if (evmask & (evmask - 1)) /* > 1 bit set */
1150 evmask = 0x01; /* Rev C and later: #instrs */
1151 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1155 if (evmask == 0 && pmask != NULL) {
1156 for (pm = pmask; pm->pm_name; pm++)
1157 evmask |= pm->pm_value;
1158 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1162 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
1163 pmc_config->pm_md.pm_amd.pm_amd_config =
1164 AMD_PMC_TO_UNITMASK(evmask);
1171 #if defined(__amd64__) || defined(__i386__)
1177 static struct pmc_event_alias p4_aliases[] = {
1178 EV_ALIAS("branches", "p4-branch-retired,mask=mmtp+mmtm"),
1179 EV_ALIAS("branch-mispredicts", "p4-mispred-branch-retired"),
1180 EV_ALIAS("cycles", "tsc"),
1181 EV_ALIAS("instructions",
1182 "p4-instr-retired,mask=nbogusntag+nbogustag"),
1183 EV_ALIAS("unhalted-cycles", "p4-global-power-events"),
1184 EV_ALIAS(NULL, NULL)
1187 #define P4_KW_ACTIVE "active"
1188 #define P4_KW_ACTIVE_ANY "any"
1189 #define P4_KW_ACTIVE_BOTH "both"
1190 #define P4_KW_ACTIVE_NONE "none"
1191 #define P4_KW_ACTIVE_SINGLE "single"
1192 #define P4_KW_BUSREQTYPE "busreqtype"
1193 #define P4_KW_CASCADE "cascade"
1194 #define P4_KW_EDGE "edge"
1195 #define P4_KW_INV "complement"
1196 #define P4_KW_OS "os"
1197 #define P4_KW_MASK "mask"
1198 #define P4_KW_PRECISE "precise"
1199 #define P4_KW_TAG "tag"
1200 #define P4_KW_THRESHOLD "threshold"
1201 #define P4_KW_USR "usr"
1203 #define __P4MASK(N,V) PMCMASK(N, (1 << (V)))
1205 static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */
1217 static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */
1218 __P4MASK(tcmiss, 0),
1222 static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */
1225 __P4MASK(hit-uc, 2),
1229 static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */
1230 __P4MASK(st-rb-full, 2),
1231 __P4MASK(64k-conf, 3),
1235 static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */
1241 static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */
1242 __P4MASK(split-ld, 1),
1246 static const struct pmc_masks p4_mask_spr[] = { /* store port replay */
1247 __P4MASK(split-st, 1),
1251 static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */
1252 __P4MASK(no-sta, 1),
1253 __P4MASK(no-std, 3),
1254 __P4MASK(partial-data, 4),
1255 __P4MASK(unalgn-addr, 5),
1259 static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */
1260 __P4MASK(dtmiss, 0),
1261 __P4MASK(itmiss, 1),
1265 static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */
1266 __P4MASK(rd-2ndl-hits, 0),
1267 __P4MASK(rd-2ndl-hite, 1),
1268 __P4MASK(rd-2ndl-hitm, 2),
1269 __P4MASK(rd-3rdl-hits, 3),
1270 __P4MASK(rd-3rdl-hite, 4),
1271 __P4MASK(rd-3rdl-hitm, 5),
1272 __P4MASK(rd-2ndl-miss, 8),
1273 __P4MASK(rd-3rdl-miss, 9),
1274 __P4MASK(wr-2ndl-miss, 10),
1278 static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */
1279 __P4MASK(all-read, 5),
1280 __P4MASK(all-write, 6),
1281 __P4MASK(mem-uc, 7),
1282 __P4MASK(mem-wc, 8),
1283 __P4MASK(mem-wt, 9),
1284 __P4MASK(mem-wp, 10),
1285 __P4MASK(mem-wb, 11),
1287 __P4MASK(other, 14),
1288 __P4MASK(prefetch, 15),
1292 static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */
1293 __P4MASK(all-read, 5),
1294 __P4MASK(all-write, 6),
1295 __P4MASK(mem-uc, 7),
1296 __P4MASK(mem-wc, 8),
1297 __P4MASK(mem-wt, 9),
1298 __P4MASK(mem-wp, 10),
1299 __P4MASK(mem-wb, 11),
1301 __P4MASK(other, 14),
1302 __P4MASK(prefetch, 15),
1306 static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */
1307 __P4MASK(drdy-drv, 0),
1308 __P4MASK(drdy-own, 1),
1309 __P4MASK(drdy-other, 2),
1310 __P4MASK(dbsy-drv, 3),
1311 __P4MASK(dbsy-own, 4),
1312 __P4MASK(dbsy-other, 5),
1316 static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */
1317 __P4MASK(req-type0, 0),
1318 __P4MASK(req-type1, 1),
1319 __P4MASK(req-len0, 2),
1320 __P4MASK(req-len1, 3),
1321 __P4MASK(req-io-type, 5),
1322 __P4MASK(req-lock-type, 6),
1323 __P4MASK(req-cache-type, 7),
1324 __P4MASK(req-split-type, 8),
1325 __P4MASK(req-dem-type, 9),
1326 __P4MASK(req-ord-type, 10),
1327 __P4MASK(mem-type0, 11),
1328 __P4MASK(mem-type1, 12),
1329 __P4MASK(mem-type2, 13),
1333 static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */
1338 static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */
1343 static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */
1348 static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */
1353 static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */
1358 static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */
1363 static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */
1368 static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */
1373 static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */
1379 static const struct pmc_masks p4_mask_gpe[] = { /* global power events */
1380 __P4MASK(running, 0),
1384 static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */
1389 static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */
1390 __P4MASK(from-tc-build, 0),
1391 __P4MASK(from-tc-deliver, 1),
1392 __P4MASK(from-rom, 2),
1396 static const struct pmc_masks p4_mask_rmbt[] = {
1397 /* retired mispred branch type */
1398 __P4MASK(conditional, 1),
1400 __P4MASK(return, 3),
1401 __P4MASK(indirect, 4),
1405 static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */
1406 __P4MASK(conditional, 1),
1408 __P4MASK(retired, 3),
1409 __P4MASK(indirect, 4),
1413 static const struct pmc_masks p4_mask_rs[] = { /* resource stall */
1414 __P4MASK(sbfull, 5),
1418 static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */
1419 __P4MASK(wcb-evicts, 0),
1420 __P4MASK(wcb-full-evict, 1),
1424 static const struct pmc_masks p4_mask_fee[] = { /* front end event */
1425 __P4MASK(nbogus, 0),
1430 static const struct pmc_masks p4_mask_ee[] = { /* execution event */
1431 __P4MASK(nbogus0, 0),
1432 __P4MASK(nbogus1, 1),
1433 __P4MASK(nbogus2, 2),
1434 __P4MASK(nbogus3, 3),
1435 __P4MASK(bogus0, 4),
1436 __P4MASK(bogus1, 5),
1437 __P4MASK(bogus2, 6),
1438 __P4MASK(bogus3, 7),
1442 static const struct pmc_masks p4_mask_re[] = { /* replay event */
1443 __P4MASK(nbogus, 0),
1448 static const struct pmc_masks p4_mask_insret[] = { /* instr retired */
1449 __P4MASK(nbogusntag, 0),
1450 __P4MASK(nbogustag, 1),
1451 __P4MASK(bogusntag, 2),
1452 __P4MASK(bogustag, 3),
1456 static const struct pmc_masks p4_mask_ur[] = { /* uops retired */
1457 __P4MASK(nbogus, 0),
1462 static const struct pmc_masks p4_mask_ut[] = { /* uop type */
1463 __P4MASK(tagloads, 1),
1464 __P4MASK(tagstores, 2),
1468 static const struct pmc_masks p4_mask_br[] = { /* branch retired */
1476 static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */
1477 __P4MASK(nbogus, 0),
1481 static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */
1490 static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */
1492 __P4MASK(moclear, 2),
1493 __P4MASK(smclear, 3),
1497 /* P4 event parser */
1499 p4_allocate_pmc(enum pmc_event pe, char *ctrspec,
1500 struct pmc_op_pmcallocate *pmc_config)
1504 int count, has_tag, has_busreqtype, n;
1505 uint32_t evmask, cccractivemask;
1506 const struct pmc_masks *pm, *pmask;
1508 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1509 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig =
1510 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0;
1514 cccractivemask = 0x3;
1515 has_tag = has_busreqtype = 0;
1517 #define __P4SETMASK(M) do { \
1518 pmask = p4_mask_##M; \
1522 case PMC_EV_P4_TC_DELIVER_MODE:
1525 case PMC_EV_P4_BPU_FETCH_REQUEST:
1528 case PMC_EV_P4_ITLB_REFERENCE:
1531 case PMC_EV_P4_MEMORY_CANCEL:
1532 __P4SETMASK(memcan);
1534 case PMC_EV_P4_MEMORY_COMPLETE:
1535 __P4SETMASK(memcomp);
1537 case PMC_EV_P4_LOAD_PORT_REPLAY:
1540 case PMC_EV_P4_STORE_PORT_REPLAY:
1543 case PMC_EV_P4_MOB_LOAD_REPLAY:
1546 case PMC_EV_P4_PAGE_WALK_TYPE:
1549 case PMC_EV_P4_BSQ_CACHE_REFERENCE:
1552 case PMC_EV_P4_IOQ_ALLOCATION:
1556 case PMC_EV_P4_IOQ_ACTIVE_ENTRIES:
1560 case PMC_EV_P4_FSB_DATA_ACTIVITY:
1563 case PMC_EV_P4_BSQ_ALLOCATION:
1566 case PMC_EV_P4_SSE_INPUT_ASSIST:
1569 case PMC_EV_P4_PACKED_SP_UOP:
1572 case PMC_EV_P4_PACKED_DP_UOP:
1575 case PMC_EV_P4_SCALAR_SP_UOP:
1578 case PMC_EV_P4_SCALAR_DP_UOP:
1581 case PMC_EV_P4_64BIT_MMX_UOP:
1584 case PMC_EV_P4_128BIT_MMX_UOP:
1585 __P4SETMASK(128bmu);
1587 case PMC_EV_P4_X87_FP_UOP:
1590 case PMC_EV_P4_X87_SIMD_MOVES_UOP:
1593 case PMC_EV_P4_GLOBAL_POWER_EVENTS:
1596 case PMC_EV_P4_TC_MS_XFER:
1599 case PMC_EV_P4_UOP_QUEUE_WRITES:
1602 case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE:
1605 case PMC_EV_P4_RETIRED_BRANCH_TYPE:
1608 case PMC_EV_P4_RESOURCE_STALL:
1611 case PMC_EV_P4_WC_BUFFER:
1614 case PMC_EV_P4_BSQ_ACTIVE_ENTRIES:
1615 case PMC_EV_P4_B2B_CYCLES:
1617 case PMC_EV_P4_SNOOP:
1618 case PMC_EV_P4_RESPONSE:
1620 case PMC_EV_P4_FRONT_END_EVENT:
1623 case PMC_EV_P4_EXECUTION_EVENT:
1626 case PMC_EV_P4_REPLAY_EVENT:
1629 case PMC_EV_P4_INSTR_RETIRED:
1630 __P4SETMASK(insret);
1632 case PMC_EV_P4_UOPS_RETIRED:
1635 case PMC_EV_P4_UOP_TYPE:
1638 case PMC_EV_P4_BRANCH_RETIRED:
1641 case PMC_EV_P4_MISPRED_BRANCH_RETIRED:
1644 case PMC_EV_P4_X87_ASSIST:
1647 case PMC_EV_P4_MACHINE_CLEAR:
1648 __P4SETMASK(machclr);
1654 /* process additional flags */
1655 while ((p = strsep(&ctrspec, ",")) != NULL) {
1656 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) {
1658 if (*++q == '\0') /* skip '=' */
1661 if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0)
1662 cccractivemask = 0x0;
1663 else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0)
1664 cccractivemask = 0x1;
1665 else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0)
1666 cccractivemask = 0x2;
1667 else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0)
1668 cccractivemask = 0x3;
1672 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) {
1673 if (has_busreqtype == 0)
1677 if (*++q == '\0') /* skip '=' */
1680 count = strtol(q, &e, 0);
1681 if (e == q || *e != '\0')
1683 evmask = (evmask & ~0x1F) | (count & 0x1F);
1684 } else if (KWMATCH(p, P4_KW_CASCADE))
1685 pmc_config->pm_caps |= PMC_CAP_CASCADE;
1686 else if (KWMATCH(p, P4_KW_EDGE))
1687 pmc_config->pm_caps |= PMC_CAP_EDGE;
1688 else if (KWMATCH(p, P4_KW_INV))
1689 pmc_config->pm_caps |= PMC_CAP_INVERT;
1690 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) {
1691 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1693 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1694 } else if (KWMATCH(p, P4_KW_OS))
1695 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1696 else if (KWMATCH(p, P4_KW_PRECISE))
1697 pmc_config->pm_caps |= PMC_CAP_PRECISE;
1698 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) {
1703 if (*++q == '\0') /* skip '=' */
1706 count = strtol(q, &e, 0);
1707 if (e == q || *e != '\0')
1710 pmc_config->pm_caps |= PMC_CAP_TAGGING;
1711 pmc_config->pm_md.pm_p4.pm_p4_escrconfig |=
1712 P4_ESCR_TO_TAG_VALUE(count);
1713 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) {
1715 if (*++q == '\0') /* skip '=' */
1718 count = strtol(q, &e, 0);
1719 if (e == q || *e != '\0')
1722 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1723 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &=
1724 ~P4_CCCR_THRESHOLD_MASK;
1725 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |=
1726 P4_CCCR_TO_THRESHOLD(count);
1727 } else if (KWMATCH(p, P4_KW_USR))
1728 pmc_config->pm_caps |= PMC_CAP_USER;
1733 /* other post processing */
1734 if (pe == PMC_EV_P4_IOQ_ALLOCATION ||
1735 pe == PMC_EV_P4_FSB_DATA_ACTIVITY ||
1736 pe == PMC_EV_P4_BSQ_ALLOCATION)
1737 pmc_config->pm_caps |= PMC_CAP_EDGE;
1739 /* fill in thread activity mask */
1740 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |=
1741 P4_CCCR_TO_ACTIVE_THREAD(cccractivemask);
1744 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1747 case PMC_EV_P4_FSB_DATA_ACTIVITY:
1748 if ((evmask & 0x06) == 0x06 ||
1749 (evmask & 0x18) == 0x18)
1750 return (-1); /* can't have own+other bits together */
1751 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */
1754 case PMC_EV_P4_MACHINE_CLEAR:
1755 /* only one bit is allowed to be set */
1756 if ((evmask & (evmask - 1)) != 0)
1759 evmask = 0x1; /* 'CLEAR' */
1760 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1764 if (evmask == 0 && pmask) {
1765 for (pm = pmask; pm->pm_name; pm++)
1766 evmask |= pm->pm_value;
1767 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1771 pmc_config->pm_md.pm_p4.pm_p4_escrconfig =
1772 P4_ESCR_TO_EVENT_MASK(evmask);
1779 #if defined(__i386__)
1782 * Pentium style PMCs
1785 static struct pmc_event_alias p5_aliases[] = {
1786 EV_ALIAS("branches", "p5-taken-branches"),
1787 EV_ALIAS("cycles", "tsc"),
1788 EV_ALIAS("dc-misses", "p5-data-read-miss-or-write-miss"),
1789 EV_ALIAS("ic-misses", "p5-code-cache-miss"),
1790 EV_ALIAS("instructions", "p5-instructions-executed"),
1791 EV_ALIAS("interrupts", "p5-hardware-interrupts"),
1792 EV_ALIAS("unhalted-cycles",
1793 "p5-number-of-cycles-not-in-halt-state"),
1794 EV_ALIAS(NULL, NULL)
1798 p5_allocate_pmc(enum pmc_event pe, char *ctrspec,
1799 struct pmc_op_pmcallocate *pmc_config)
1801 return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */
1805 * Pentium Pro style PMCs. These PMCs are found in Pentium II, Pentium III,
1806 * and Pentium M CPUs.
1809 static struct pmc_event_alias p6_aliases[] = {
1810 EV_ALIAS("branches", "p6-br-inst-retired"),
1811 EV_ALIAS("branch-mispredicts", "p6-br-miss-pred-retired"),
1812 EV_ALIAS("cycles", "tsc"),
1813 EV_ALIAS("dc-misses", "p6-dcu-lines-in"),
1814 EV_ALIAS("ic-misses", "p6-ifu-fetch-miss"),
1815 EV_ALIAS("instructions", "p6-inst-retired"),
1816 EV_ALIAS("interrupts", "p6-hw-int-rx"),
1817 EV_ALIAS("unhalted-cycles", "p6-cpu-clk-unhalted"),
1818 EV_ALIAS(NULL, NULL)
1821 #define P6_KW_CMASK "cmask"
1822 #define P6_KW_EDGE "edge"
1823 #define P6_KW_INV "inv"
1824 #define P6_KW_OS "os"
1825 #define P6_KW_UMASK "umask"
1826 #define P6_KW_USR "usr"
1828 static struct pmc_masks p6_mask_mesi[] = {
1836 static struct pmc_masks p6_mask_mesihw[] = {
1841 PMCMASK(nonhw, 0x00),
1843 PMCMASK(both, 0x30),
1847 static struct pmc_masks p6_mask_hw[] = {
1848 PMCMASK(nonhw, 0x00),
1850 PMCMASK(both, 0x30),
1854 static struct pmc_masks p6_mask_any[] = {
1855 PMCMASK(self, 0x00),
1860 static struct pmc_masks p6_mask_ekp[] = {
1868 static struct pmc_masks p6_mask_pps[] = {
1869 PMCMASK(packed-and-scalar, 0x00),
1870 PMCMASK(scalar, 0x01),
1874 static struct pmc_masks p6_mask_mite[] = {
1875 PMCMASK(packed-multiply, 0x01),
1876 PMCMASK(packed-shift, 0x02),
1877 PMCMASK(pack, 0x04),
1878 PMCMASK(unpack, 0x08),
1879 PMCMASK(packed-logical, 0x10),
1880 PMCMASK(packed-arithmetic, 0x20),
1884 static struct pmc_masks p6_mask_fmt[] = {
1885 PMCMASK(mmxtofp, 0x00),
1886 PMCMASK(fptommx, 0x01),
1890 static struct pmc_masks p6_mask_sr[] = {
1898 static struct pmc_masks p6_mask_eet[] = {
1900 PMCMASK(freq, 0x02),
1904 static struct pmc_masks p6_mask_efur[] = {
1906 PMCMASK(loadop, 0x01),
1907 PMCMASK(stdsta, 0x02),
1911 static struct pmc_masks p6_mask_essir[] = {
1912 PMCMASK(sse-packed-single, 0x00),
1913 PMCMASK(sse-packed-single-scalar-single, 0x01),
1914 PMCMASK(sse2-packed-double, 0x02),
1915 PMCMASK(sse2-scalar-double, 0x03),
1919 static struct pmc_masks p6_mask_esscir[] = {
1920 PMCMASK(sse-packed-single, 0x00),
1921 PMCMASK(sse-scalar-single, 0x01),
1922 PMCMASK(sse2-packed-double, 0x02),
1923 PMCMASK(sse2-scalar-double, 0x03),
1927 /* P6 event parser */
1929 p6_allocate_pmc(enum pmc_event pe, char *ctrspec,
1930 struct pmc_op_pmcallocate *pmc_config)
1935 const struct pmc_masks *pm, *pmask;
1937 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1938 pmc_config->pm_md.pm_ppro.pm_ppro_config = 0;
1942 #define P6MASKSET(M) pmask = p6_mask_ ## M
1945 case PMC_EV_P6_L2_IFETCH: P6MASKSET(mesi); break;
1946 case PMC_EV_P6_L2_LD: P6MASKSET(mesi); break;
1947 case PMC_EV_P6_L2_ST: P6MASKSET(mesi); break;
1948 case PMC_EV_P6_L2_RQSTS: P6MASKSET(mesi); break;
1949 case PMC_EV_P6_BUS_DRDY_CLOCKS:
1950 case PMC_EV_P6_BUS_LOCK_CLOCKS:
1951 case PMC_EV_P6_BUS_TRAN_BRD:
1952 case PMC_EV_P6_BUS_TRAN_RFO:
1953 case PMC_EV_P6_BUS_TRANS_WB:
1954 case PMC_EV_P6_BUS_TRAN_IFETCH:
1955 case PMC_EV_P6_BUS_TRAN_INVAL:
1956 case PMC_EV_P6_BUS_TRAN_PWR:
1957 case PMC_EV_P6_BUS_TRANS_P:
1958 case PMC_EV_P6_BUS_TRANS_IO:
1959 case PMC_EV_P6_BUS_TRAN_DEF:
1960 case PMC_EV_P6_BUS_TRAN_BURST:
1961 case PMC_EV_P6_BUS_TRAN_ANY:
1962 case PMC_EV_P6_BUS_TRAN_MEM:
1963 P6MASKSET(any); break;
1964 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED:
1965 case PMC_EV_P6_EMON_KNI_PREF_MISS:
1966 P6MASKSET(ekp); break;
1967 case PMC_EV_P6_EMON_KNI_INST_RETIRED:
1968 case PMC_EV_P6_EMON_KNI_COMP_INST_RET:
1969 P6MASKSET(pps); break;
1970 case PMC_EV_P6_MMX_INSTR_TYPE_EXEC:
1971 P6MASKSET(mite); break;
1972 case PMC_EV_P6_FP_MMX_TRANS:
1973 P6MASKSET(fmt); break;
1974 case PMC_EV_P6_SEG_RENAME_STALLS:
1975 case PMC_EV_P6_SEG_REG_RENAMES:
1976 P6MASKSET(sr); break;
1977 case PMC_EV_P6_EMON_EST_TRANS:
1978 P6MASKSET(eet); break;
1979 case PMC_EV_P6_EMON_FUSED_UOPS_RET:
1980 P6MASKSET(efur); break;
1981 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED:
1982 P6MASKSET(essir); break;
1983 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED:
1984 P6MASKSET(esscir); break;
1990 /* Pentium M PMCs have a few events with different semantics */
1991 if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) {
1992 if (pe == PMC_EV_P6_L2_LD ||
1993 pe == PMC_EV_P6_L2_LINES_IN ||
1994 pe == PMC_EV_P6_L2_LINES_OUT)
1996 else if (pe == PMC_EV_P6_L2_M_LINES_OUTM)
2000 /* Parse additional modifiers if present */
2001 while ((p = strsep(&ctrspec, ",")) != NULL) {
2002 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) {
2004 if (*++q == '\0') /* skip '=' */
2006 count = strtol(q, &e, 0);
2007 if (e == q || *e != '\0')
2009 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
2010 pmc_config->pm_md.pm_ppro.pm_ppro_config |=
2011 P6_EVSEL_TO_CMASK(count);
2012 } else if (KWMATCH(p, P6_KW_EDGE)) {
2013 pmc_config->pm_caps |= PMC_CAP_EDGE;
2014 } else if (KWMATCH(p, P6_KW_INV)) {
2015 pmc_config->pm_caps |= PMC_CAP_INVERT;
2016 } else if (KWMATCH(p, P6_KW_OS)) {
2017 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2018 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) {
2020 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
2022 if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS ||
2023 pe == PMC_EV_P6_BUS_LOCK_CLOCKS ||
2024 pe == PMC_EV_P6_BUS_TRAN_BRD ||
2025 pe == PMC_EV_P6_BUS_TRAN_RFO ||
2026 pe == PMC_EV_P6_BUS_TRAN_IFETCH ||
2027 pe == PMC_EV_P6_BUS_TRAN_INVAL ||
2028 pe == PMC_EV_P6_BUS_TRAN_PWR ||
2029 pe == PMC_EV_P6_BUS_TRAN_DEF ||
2030 pe == PMC_EV_P6_BUS_TRAN_BURST ||
2031 pe == PMC_EV_P6_BUS_TRAN_ANY ||
2032 pe == PMC_EV_P6_BUS_TRAN_MEM ||
2033 pe == PMC_EV_P6_BUS_TRANS_IO ||
2034 pe == PMC_EV_P6_BUS_TRANS_P ||
2035 pe == PMC_EV_P6_BUS_TRANS_WB ||
2036 pe == PMC_EV_P6_EMON_EST_TRANS ||
2037 pe == PMC_EV_P6_EMON_FUSED_UOPS_RET ||
2038 pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET ||
2039 pe == PMC_EV_P6_EMON_KNI_INST_RETIRED ||
2040 pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED ||
2041 pe == PMC_EV_P6_EMON_KNI_PREF_MISS ||
2042 pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED ||
2043 pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED ||
2044 pe == PMC_EV_P6_FP_MMX_TRANS)
2045 && (n > 1)) /* Only one mask keyword is allowed. */
2047 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
2048 } else if (KWMATCH(p, P6_KW_USR)) {
2049 pmc_config->pm_caps |= PMC_CAP_USER;
2054 /* post processing */
2058 * The following events default to an evmask of 0
2061 /* default => 'self' */
2062 case PMC_EV_P6_BUS_DRDY_CLOCKS:
2063 case PMC_EV_P6_BUS_LOCK_CLOCKS:
2064 case PMC_EV_P6_BUS_TRAN_BRD:
2065 case PMC_EV_P6_BUS_TRAN_RFO:
2066 case PMC_EV_P6_BUS_TRANS_WB:
2067 case PMC_EV_P6_BUS_TRAN_IFETCH:
2068 case PMC_EV_P6_BUS_TRAN_INVAL:
2069 case PMC_EV_P6_BUS_TRAN_PWR:
2070 case PMC_EV_P6_BUS_TRANS_P:
2071 case PMC_EV_P6_BUS_TRANS_IO:
2072 case PMC_EV_P6_BUS_TRAN_DEF:
2073 case PMC_EV_P6_BUS_TRAN_BURST:
2074 case PMC_EV_P6_BUS_TRAN_ANY:
2075 case PMC_EV_P6_BUS_TRAN_MEM:
2077 /* default => 'nta' */
2078 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED:
2079 case PMC_EV_P6_EMON_KNI_PREF_MISS:
2081 /* default => 'packed and scalar' */
2082 case PMC_EV_P6_EMON_KNI_INST_RETIRED:
2083 case PMC_EV_P6_EMON_KNI_COMP_INST_RET:
2085 /* default => 'mmx to fp transitions' */
2086 case PMC_EV_P6_FP_MMX_TRANS:
2088 /* default => 'SSE Packed Single' */
2089 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED:
2090 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED:
2092 /* default => 'all fused micro-ops' */
2093 case PMC_EV_P6_EMON_FUSED_UOPS_RET:
2095 /* default => 'all transitions' */
2096 case PMC_EV_P6_EMON_EST_TRANS:
2099 case PMC_EV_P6_MMX_UOPS_EXEC:
2100 evmask = 0x0F; /* only value allowed */
2105 * For all other events, set the default event mask
2106 * to a logical OR of all the allowed event mask bits.
2108 if (evmask == 0 && pmask) {
2109 for (pm = pmask; pm->pm_name; pm++)
2110 evmask |= pm->pm_value;
2111 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
2117 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
2118 pmc_config->pm_md.pm_ppro.pm_ppro_config |=
2119 P6_EVSEL_TO_UMASK(evmask);
2126 #if defined(__i386__) || defined(__amd64__)
2128 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec,
2129 struct pmc_op_pmcallocate *pmc_config)
2131 if (pe != PMC_EV_TSC_TSC)
2134 /* TSC events must be unqualified. */
2135 if (ctrspec && *ctrspec != '\0')
2138 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
2139 pmc_config->pm_caps |= PMC_CAP_READ;
2145 #if defined(__mips__)
2147 static struct pmc_event_alias mips24k_aliases[] = {
2148 EV_ALIAS("instructions", "INSTR_EXECUTED"),
2149 EV_ALIAS("branches", "BRANCH_COMPLETED"),
2150 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"),
2151 EV_ALIAS(NULL, NULL)
2154 #define MIPS24K_KW_OS "os"
2155 #define MIPS24K_KW_USR "usr"
2156 #define MIPS24K_KW_ANYTHREAD "anythread"
2159 mips24k_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2160 struct pmc_op_pmcallocate *pmc_config __unused)
2166 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2168 while ((p = strsep(&ctrspec, ",")) != NULL) {
2169 if (KWMATCH(p, MIPS24K_KW_OS))
2170 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2171 else if (KWMATCH(p, MIPS24K_KW_USR))
2172 pmc_config->pm_caps |= PMC_CAP_USER;
2173 else if (KWMATCH(p, MIPS24K_KW_ANYTHREAD))
2174 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
2181 #endif /* __mips__ */
2185 * Match an event name `name' with its canonical form.
2187 * Matches are case insensitive and spaces, periods, underscores and
2188 * hyphen characters are considered to match each other.
2190 * Returns 1 for a match, 0 otherwise.
2194 pmc_match_event_name(const char *name, const char *canonicalname)
2197 const unsigned char *c, *n;
2199 c = (const unsigned char *) canonicalname;
2200 n = (const unsigned char *) name;
2202 for (; (nc = *n) && (cc = *c); n++, c++) {
2204 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') &&
2205 (cc == ' ' || cc == '_' || cc == '-' || cc == '.'))
2208 if (toupper(nc) == toupper(cc))
2215 if (*n == '\0' && *c == '\0')
2222 * Match an event name against all the event named supported by a
2225 * Returns an event descriptor pointer on match or NULL otherwise.
2227 static const struct pmc_event_descr *
2228 pmc_match_event_class(const char *name,
2229 const struct pmc_class_descr *pcd)
2232 const struct pmc_event_descr *ev;
2234 ev = pcd->pm_evc_event_table;
2235 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++)
2236 if (pmc_match_event_name(name, ev->pm_ev_name))
2243 pmc_mdep_is_compatible_class(enum pmc_class pc)
2247 for (n = 0; n < pmc_mdep_class_list_size; n++)
2248 if (pmc_mdep_class_list[n] == pc)
2258 pmc_allocate(const char *ctrspec, enum pmc_mode mode,
2259 uint32_t flags, int cpu, pmc_id_t *pmcid)
2263 char *r, *spec_copy;
2264 const char *ctrname;
2265 const struct pmc_event_descr *ev;
2266 const struct pmc_event_alias *alias;
2267 struct pmc_op_pmcallocate pmc_config;
2268 const struct pmc_class_descr *pcd;
2273 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS &&
2274 mode != PMC_MODE_SC && mode != PMC_MODE_TC) {
2279 /* replace an event alias with the canonical event specifier */
2280 if (pmc_mdep_event_aliases)
2281 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++)
2282 if (!strcasecmp(ctrspec, alias->pm_alias)) {
2283 spec_copy = strdup(alias->pm_spec);
2287 if (spec_copy == NULL)
2288 spec_copy = strdup(ctrspec);
2291 ctrname = strsep(&r, ",");
2294 * If a explicit class prefix was given by the user, restrict the
2295 * search for the event to the specified PMC class.
2298 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) {
2299 pcd = pmc_class_table[n];
2300 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) &&
2301 strncasecmp(ctrname, pcd->pm_evc_name,
2302 pcd->pm_evc_name_size) == 0) {
2303 if ((ev = pmc_match_event_class(ctrname +
2304 pcd->pm_evc_name_size, pcd)) == NULL) {
2313 * Otherwise, search for this event in all compatible PMC
2316 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) {
2317 pcd = pmc_class_table[n];
2318 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class))
2319 ev = pmc_match_event_class(ctrname, pcd);
2327 bzero(&pmc_config, sizeof(pmc_config));
2328 pmc_config.pm_ev = ev->pm_ev_code;
2329 pmc_config.pm_class = pcd->pm_evc_class;
2330 pmc_config.pm_cpu = cpu;
2331 pmc_config.pm_mode = mode;
2332 pmc_config.pm_flags = flags;
2334 if (PMC_IS_SAMPLING_MODE(mode))
2335 pmc_config.pm_caps |= PMC_CAP_INTERRUPT;
2337 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) {
2342 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0)
2345 *pmcid = pmc_config.pm_pmcid;
2357 pmc_attach(pmc_id_t pmc, pid_t pid)
2359 struct pmc_op_pmcattach pmc_attach_args;
2361 pmc_attach_args.pm_pmc = pmc;
2362 pmc_attach_args.pm_pid = pid;
2364 return (PMC_CALL(PMCATTACH, &pmc_attach_args));
2368 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps)
2373 cl = PMC_ID_TO_CLASS(pmcid);
2374 for (i = 0; i < cpu_info.pm_nclass; i++)
2375 if (cpu_info.pm_classes[i].pm_class == cl) {
2376 *caps = cpu_info.pm_classes[i].pm_caps;
2384 pmc_configure_logfile(int fd)
2386 struct pmc_op_configurelog cla;
2389 if (PMC_CALL(CONFIGURELOG, &cla) < 0)
2395 pmc_cpuinfo(const struct pmc_cpuinfo **pci)
2397 if (pmc_syscall == -1) {
2407 pmc_detach(pmc_id_t pmc, pid_t pid)
2409 struct pmc_op_pmcattach pmc_detach_args;
2411 pmc_detach_args.pm_pmc = pmc;
2412 pmc_detach_args.pm_pid = pid;
2413 return (PMC_CALL(PMCDETACH, &pmc_detach_args));
2417 pmc_disable(int cpu, int pmc)
2419 struct pmc_op_pmcadmin ssa;
2423 ssa.pm_state = PMC_STATE_DISABLED;
2424 return (PMC_CALL(PMCADMIN, &ssa));
2428 pmc_enable(int cpu, int pmc)
2430 struct pmc_op_pmcadmin ssa;
2434 ssa.pm_state = PMC_STATE_FREE;
2435 return (PMC_CALL(PMCADMIN, &ssa));
2439 * Return a list of events known to a given PMC class. 'cl' is the
2440 * PMC class identifier, 'eventnames' is the returned list of 'const
2441 * char *' pointers pointing to the names of the events. 'nevents' is
2442 * the number of event name pointers returned.
2444 * The space for 'eventnames' is allocated using malloc(3). The caller
2445 * is responsible for freeing this space when done.
2448 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
2453 const struct pmc_event_descr *ev;
2458 ev = iaf_event_table;
2459 count = PMC_EVENT_TABLE_SIZE(iaf);
2463 * Return the most appropriate set of event name
2464 * spellings for the current CPU.
2466 switch (cpu_info.pm_cputype) {
2468 case PMC_CPU_INTEL_ATOM:
2469 ev = atom_event_table;
2470 count = PMC_EVENT_TABLE_SIZE(atom);
2472 case PMC_CPU_INTEL_CORE:
2473 ev = core_event_table;
2474 count = PMC_EVENT_TABLE_SIZE(core);
2476 case PMC_CPU_INTEL_CORE2:
2477 case PMC_CPU_INTEL_CORE2EXTREME:
2478 ev = core2_event_table;
2479 count = PMC_EVENT_TABLE_SIZE(core2);
2481 case PMC_CPU_INTEL_COREI7:
2482 ev = corei7_event_table;
2483 count = PMC_EVENT_TABLE_SIZE(corei7);
2485 case PMC_CPU_INTEL_WESTMERE:
2486 ev = westmere_event_table;
2487 count = PMC_EVENT_TABLE_SIZE(westmere);
2492 ev = ucf_event_table;
2493 count = PMC_EVENT_TABLE_SIZE(ucf);
2497 * Return the most appropriate set of event name
2498 * spellings for the current CPU.
2500 switch (cpu_info.pm_cputype) {
2502 case PMC_CPU_INTEL_COREI7:
2503 ev = corei7uc_event_table;
2504 count = PMC_EVENT_TABLE_SIZE(corei7uc);
2506 case PMC_CPU_INTEL_WESTMERE:
2507 ev = westmereuc_event_table;
2508 count = PMC_EVENT_TABLE_SIZE(westmereuc);
2513 ev = tsc_event_table;
2514 count = PMC_EVENT_TABLE_SIZE(tsc);
2517 ev = k7_event_table;
2518 count = PMC_EVENT_TABLE_SIZE(k7);
2521 ev = k8_event_table;
2522 count = PMC_EVENT_TABLE_SIZE(k8);
2525 ev = p4_event_table;
2526 count = PMC_EVENT_TABLE_SIZE(p4);
2529 ev = p5_event_table;
2530 count = PMC_EVENT_TABLE_SIZE(p5);
2533 ev = p6_event_table;
2534 count = PMC_EVENT_TABLE_SIZE(p6);
2536 case PMC_CLASS_MIPS24K:
2537 ev = mips24k_event_table;
2538 count = PMC_EVENT_TABLE_SIZE(mips24k);
2545 if ((names = malloc(count * sizeof(const char *))) == NULL)
2548 *eventnames = names;
2551 for (;count--; ev++, names++)
2552 *names = ev->pm_ev_name;
2557 pmc_flush_logfile(void)
2559 return (PMC_CALL(FLUSHLOG,0));
2563 pmc_get_driver_stats(struct pmc_driverstats *ds)
2565 struct pmc_op_getdriverstats gms;
2567 if (PMC_CALL(GETDRIVERSTATS, &gms) < 0)
2570 /* copy out fields in the current userland<->library interface */
2571 ds->pm_intr_ignored = gms.pm_intr_ignored;
2572 ds->pm_intr_processed = gms.pm_intr_processed;
2573 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull;
2574 ds->pm_syscalls = gms.pm_syscalls;
2575 ds->pm_syscall_errors = gms.pm_syscall_errors;
2576 ds->pm_buffer_requests = gms.pm_buffer_requests;
2577 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed;
2578 ds->pm_log_sweeps = gms.pm_log_sweeps;
2583 pmc_get_msr(pmc_id_t pmc, uint32_t *msr)
2585 struct pmc_op_getmsr gm;
2588 if (PMC_CALL(PMCGETMSR, &gm) < 0)
2597 int error, pmc_mod_id;
2599 uint32_t abi_version;
2600 struct module_stat pmc_modstat;
2601 struct pmc_op_getcpuinfo op_cpu_info;
2602 #if defined(__amd64__) || defined(__i386__)
2603 int cpu_has_iaf_counters;
2607 if (pmc_syscall != -1) /* already inited */
2610 /* retrieve the system call number from the KLD */
2611 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0)
2614 pmc_modstat.version = sizeof(struct module_stat);
2615 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0)
2618 pmc_syscall = pmc_modstat.data.intval;
2620 /* check the kernel module's ABI against our compiled-in version */
2621 abi_version = PMC_VERSION;
2622 if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0)
2623 return (pmc_syscall = -1);
2625 /* ignore patch & minor numbers for the comparision */
2626 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) {
2627 errno = EPROGMISMATCH;
2628 return (pmc_syscall = -1);
2631 if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0)
2632 return (pmc_syscall = -1);
2634 cpu_info.pm_cputype = op_cpu_info.pm_cputype;
2635 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu;
2636 cpu_info.pm_npmc = op_cpu_info.pm_npmc;
2637 cpu_info.pm_nclass = op_cpu_info.pm_nclass;
2638 for (n = 0; n < cpu_info.pm_nclass; n++)
2639 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n];
2641 pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE *
2642 sizeof(struct pmc_class_descr *));
2644 if (pmc_class_table == NULL)
2647 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++)
2648 pmc_class_table[n] = NULL;
2651 * Fill in the class table.
2654 #if defined(__amd64__) || defined(__i386__)
2655 pmc_class_table[n++] = &tsc_class_table_descr;
2658 * Check if this CPU has fixed function counters.
2660 cpu_has_iaf_counters = 0;
2661 for (t = 0; t < cpu_info.pm_nclass; t++)
2662 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF &&
2663 cpu_info.pm_classes[t].pm_num > 0)
2664 cpu_has_iaf_counters = 1;
2667 #define PMC_MDEP_INIT(C) do { \
2668 pmc_mdep_event_aliases = C##_aliases; \
2669 pmc_mdep_class_list = C##_pmc_classes; \
2670 pmc_mdep_class_list_size = \
2671 PMC_TABLE_SIZE(C##_pmc_classes); \
2674 #define PMC_MDEP_INIT_INTEL_V2(C) do { \
2676 pmc_class_table[n++] = &iaf_class_table_descr; \
2677 if (!cpu_has_iaf_counters) \
2678 pmc_mdep_event_aliases = \
2679 C##_aliases_without_iaf; \
2680 pmc_class_table[n] = &C##_class_table_descr; \
2683 /* Configure the event name parser. */
2684 switch (cpu_info.pm_cputype) {
2685 #if defined(__i386__)
2686 case PMC_CPU_AMD_K7:
2688 pmc_class_table[n] = &k7_class_table_descr;
2690 case PMC_CPU_INTEL_P5:
2692 pmc_class_table[n] = &p5_class_table_descr;
2694 case PMC_CPU_INTEL_P6: /* P6 ... Pentium M CPUs have */
2695 case PMC_CPU_INTEL_PII: /* similar PMCs. */
2696 case PMC_CPU_INTEL_PIII:
2697 case PMC_CPU_INTEL_PM:
2699 pmc_class_table[n] = &p6_class_table_descr;
2702 #if defined(__amd64__) || defined(__i386__)
2703 case PMC_CPU_AMD_K8:
2705 pmc_class_table[n] = &k8_class_table_descr;
2707 case PMC_CPU_INTEL_ATOM:
2708 PMC_MDEP_INIT_INTEL_V2(atom);
2710 case PMC_CPU_INTEL_CORE:
2711 PMC_MDEP_INIT(core);
2712 pmc_class_table[n] = &core_class_table_descr;
2714 case PMC_CPU_INTEL_CORE2:
2715 case PMC_CPU_INTEL_CORE2EXTREME:
2716 PMC_MDEP_INIT_INTEL_V2(core2);
2718 case PMC_CPU_INTEL_COREI7:
2719 pmc_class_table[n++] = &ucf_class_table_descr;
2720 pmc_class_table[n++] = &corei7uc_class_table_descr;
2721 PMC_MDEP_INIT_INTEL_V2(corei7);
2723 case PMC_CPU_INTEL_WESTMERE:
2724 pmc_class_table[n++] = &ucf_class_table_descr;
2725 pmc_class_table[n++] = &westmereuc_class_table_descr;
2726 PMC_MDEP_INIT_INTEL_V2(westmere);
2728 case PMC_CPU_INTEL_PIV:
2730 pmc_class_table[n] = &p4_class_table_descr;
2733 #if defined(__mips__)
2734 case PMC_CPU_MIPS_24K:
2735 PMC_MDEP_INIT(mips24k);
2736 pmc_class_table[n] = &mips24k_class_table_descr;
2738 #endif /* __mips__ */
2741 * Some kind of CPU this version of the library knows nothing
2742 * about. This shouldn't happen since the abi version check
2743 * should have caught this.
2746 return (pmc_syscall = -1);
2753 pmc_name_of_capability(enum pmc_caps cap)
2758 * 'cap' should have a single bit set and should be in
2761 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST ||
2762 cap > PMC_CAP_LAST) {
2768 return (pmc_capability_names[i - 1]);
2772 pmc_name_of_class(enum pmc_class pc)
2774 if ((int) pc >= PMC_CLASS_FIRST &&
2775 pc <= PMC_CLASS_LAST)
2776 return (pmc_class_names[pc]);
2783 pmc_name_of_cputype(enum pmc_cputype cp)
2787 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++)
2788 if (cp == pmc_cputype_names[n].pm_cputype)
2789 return (pmc_cputype_names[n].pm_name);
2796 pmc_name_of_disposition(enum pmc_disp pd)
2798 if ((int) pd >= PMC_DISP_FIRST &&
2799 pd <= PMC_DISP_LAST)
2800 return (pmc_disposition_names[pd]);
2807 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
2809 const struct pmc_event_descr *ev, *evfence;
2811 ev = evfence = NULL;
2812 if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) {
2813 ev = iaf_event_table;
2814 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf);
2815 } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) {
2817 case PMC_CPU_INTEL_ATOM:
2818 ev = atom_event_table;
2819 evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom);
2821 case PMC_CPU_INTEL_CORE:
2822 ev = core_event_table;
2823 evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core);
2825 case PMC_CPU_INTEL_CORE2:
2826 case PMC_CPU_INTEL_CORE2EXTREME:
2827 ev = core2_event_table;
2828 evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2);
2830 case PMC_CPU_INTEL_COREI7:
2831 ev = corei7_event_table;
2832 evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7);
2834 case PMC_CPU_INTEL_WESTMERE:
2835 ev = westmere_event_table;
2836 evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere);
2838 default: /* Unknown CPU type. */
2841 } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) {
2842 ev = ucf_event_table;
2843 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf);
2844 } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) {
2846 case PMC_CPU_INTEL_COREI7:
2847 ev = corei7uc_event_table;
2848 evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc);
2850 case PMC_CPU_INTEL_WESTMERE:
2851 ev = westmereuc_event_table;
2852 evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc);
2854 default: /* Unknown CPU type. */
2857 } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) {
2858 ev = k7_event_table;
2859 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7);
2860 } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
2861 ev = k8_event_table;
2862 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
2863 } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) {
2864 ev = p4_event_table;
2865 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4);
2866 } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) {
2867 ev = p5_event_table;
2868 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5);
2869 } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) {
2870 ev = p6_event_table;
2871 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6);
2872 } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) {
2873 ev = mips24k_event_table;
2874 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k
2876 } else if (pe == PMC_EV_TSC_TSC) {
2877 ev = tsc_event_table;
2878 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc);
2881 for (; ev != evfence; ev++)
2882 if (pe == ev->pm_ev_code)
2883 return (ev->pm_ev_name);
2889 pmc_name_of_event(enum pmc_event pe)
2893 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL)
2901 pmc_name_of_mode(enum pmc_mode pm)
2903 if ((int) pm >= PMC_MODE_FIRST &&
2904 pm <= PMC_MODE_LAST)
2905 return (pmc_mode_names[pm]);
2912 pmc_name_of_state(enum pmc_state ps)
2914 if ((int) ps >= PMC_STATE_FIRST &&
2915 ps <= PMC_STATE_LAST)
2916 return (pmc_state_names[ps]);
2925 if (pmc_syscall == -1) {
2930 return (cpu_info.pm_ncpu);
2936 if (pmc_syscall == -1) {
2941 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) {
2946 return (cpu_info.pm_npmc);
2950 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci)
2953 struct pmc_op_getpmcinfo *pmci;
2955 if ((npmc = pmc_npmc(cpu)) < 0)
2958 nbytes = sizeof(struct pmc_op_getpmcinfo) +
2959 npmc * sizeof(struct pmc_info);
2961 if ((pmci = calloc(1, nbytes)) == NULL)
2966 if (PMC_CALL(GETPMCINFO, pmci) < 0) {
2971 /* kernel<->library, library<->userland interfaces are identical */
2972 *ppmci = (struct pmc_pmcinfo *) pmci;
2977 pmc_read(pmc_id_t pmc, pmc_value_t *value)
2979 struct pmc_op_pmcrw pmc_read_op;
2981 pmc_read_op.pm_pmcid = pmc;
2982 pmc_read_op.pm_flags = PMC_F_OLDVALUE;
2983 pmc_read_op.pm_value = -1;
2985 if (PMC_CALL(PMCRW, &pmc_read_op) < 0)
2988 *value = pmc_read_op.pm_value;
2993 pmc_release(pmc_id_t pmc)
2995 struct pmc_op_simple pmc_release_args;
2997 pmc_release_args.pm_pmcid = pmc;
2998 return (PMC_CALL(PMCRELEASE, &pmc_release_args));
3002 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep)
3004 struct pmc_op_pmcrw pmc_rw_op;
3006 pmc_rw_op.pm_pmcid = pmc;
3007 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE;
3008 pmc_rw_op.pm_value = newvalue;
3010 if (PMC_CALL(PMCRW, &pmc_rw_op) < 0)
3013 *oldvaluep = pmc_rw_op.pm_value;
3018 pmc_set(pmc_id_t pmc, pmc_value_t value)
3020 struct pmc_op_pmcsetcount sc;
3023 sc.pm_count = value;
3025 if (PMC_CALL(PMCSETCOUNT, &sc) < 0)
3031 pmc_start(pmc_id_t pmc)
3033 struct pmc_op_simple pmc_start_args;
3035 pmc_start_args.pm_pmcid = pmc;
3036 return (PMC_CALL(PMCSTART, &pmc_start_args));
3040 pmc_stop(pmc_id_t pmc)
3042 struct pmc_op_simple pmc_stop_args;
3044 pmc_stop_args.pm_pmcid = pmc;
3045 return (PMC_CALL(PMCSTOP, &pmc_stop_args));
3049 pmc_width(pmc_id_t pmcid, uint32_t *width)
3054 cl = PMC_ID_TO_CLASS(pmcid);
3055 for (i = 0; i < cpu_info.pm_nclass; i++)
3056 if (cpu_info.pm_classes[i].pm_class == cl) {
3057 *width = cpu_info.pm_classes[i].pm_width;
3065 pmc_write(pmc_id_t pmc, pmc_value_t value)
3067 struct pmc_op_pmcrw pmc_write_op;
3069 pmc_write_op.pm_pmcid = pmc;
3070 pmc_write_op.pm_flags = PMC_F_NEWVALUE;
3071 pmc_write_op.pm_value = value;
3072 return (PMC_CALL(PMCRW, &pmc_write_op));
3076 pmc_writelog(uint32_t userdata)
3078 struct pmc_op_writelog wl;
3080 wl.pm_userdata = userdata;
3081 return (PMC_CALL(WRITELOG, &wl));