lib/libpmc/libpmc.c

   1 /*-
   2  * Copyright (c) 2003-2008 Joseph Koshy
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/types.h>
  31 #include <sys/module.h>
  32 #include <sys/pmc.h>
  33 #include <sys/syscall.h>
  34
  35 #include <ctype.h>
  36 #include <errno.h>
  37 #include <fcntl.h>
  38 #include <pmc.h>
  39 #include <stdio.h>
  40 #include <stdlib.h>
  41 #include <string.h>
  42 #include <strings.h>
  43 #include <unistd.h>
  44
  45 #include "libpmcinternal.h"
  46
  47 /* Function prototypes */
  48 #if defined(__i386__)
  49 static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  50     struct pmc_op_pmcallocate *_pmc_config);
  51 #endif
  52 #if defined(__amd64__) || defined(__i386__)
  53 static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  54     struct pmc_op_pmcallocate *_pmc_config);
  55 static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  56     struct pmc_op_pmcallocate *_pmc_config);
  57 static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  58     struct pmc_op_pmcallocate *_pmc_config);
  59 static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  60     struct pmc_op_pmcallocate *_pmc_config);
  61 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  62     struct pmc_op_pmcallocate *_pmc_config);
  63 static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  64     struct pmc_op_pmcallocate *_pmc_config);
  65 #endif
  66 #if defined(__i386__)
  67 static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  68     struct pmc_op_pmcallocate *_pmc_config);
  69 static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  70     struct pmc_op_pmcallocate *_pmc_config);
  71 #endif
  72 #if defined(__amd64__) || defined(__i386__)
  73 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  74     struct pmc_op_pmcallocate *_pmc_config);
  75 #endif
  76 #if defined(__XSCALE__)
  77 static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  78     struct pmc_op_pmcallocate *_pmc_config);
  79 #endif
  80 #if defined(__mips__)
  81 static int mips24k_allocate_pmc(enum pmc_event _pe, char* ctrspec,
  82                              struct pmc_op_pmcallocate *_pmc_config);
  83 #endif /* __mips__ */
  84 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  85     struct pmc_op_pmcallocate *_pmc_config);
  86
  87 #if defined(__powerpc__)
  88 static int ppc7450_allocate_pmc(enum pmc_event _pe, char* ctrspec,
  89                              struct pmc_op_pmcallocate *_pmc_config);
  90 #endif /* __powerpc__ */
  91
  92 #define PMC_CALL(cmd, params)                           \
  93         syscall(pmc_syscall, PMC_OP_##cmd, (params))
  94
  95 /*
  96  * Event aliases provide a way for the user to ask for generic events
  97  * like "cache-misses", or "instructions-retired".  These aliases are
  98  * mapped to the appropriate canonical event descriptions using a
  99  * lookup table.
 100  */
 101 struct pmc_event_alias {
 102         const char      *pm_alias;
 103         const char      *pm_spec;
 104 };
 105
 106 static const struct pmc_event_alias *pmc_mdep_event_aliases;
 107
 108 /*
 109  * The pmc_event_descr structure maps symbolic names known to the user
 110  * to integer codes used by the PMC KLD.
 111  */
 112 struct pmc_event_descr {
 113         const char      *pm_ev_name;
 114         enum pmc_event  pm_ev_code;
 115 };
 116
 117 /*
 118  * The pmc_class_descr structure maps class name prefixes for
 119  * event names to event tables and other PMC class data.
 120  */
 121 struct pmc_class_descr {
 122         const char      *pm_evc_name;
 123         size_t          pm_evc_name_size;
 124         enum pmc_class  pm_evc_class;
 125         const struct pmc_event_descr *pm_evc_event_table;
 126         size_t          pm_evc_event_table_size;
 127         int             (*pm_evc_allocate_pmc)(enum pmc_event _pe,
 128                             char *_ctrspec, struct pmc_op_pmcallocate *_pa);
 129 };
 130
 131 #define PMC_TABLE_SIZE(N)       (sizeof(N)/sizeof(N[0]))
 132 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table)
 133
 134 #undef  __PMC_EV
 135 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N },
 136
 137 /*
 138  * PMC_CLASSDEP_TABLE(NAME, CLASS)
 139  *
 140  * Define a table mapping event names and aliases to HWPMC event IDs.
 141  */
 142 #define PMC_CLASSDEP_TABLE(N, C)                                \
 143         static const struct pmc_event_descr N##_event_table[] = \
 144         {                                                       \
 145                 __PMC_EV_##C()                                  \
 146         }
 147
 148 PMC_CLASSDEP_TABLE(iaf, IAF);
 149 PMC_CLASSDEP_TABLE(k7, K7);
 150 PMC_CLASSDEP_TABLE(k8, K8);
 151 PMC_CLASSDEP_TABLE(p4, P4);
 152 PMC_CLASSDEP_TABLE(p5, P5);
 153 PMC_CLASSDEP_TABLE(p6, P6);
 154 PMC_CLASSDEP_TABLE(xscale, XSCALE);
 155 PMC_CLASSDEP_TABLE(mips24k, MIPS24K);
 156 PMC_CLASSDEP_TABLE(ucf, UCF);
 157 PMC_CLASSDEP_TABLE(ppc7450, PPC7450);
 158
 159 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT];
 160
 161 #undef  __PMC_EV_ALIAS
 162 #define __PMC_EV_ALIAS(N,CODE)  { N, PMC_EV_##CODE },
 163
 164 static const struct pmc_event_descr atom_event_table[] =
 165 {
 166         __PMC_EV_ALIAS_ATOM()
 167 };
 168
 169 static const struct pmc_event_descr core_event_table[] =
 170 {
 171         __PMC_EV_ALIAS_CORE()
 172 };
 173
 174
 175 static const struct pmc_event_descr core2_event_table[] =
 176 {
 177         __PMC_EV_ALIAS_CORE2()
 178 };
 179
 180 static const struct pmc_event_descr corei7_event_table[] =
 181 {
 182         __PMC_EV_ALIAS_COREI7()
 183 };
 184
 185 static const struct pmc_event_descr sandybridge_event_table[] =
 186 {
 187         __PMC_EV_ALIAS_SANDYBRIDGE()
 188 };
 189
 190 static const struct pmc_event_descr westmere_event_table[] =
 191 {
 192         __PMC_EV_ALIAS_WESTMERE()
 193 };
 194
 195 static const struct pmc_event_descr corei7uc_event_table[] =
 196 {
 197         __PMC_EV_ALIAS_COREI7UC()
 198 };
 199
 200 static const struct pmc_event_descr sandybridgeuc_event_table[] =
 201 {
 202         __PMC_EV_ALIAS_SANDYBRIDGEUC()
 203 };
 204
 205 static const struct pmc_event_descr westmereuc_event_table[] =
 206 {
 207         __PMC_EV_ALIAS_WESTMEREUC()
 208 };
 209
 210 /*
 211  * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...)
 212  *
 213  * Map a CPU to the PMC classes it supports.
 214  */
 215 #define PMC_MDEP_TABLE(N,C,...)                         \
 216         static const enum pmc_class N##_pmc_classes[] = {       \
 217                 PMC_CLASS_##C, __VA_ARGS__                      \
 218         }
 219
 220 PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 221 PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 222 PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 223 PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 224 PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 225 PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 226 PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 227 PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 228 PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 229 PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 230 PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 231 PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE);
 232 PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K);
 233 PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450);
 234 PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT);
 235
 236 static const struct pmc_event_descr tsc_event_table[] =
 237 {
 238         __PMC_EV_TSC()
 239 };
 240
 241 #undef  PMC_CLASS_TABLE_DESC
 242 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR)    \
 243 static const struct pmc_class_descr NAME##_class_table_descr =  \
 244         {                                                       \
 245                 .pm_evc_name  = #CLASS "-",                     \
 246                 .pm_evc_name_size = sizeof(#CLASS "-") - 1,     \
 247                 .pm_evc_class = PMC_CLASS_##CLASS ,             \
 248                 .pm_evc_event_table = EVENTS##_event_table ,    \
 249                 .pm_evc_event_table_size =                      \
 250                         PMC_EVENT_TABLE_SIZE(EVENTS),           \
 251                 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \
 252         }
 253
 254 #if     defined(__i386__) || defined(__amd64__)
 255 PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf);
 256 PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap);
 257 PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
 258 PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
 259 PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
 260 PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap);
 261 PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
 262 PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
 263 PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
 264 PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp);
 265 PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp);
 266 #endif
 267 #if     defined(__i386__)
 268 PMC_CLASS_TABLE_DESC(k7, K7, k7, k7);
 269 #endif
 270 #if     defined(__i386__) || defined(__amd64__)
 271 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
 272 PMC_CLASS_TABLE_DESC(p4, P4, p4, p4);
 273 #endif
 274 #if     defined(__i386__)
 275 PMC_CLASS_TABLE_DESC(p5, P5, p5, p5);
 276 PMC_CLASS_TABLE_DESC(p6, P6, p6, p6);
 277 #endif
 278 #if     defined(__i386__) || defined(__amd64__)
 279 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);
 280 #endif
 281 #if     defined(__XSCALE__)
 282 PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale);
 283 #endif
 284 #if defined(__mips__)
 285 PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips24k);
 286 #endif /* __mips__ */
 287 #if defined(__powerpc__)
 288 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, ppc7450);
 289 #endif
 290
 291 static struct pmc_class_descr soft_class_table_descr =
 292 {
 293         .pm_evc_name  = "SOFT-",
 294         .pm_evc_name_size = sizeof("SOFT-") - 1,
 295         .pm_evc_class = PMC_CLASS_SOFT,
 296         .pm_evc_event_table = NULL,
 297         .pm_evc_event_table_size = 0,
 298         .pm_evc_allocate_pmc = soft_allocate_pmc
 299 };
 300
 301 #undef  PMC_CLASS_TABLE_DESC
 302
 303 static const struct pmc_class_descr **pmc_class_table;
 304 #define PMC_CLASS_TABLE_SIZE    cpu_info.pm_nclass
 305
 306 static const enum pmc_class *pmc_mdep_class_list;
 307 static size_t pmc_mdep_class_list_size;
 308
 309 /*
 310  * Mapping tables, mapping enumeration values to human readable
 311  * strings.
 312  */
 313
 314 static const char * pmc_capability_names[] = {
 315 #undef  __PMC_CAP
 316 #define __PMC_CAP(N,V,D)        #N ,
 317         __PMC_CAPS()
 318 };
 319
 320 static const char * pmc_class_names[] = {
 321 #undef  __PMC_CLASS
 322 #define __PMC_CLASS(C)  #C ,
 323         __PMC_CLASSES()
 324 };
 325
 326 struct pmc_cputype_map {
 327         enum pmc_cputype pm_cputype;
 328         const char      *pm_name;
 329 };
 330
 331 static const struct pmc_cputype_map pmc_cputype_names[] = {
 332 #undef  __PMC_CPU
 333 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } ,
 334         __PMC_CPUS()
 335 };
 336
 337 static const char * pmc_disposition_names[] = {
 338 #undef  __PMC_DISP
 339 #define __PMC_DISP(D)   #D ,
 340         __PMC_DISPOSITIONS()
 341 };
 342
 343 static const char * pmc_mode_names[] = {
 344 #undef  __PMC_MODE
 345 #define __PMC_MODE(M,N) #M ,
 346         __PMC_MODES()
 347 };
 348
 349 static const char * pmc_state_names[] = {
 350 #undef  __PMC_STATE
 351 #define __PMC_STATE(S) #S ,
 352         __PMC_STATES()
 353 };
 354
 355 /*
 356  * Filled in by pmc_init().
 357  */
 358 static int pmc_syscall = -1;
 359 static struct pmc_cpuinfo cpu_info;
 360 static struct pmc_op_getdyneventinfo soft_event_info;
 361
 362 /* Event masks for events */
 363 struct pmc_masks {
 364         const char      *pm_name;
 365         const uint32_t  pm_value;
 366 };
 367 #define PMCMASK(N,V)    { .pm_name = #N, .pm_value = (V) }
 368 #define NULLMASK        { .pm_name = NULL }
 369
 370 #if defined(__amd64__) || defined(__i386__)
 371 static int
 372 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint32_t *evmask)
 373 {
 374         const struct pmc_masks *pm;
 375         char *q, *r;
 376         int c;
 377
 378         if (pmask == NULL)      /* no mask keywords */
 379                 return (-1);
 380         q = strchr(p, '=');     /* skip '=' */
 381         if (*++q == '\0')       /* no more data */
 382                 return (-1);
 383         c = 0;                  /* count of mask keywords seen */
 384         while ((r = strsep(&q, "+")) != NULL) {
 385                 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name);
 386                     pm++)
 387                         ;
 388                 if (pm->pm_name == NULL) /* not found */
 389                         return (-1);
 390                 *evmask |= pm->pm_value;
 391                 c++;
 392         }
 393         return (c);
 394 }
 395 #endif
 396
 397 #define KWMATCH(p,kw)           (strcasecmp((p), (kw)) == 0)
 398 #define KWPREFIXMATCH(p,kw)     (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0)
 399 #define EV_ALIAS(N,S)           { .pm_alias = N, .pm_spec = S }
 400
 401 #if defined(__i386__)
 402
 403 /*
 404  * AMD K7 (Athlon) CPUs.
 405  */
 406
 407 static struct pmc_event_alias k7_aliases[] = {
 408         EV_ALIAS("branches",            "k7-retired-branches"),
 409         EV_ALIAS("branch-mispredicts",  "k7-retired-branches-mispredicted"),
 410         EV_ALIAS("cycles",              "tsc"),
 411         EV_ALIAS("dc-misses",           "k7-dc-misses"),
 412         EV_ALIAS("ic-misses",           "k7-ic-misses"),
 413         EV_ALIAS("instructions",        "k7-retired-instructions"),
 414         EV_ALIAS("interrupts",          "k7-hardware-interrupts"),
 415         EV_ALIAS(NULL, NULL)
 416 };
 417
 418 #define K7_KW_COUNT     "count"
 419 #define K7_KW_EDGE      "edge"
 420 #define K7_KW_INV       "inv"
 421 #define K7_KW_OS        "os"
 422 #define K7_KW_UNITMASK  "unitmask"
 423 #define K7_KW_USR       "usr"
 424
 425 static int
 426 k7_allocate_pmc(enum pmc_event pe, char *ctrspec,
 427     struct pmc_op_pmcallocate *pmc_config)
 428 {
 429         char            *e, *p, *q;
 430         int             c, has_unitmask;
 431         uint32_t        count, unitmask;
 432
 433         pmc_config->pm_md.pm_amd.pm_amd_config = 0;
 434         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
 435
 436         if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 ||
 437             pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM ||
 438             pe == PMC_EV_K7_DC_WRITEBACKS) {
 439                 has_unitmask = 1;
 440                 unitmask = AMD_PMC_UNITMASK_MOESI;
 441         } else
 442                 unitmask = has_unitmask = 0;
 443
 444         while ((p = strsep(&ctrspec, ",")) != NULL) {
 445                 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) {
 446                         q = strchr(p, '=');
 447                         if (*++q == '\0') /* skip '=' */
 448                                 return (-1);
 449
 450                         count = strtol(q, &e, 0);
 451                         if (e == q || *e != '\0')
 452                                 return (-1);
 453
 454                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
 455                         pmc_config->pm_md.pm_amd.pm_amd_config |=
 456                             AMD_PMC_TO_COUNTER(count);
 457
 458                 } else if (KWMATCH(p, K7_KW_EDGE)) {
 459                         pmc_config->pm_caps |= PMC_CAP_EDGE;
 460                 } else if (KWMATCH(p, K7_KW_INV)) {
 461                         pmc_config->pm_caps |= PMC_CAP_INVERT;
 462                 } else if (KWMATCH(p, K7_KW_OS)) {
 463                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
 464                 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) {
 465                         if (has_unitmask == 0)
 466                                 return (-1);
 467                         unitmask = 0;
 468                         q = strchr(p, '=');
 469                         if (*++q == '\0') /* skip '=' */
 470                                 return (-1);
 471
 472                         while ((c = tolower(*q++)) != 0)
 473                                 if (c == 'm')
 474                                         unitmask |= AMD_PMC_UNITMASK_M;
 475                                 else if (c == 'o')
 476                                         unitmask |= AMD_PMC_UNITMASK_O;
 477                                 else if (c == 'e')
 478                                         unitmask |= AMD_PMC_UNITMASK_E;
 479                                 else if (c == 's')
 480                                         unitmask |= AMD_PMC_UNITMASK_S;
 481                                 else if (c == 'i')
 482                                         unitmask |= AMD_PMC_UNITMASK_I;
 483                                 else if (c == '+')
 484                                         continue;
 485                                 else
 486                                         return (-1);
 487
 488                         if (unitmask == 0)
 489                                 return (-1);
 490
 491                 } else if (KWMATCH(p, K7_KW_USR)) {
 492                         pmc_config->pm_caps |= PMC_CAP_USER;
 493                 } else
 494                         return (-1);
 495         }
 496
 497         if (has_unitmask) {
 498                 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
 499                 pmc_config->pm_md.pm_amd.pm_amd_config |=
 500                     AMD_PMC_TO_UNITMASK(unitmask);
 501         }
 502
 503         return (0);
 504
 505 }
 506
 507 #endif
 508
 509 #if defined(__amd64__) || defined(__i386__)
 510
 511 /*
 512  * Intel Core (Family 6, Model E) PMCs.
 513  */
 514
 515 static struct pmc_event_alias core_aliases[] = {
 516         EV_ALIAS("branches",            "iap-br-instr-ret"),
 517         EV_ALIAS("branch-mispredicts",  "iap-br-mispred-ret"),
 518         EV_ALIAS("cycles",              "tsc-tsc"),
 519         EV_ALIAS("ic-misses",           "iap-icache-misses"),
 520         EV_ALIAS("instructions",        "iap-instr-ret"),
 521         EV_ALIAS("interrupts",          "iap-core-hw-int-rx"),
 522         EV_ALIAS("unhalted-cycles",     "iap-unhalted-core-cycles"),
 523         EV_ALIAS(NULL, NULL)
 524 };
 525
 526 /*
 527  * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H)
 528  * and Atom (Family 6, model 1CH) PMCs.
 529  *
 530  * We map aliases to events on the fixed-function counters if these
 531  * are present.  Note that not all CPUs in this family contain fixed-function
 532  * counters.
 533  */
 534
 535 static struct pmc_event_alias core2_aliases[] = {
 536         EV_ALIAS("branches",            "iap-br-inst-retired.any"),
 537         EV_ALIAS("branch-mispredicts",  "iap-br-inst-retired.mispred"),
 538         EV_ALIAS("cycles",              "tsc-tsc"),
 539         EV_ALIAS("ic-misses",           "iap-l1i-misses"),
 540         EV_ALIAS("instructions",        "iaf-instr-retired.any"),
 541         EV_ALIAS("interrupts",          "iap-hw-int-rcv"),
 542         EV_ALIAS("unhalted-cycles",     "iaf-cpu-clk-unhalted.core"),
 543         EV_ALIAS(NULL, NULL)
 544 };
 545
 546 static struct pmc_event_alias core2_aliases_without_iaf[] = {
 547         EV_ALIAS("branches",            "iap-br-inst-retired.any"),
 548         EV_ALIAS("branch-mispredicts",  "iap-br-inst-retired.mispred"),
 549         EV_ALIAS("cycles",              "tsc-tsc"),
 550         EV_ALIAS("ic-misses",           "iap-l1i-misses"),
 551         EV_ALIAS("instructions",        "iap-inst-retired.any_p"),
 552         EV_ALIAS("interrupts",          "iap-hw-int-rcv"),
 553         EV_ALIAS("unhalted-cycles",     "iap-cpu-clk-unhalted.core_p"),
 554         EV_ALIAS(NULL, NULL)
 555 };
 556
 557 #define atom_aliases                    core2_aliases
 558 #define atom_aliases_without_iaf        core2_aliases_without_iaf
 559 #define corei7_aliases                  core2_aliases
 560 #define corei7_aliases_without_iaf      core2_aliases_without_iaf
 561 #define sandybridge_aliases             core2_aliases
 562 #define sandybridge_aliases_without_iaf core2_aliases_without_iaf
 563 #define westmere_aliases                core2_aliases
 564 #define westmere_aliases_without_iaf    core2_aliases_without_iaf
 565
 566 #define IAF_KW_OS               "os"
 567 #define IAF_KW_USR              "usr"
 568 #define IAF_KW_ANYTHREAD        "anythread"
 569
 570 /*
 571  * Parse an event specifier for Intel fixed function counters.
 572  */
 573 static int
 574 iaf_allocate_pmc(enum pmc_event pe, char *ctrspec,
 575     struct pmc_op_pmcallocate *pmc_config)
 576 {
 577         char *p;
 578
 579         (void) pe;
 580
 581         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
 582         pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0;
 583
 584         while ((p = strsep(&ctrspec, ",")) != NULL) {
 585                 if (KWMATCH(p, IAF_KW_OS))
 586                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
 587                 else if (KWMATCH(p, IAF_KW_USR))
 588                         pmc_config->pm_caps |= PMC_CAP_USER;
 589                 else if (KWMATCH(p, IAF_KW_ANYTHREAD))
 590                         pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY;
 591                 else
 592                         return (-1);
 593         }
 594
 595         return (0);
 596 }
 597
 598 /*
 599  * Core/Core2 support.
 600  */
 601
 602 #define IAP_KW_AGENT            "agent"
 603 #define IAP_KW_ANYTHREAD        "anythread"
 604 #define IAP_KW_CACHESTATE       "cachestate"
 605 #define IAP_KW_CMASK            "cmask"
 606 #define IAP_KW_CORE             "core"
 607 #define IAP_KW_EDGE             "edge"
 608 #define IAP_KW_INV              "inv"
 609 #define IAP_KW_OS               "os"
 610 #define IAP_KW_PREFETCH         "prefetch"
 611 #define IAP_KW_SNOOPRESPONSE    "snoopresponse"
 612 #define IAP_KW_SNOOPTYPE        "snooptype"
 613 #define IAP_KW_TRANSITION       "trans"
 614 #define IAP_KW_USR              "usr"
 615 #define IAP_KW_RSP              "rsp"
 616
 617 static struct pmc_masks iap_core_mask[] = {
 618         PMCMASK(all,    (0x3 << 14)),
 619         PMCMASK(this,   (0x1 << 14)),
 620         NULLMASK
 621 };
 622
 623 static struct pmc_masks iap_agent_mask[] = {
 624         PMCMASK(this,   0),
 625         PMCMASK(any,    (0x1 << 13)),
 626         NULLMASK
 627 };
 628
 629 static struct pmc_masks iap_prefetch_mask[] = {
 630         PMCMASK(both,           (0x3 << 12)),
 631         PMCMASK(only,           (0x1 << 12)),
 632         PMCMASK(exclude,        0),
 633         NULLMASK
 634 };
 635
 636 static struct pmc_masks iap_cachestate_mask[] = {
 637         PMCMASK(i,              (1 <<  8)),
 638         PMCMASK(s,              (1 <<  9)),
 639         PMCMASK(e,              (1 << 10)),
 640         PMCMASK(m,              (1 << 11)),
 641         NULLMASK
 642 };
 643
 644 static struct pmc_masks iap_snoopresponse_mask[] = {
 645         PMCMASK(clean,          (1 << 8)),
 646         PMCMASK(hit,            (1 << 9)),
 647         PMCMASK(hitm,           (1 << 11)),
 648         NULLMASK
 649 };
 650
 651 static struct pmc_masks iap_snooptype_mask[] = {
 652         PMCMASK(cmp2s,          (1 << 8)),
 653         PMCMASK(cmp2i,          (1 << 9)),
 654         NULLMASK
 655 };
 656
 657 static struct pmc_masks iap_transition_mask[] = {
 658         PMCMASK(any,            0x00),
 659         PMCMASK(frequency,      0x10),
 660         NULLMASK
 661 };
 662
 663 static struct pmc_masks iap_rsp_mask[] = {
 664         PMCMASK(DMND_DATA_RD,           (1 <<  0)),
 665         PMCMASK(DMND_RFO,               (1 <<  1)),
 666         PMCMASK(DMND_IFETCH,            (1 <<  2)),
 667         PMCMASK(WB,                     (1 <<  3)),
 668         PMCMASK(PF_DATA_RD,             (1 <<  4)),
 669         PMCMASK(PF_RFO,                 (1 <<  5)),
 670         PMCMASK(PF_IFETCH,              (1 <<  6)),
 671         PMCMASK(OTHER,                  (1 <<  7)),
 672         PMCMASK(UNCORE_HIT,             (1 <<  8)),
 673         PMCMASK(OTHER_CORE_HIT_SNP,     (1 <<  9)),
 674         PMCMASK(OTHER_CORE_HITM,        (1 << 10)),
 675         PMCMASK(REMOTE_CACHE_FWD,       (1 << 12)),
 676         PMCMASK(REMOTE_DRAM,            (1 << 13)),
 677         PMCMASK(LOCAL_DRAM,             (1 << 14)),
 678         PMCMASK(NON_DRAM,               (1 << 15)),
 679         NULLMASK
 680 };
 681
 682 static int
 683 iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
 684     struct pmc_op_pmcallocate *pmc_config)
 685 {
 686         char *e, *p, *q;
 687         uint32_t cachestate, evmask, rsp;
 688         int count, n;
 689
 690         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
 691             PMC_CAP_QUALIFIER);
 692         pmc_config->pm_md.pm_iap.pm_iap_config = 0;
 693
 694         cachestate = evmask = rsp = 0;
 695
 696         /* Parse additional modifiers if present */
 697         while ((p = strsep(&ctrspec, ",")) != NULL) {
 698
 699                 n = 0;
 700                 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) {
 701                         q = strchr(p, '=');
 702                         if (*++q == '\0') /* skip '=' */
 703                                 return (-1);
 704                         count = strtol(q, &e, 0);
 705                         if (e == q || *e != '\0')
 706                                 return (-1);
 707                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
 708                         pmc_config->pm_md.pm_iap.pm_iap_config |=
 709                             IAP_CMASK(count);
 710                 } else if (KWMATCH(p, IAP_KW_EDGE)) {
 711                         pmc_config->pm_caps |= PMC_CAP_EDGE;
 712                 } else if (KWMATCH(p, IAP_KW_INV)) {
 713                         pmc_config->pm_caps |= PMC_CAP_INVERT;
 714                 } else if (KWMATCH(p, IAP_KW_OS)) {
 715                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
 716                 } else if (KWMATCH(p, IAP_KW_USR)) {
 717                         pmc_config->pm_caps |= PMC_CAP_USER;
 718                 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) {
 719                         pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY;
 720                 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) {
 721                         n = pmc_parse_mask(iap_core_mask, p, &evmask);
 722                         if (n != 1)
 723                                 return (-1);
 724                 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) {
 725                         n = pmc_parse_mask(iap_agent_mask, p, &evmask);
 726                         if (n != 1)
 727                                 return (-1);
 728                 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) {
 729                         n = pmc_parse_mask(iap_prefetch_mask, p, &evmask);
 730                         if (n != 1)
 731                                 return (-1);
 732                 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) {
 733                         n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate);
 734                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE &&
 735                     KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) {
 736                         n = pmc_parse_mask(iap_transition_mask, p, &evmask);
 737                         if (n != 1)
 738                                 return (-1);
 739                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM ||
 740                     cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 ||
 741                     cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) {
 742                         if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) {
 743                                 n = pmc_parse_mask(iap_snoopresponse_mask, p,
 744                                     &evmask);
 745                         } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) {
 746                                 n = pmc_parse_mask(iap_snooptype_mask, p,
 747                                     &evmask);
 748                         } else
 749                                 return (-1);
 750                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 ||
 751                     cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) {
 752                         if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
 753                                 n = pmc_parse_mask(iap_rsp_mask, p, &rsp);
 754                         } else
 755                                 return (-1);
 756                 } else
 757                         return (-1);
 758
 759                 if (n < 0)      /* Parsing failed. */
 760                         return (-1);
 761         }
 762
 763         pmc_config->pm_md.pm_iap.pm_iap_config |= evmask;
 764
 765         /*
 766          * If the event requires a 'cachestate' qualifier but was not
 767          * specified by the user, use a sensible default.
 768          */
 769         switch (pe) {
 770         case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */
 771         case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */
 772         case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */
 773         case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */
 774         case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */
 775         case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */
 776         case PMC_EV_IAP_EVENT_32H: /* Core */
 777         case PMC_EV_IAP_EVENT_40H: /* Core */
 778         case PMC_EV_IAP_EVENT_41H: /* Core */
 779         case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */
 780                 if (cachestate == 0)
 781                         cachestate = (0xF << 8);
 782                 break;
 783         case PMC_EV_IAP_EVENT_77H: /* Atom */
 784                 /* IAP_EVENT_77H only accepts a cachestate qualifier on the
 785                  * Atom processor
 786                  */
 787                 if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0)
 788                         cachestate = (0xF << 8);
 789             break;
 790         default:
 791                 break;
 792         }
 793
 794         pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate;
 795         pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp;
 796
 797         return (0);
 798 }
 799
 800 /*
 801  * Intel Uncore.
 802  */
 803
 804 static int
 805 ucf_allocate_pmc(enum pmc_event pe, char *ctrspec,
 806     struct pmc_op_pmcallocate *pmc_config)
 807 {
 808         (void) pe;
 809         (void) ctrspec;
 810
 811         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
 812         pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0;
 813
 814         return (0);
 815 }
 816
 817 #define UCP_KW_CMASK            "cmask"
 818 #define UCP_KW_EDGE             "edge"
 819 #define UCP_KW_INV              "inv"
 820
 821 static int
 822 ucp_allocate_pmc(enum pmc_event pe, char *ctrspec,
 823     struct pmc_op_pmcallocate *pmc_config)
 824 {
 825         char *e, *p, *q;
 826         int count, n;
 827
 828         (void) pe;
 829
 830         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
 831             PMC_CAP_QUALIFIER);
 832         pmc_config->pm_md.pm_ucp.pm_ucp_config = 0;
 833
 834         /* Parse additional modifiers if present */
 835         while ((p = strsep(&ctrspec, ",")) != NULL) {
 836
 837                 n = 0;
 838                 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) {
 839                         q = strchr(p, '=');
 840                         if (*++q == '\0') /* skip '=' */
 841                                 return (-1);
 842                         count = strtol(q, &e, 0);
 843                         if (e == q || *e != '\0')
 844                                 return (-1);
 845                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
 846                         pmc_config->pm_md.pm_ucp.pm_ucp_config |=
 847                             UCP_CMASK(count);
 848                 } else if (KWMATCH(p, UCP_KW_EDGE)) {
 849                         pmc_config->pm_caps |= PMC_CAP_EDGE;
 850                 } else if (KWMATCH(p, UCP_KW_INV)) {
 851                         pmc_config->pm_caps |= PMC_CAP_INVERT;
 852                 } else
 853                         return (-1);
 854
 855                 if (n < 0)      /* Parsing failed. */
 856                         return (-1);
 857         }
 858
 859         return (0);
 860 }
 861
 862 /*
 863  * AMD K8 PMCs.
 864  *
 865  * These are very similar to AMD K7 PMCs, but support more kinds of
 866  * events.
 867  */
 868
 869 static struct pmc_event_alias k8_aliases[] = {
 870         EV_ALIAS("branches",            "k8-fr-retired-taken-branches"),
 871         EV_ALIAS("branch-mispredicts",
 872             "k8-fr-retired-taken-branches-mispredicted"),
 873         EV_ALIAS("cycles",              "tsc"),
 874         EV_ALIAS("dc-misses",           "k8-dc-miss"),
 875         EV_ALIAS("ic-misses",           "k8-ic-miss"),
 876         EV_ALIAS("instructions",        "k8-fr-retired-x86-instructions"),
 877         EV_ALIAS("interrupts",          "k8-fr-taken-hardware-interrupts"),
 878         EV_ALIAS("unhalted-cycles",     "k8-bu-cpu-clk-unhalted"),
 879         EV_ALIAS(NULL, NULL)
 880 };
 881
 882 #define __K8MASK(N,V) PMCMASK(N,(1 << (V)))
 883
 884 /*
 885  * Parsing tables
 886  */
 887
 888 /* fp dispatched fpu ops */
 889 static const struct pmc_masks k8_mask_fdfo[] = {
 890         __K8MASK(add-pipe-excluding-junk-ops,   0),
 891         __K8MASK(multiply-pipe-excluding-junk-ops,      1),
 892         __K8MASK(store-pipe-excluding-junk-ops, 2),
 893         __K8MASK(add-pipe-junk-ops,             3),
 894         __K8MASK(multiply-pipe-junk-ops,        4),
 895         __K8MASK(store-pipe-junk-ops,           5),
 896         NULLMASK
 897 };
 898
 899 /* ls segment register loads */
 900 static const struct pmc_masks k8_mask_lsrl[] = {
 901         __K8MASK(es,    0),
 902         __K8MASK(cs,    1),
 903         __K8MASK(ss,    2),
 904         __K8MASK(ds,    3),
 905         __K8MASK(fs,    4),
 906         __K8MASK(gs,    5),
 907         __K8MASK(hs,    6),
 908         NULLMASK
 909 };
 910
 911 /* ls locked operation */
 912 static const struct pmc_masks k8_mask_llo[] = {
 913         __K8MASK(locked-instructions,   0),
 914         __K8MASK(cycles-in-request,     1),
 915         __K8MASK(cycles-to-complete,    2),
 916         NULLMASK
 917 };
 918
 919 /* dc refill from {l2,system} and dc copyback */
 920 static const struct pmc_masks k8_mask_dc[] = {
 921         __K8MASK(invalid,       0),
 922         __K8MASK(shared,        1),
 923         __K8MASK(exclusive,     2),
 924         __K8MASK(owner,         3),
 925         __K8MASK(modified,      4),
 926         NULLMASK
 927 };
 928
 929 /* dc one bit ecc error */
 930 static const struct pmc_masks k8_mask_dobee[] = {
 931         __K8MASK(scrubber,      0),
 932         __K8MASK(piggyback,     1),
 933         NULLMASK
 934 };
 935
 936 /* dc dispatched prefetch instructions */
 937 static const struct pmc_masks k8_mask_ddpi[] = {
 938         __K8MASK(load,  0),
 939         __K8MASK(store, 1),
 940         __K8MASK(nta,   2),
 941         NULLMASK
 942 };
 943
 944 /* dc dcache accesses by locks */
 945 static const struct pmc_masks k8_mask_dabl[] = {
 946         __K8MASK(accesses,      0),
 947         __K8MASK(misses,        1),
 948         NULLMASK
 949 };
 950
 951 /* bu internal l2 request */
 952 static const struct pmc_masks k8_mask_bilr[] = {
 953         __K8MASK(ic-fill,       0),
 954         __K8MASK(dc-fill,       1),
 955         __K8MASK(tlb-reload,    2),
 956         __K8MASK(tag-snoop,     3),
 957         __K8MASK(cancelled,     4),
 958         NULLMASK
 959 };
 960
 961 /* bu fill request l2 miss */
 962 static const struct pmc_masks k8_mask_bfrlm[] = {
 963         __K8MASK(ic-fill,       0),
 964         __K8MASK(dc-fill,       1),
 965         __K8MASK(tlb-reload,    2),
 966         NULLMASK
 967 };
 968
 969 /* bu fill into l2 */
 970 static const struct pmc_masks k8_mask_bfil[] = {
 971         __K8MASK(dirty-l2-victim,       0),
 972         __K8MASK(victim-from-l2,        1),
 973         NULLMASK
 974 };
 975
 976 /* fr retired fpu instructions */
 977 static const struct pmc_masks k8_mask_frfi[] = {
 978         __K8MASK(x87,                   0),
 979         __K8MASK(mmx-3dnow,             1),
 980         __K8MASK(packed-sse-sse2,       2),
 981         __K8MASK(scalar-sse-sse2,       3),
 982         NULLMASK
 983 };
 984
 985 /* fr retired fastpath double op instructions */
 986 static const struct pmc_masks k8_mask_frfdoi[] = {
 987         __K8MASK(low-op-pos-0,          0),
 988         __K8MASK(low-op-pos-1,          1),
 989         __K8MASK(low-op-pos-2,          2),
 990         NULLMASK
 991 };
 992
 993 /* fr fpu exceptions */
 994 static const struct pmc_masks k8_mask_ffe[] = {
 995         __K8MASK(x87-reclass-microfaults,       0),
 996         __K8MASK(sse-retype-microfaults,        1),
 997         __K8MASK(sse-reclass-microfaults,       2),
 998         __K8MASK(sse-and-x87-microtraps,        3),
 999         NULLMASK
1000 };
1001
1002 /* nb memory controller page access event */
1003 static const struct pmc_masks k8_mask_nmcpae[] = {
1004         __K8MASK(page-hit,      0),
1005         __K8MASK(page-miss,     1),
1006         __K8MASK(page-conflict, 2),
1007         NULLMASK
1008 };
1009
1010 /* nb memory controller turnaround */
1011 static const struct pmc_masks k8_mask_nmct[] = {
1012         __K8MASK(dimm-turnaround,               0),
1013         __K8MASK(read-to-write-turnaround,      1),
1014         __K8MASK(write-to-read-turnaround,      2),
1015         NULLMASK
1016 };
1017
1018 /* nb memory controller bypass saturation */
1019 static const struct pmc_masks k8_mask_nmcbs[] = {
1020         __K8MASK(memory-controller-hi-pri-bypass,       0),
1021         __K8MASK(memory-controller-lo-pri-bypass,       1),
1022         __K8MASK(dram-controller-interface-bypass,      2),
1023         __K8MASK(dram-controller-queue-bypass,          3),
1024         NULLMASK
1025 };
1026
1027 /* nb sized commands */
1028 static const struct pmc_masks k8_mask_nsc[] = {
1029         __K8MASK(nonpostwrszbyte,       0),
1030         __K8MASK(nonpostwrszdword,      1),
1031         __K8MASK(postwrszbyte,          2),
1032         __K8MASK(postwrszdword,         3),
1033         __K8MASK(rdszbyte,              4),
1034         __K8MASK(rdszdword,             5),
1035         __K8MASK(rdmodwr,               6),
1036         NULLMASK
1037 };
1038
1039 /* nb probe result */
1040 static const struct pmc_masks k8_mask_npr[] = {
1041         __K8MASK(probe-miss,            0),
1042         __K8MASK(probe-hit,             1),
1043         __K8MASK(probe-hit-dirty-no-memory-cancel, 2),
1044         __K8MASK(probe-hit-dirty-with-memory-cancel, 3),
1045         NULLMASK
1046 };
1047
1048 /* nb hypertransport bus bandwidth */
1049 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */
1050         __K8MASK(command,       0),
1051         __K8MASK(data,  1),
1052         __K8MASK(buffer-release, 2),
1053         __K8MASK(nop,   3),
1054         NULLMASK
1055 };
1056
1057 #undef  __K8MASK
1058
1059 #define K8_KW_COUNT     "count"
1060 #define K8_KW_EDGE      "edge"
1061 #define K8_KW_INV       "inv"
1062 #define K8_KW_MASK      "mask"
1063 #define K8_KW_OS        "os"
1064 #define K8_KW_USR       "usr"
1065
1066 static int
1067 k8_allocate_pmc(enum pmc_event pe, char *ctrspec,
1068     struct pmc_op_pmcallocate *pmc_config)
1069 {
1070         char            *e, *p, *q;
1071         int             n;
1072         uint32_t        count, evmask;
1073         const struct pmc_masks  *pm, *pmask;
1074
1075         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1076         pmc_config->pm_md.pm_amd.pm_amd_config = 0;
1077
1078         pmask = NULL;
1079         evmask = 0;
1080
1081 #define __K8SETMASK(M) pmask = k8_mask_##M
1082
1083         /* setup parsing tables */
1084         switch (pe) {
1085         case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1086                 __K8SETMASK(fdfo);
1087                 break;
1088         case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD:
1089                 __K8SETMASK(lsrl);
1090                 break;
1091         case PMC_EV_K8_LS_LOCKED_OPERATION:
1092                 __K8SETMASK(llo);
1093                 break;
1094         case PMC_EV_K8_DC_REFILL_FROM_L2:
1095         case PMC_EV_K8_DC_REFILL_FROM_SYSTEM:
1096         case PMC_EV_K8_DC_COPYBACK:
1097                 __K8SETMASK(dc);
1098                 break;
1099         case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR:
1100                 __K8SETMASK(dobee);
1101                 break;
1102         case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS:
1103                 __K8SETMASK(ddpi);
1104                 break;
1105         case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1106                 __K8SETMASK(dabl);
1107                 break;
1108         case PMC_EV_K8_BU_INTERNAL_L2_REQUEST:
1109                 __K8SETMASK(bilr);
1110                 break;
1111         case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS:
1112                 __K8SETMASK(bfrlm);
1113                 break;
1114         case PMC_EV_K8_BU_FILL_INTO_L2:
1115                 __K8SETMASK(bfil);
1116                 break;
1117         case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1118                 __K8SETMASK(frfi);
1119                 break;
1120         case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1121                 __K8SETMASK(frfdoi);
1122                 break;
1123         case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1124                 __K8SETMASK(ffe);
1125                 break;
1126         case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT:
1127                 __K8SETMASK(nmcpae);
1128                 break;
1129         case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND:
1130                 __K8SETMASK(nmct);
1131                 break;
1132         case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION:
1133                 __K8SETMASK(nmcbs);
1134                 break;
1135         case PMC_EV_K8_NB_SIZED_COMMANDS:
1136                 __K8SETMASK(nsc);
1137                 break;
1138         case PMC_EV_K8_NB_PROBE_RESULT:
1139                 __K8SETMASK(npr);
1140                 break;
1141         case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH:
1142         case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH:
1143         case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH:
1144                 __K8SETMASK(nhbb);
1145                 break;
1146
1147         default:
1148                 break;          /* no options defined */
1149         }
1150
1151         while ((p = strsep(&ctrspec, ",")) != NULL) {
1152                 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) {
1153                         q = strchr(p, '=');
1154                         if (*++q == '\0') /* skip '=' */
1155                                 return (-1);
1156
1157                         count = strtol(q, &e, 0);
1158                         if (e == q || *e != '\0')
1159                                 return (-1);
1160
1161                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1162                         pmc_config->pm_md.pm_amd.pm_amd_config |=
1163                             AMD_PMC_TO_COUNTER(count);
1164
1165                 } else if (KWMATCH(p, K8_KW_EDGE)) {
1166                         pmc_config->pm_caps |= PMC_CAP_EDGE;
1167                 } else if (KWMATCH(p, K8_KW_INV)) {
1168                         pmc_config->pm_caps |= PMC_CAP_INVERT;
1169                 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) {
1170                         if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1171                                 return (-1);
1172                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1173                 } else if (KWMATCH(p, K8_KW_OS)) {
1174                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1175                 } else if (KWMATCH(p, K8_KW_USR)) {
1176                         pmc_config->pm_caps |= PMC_CAP_USER;
1177                 } else
1178                         return (-1);
1179         }
1180
1181         /* other post processing */
1182         switch (pe) {
1183         case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1184         case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED:
1185         case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS:
1186         case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1187         case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1188         case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1189                 /* XXX only available in rev B and later */
1190                 break;
1191         case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1192                 /* XXX only available in rev C and later */
1193                 break;
1194         case PMC_EV_K8_LS_LOCKED_OPERATION:
1195                 /* XXX CPU Rev A,B evmask is to be zero */
1196                 if (evmask & (evmask - 1)) /* > 1 bit set */
1197                         return (-1);
1198                 if (evmask == 0) {
1199                         evmask = 0x01; /* Rev C and later: #instrs */
1200                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1201                 }
1202                 break;
1203         default:
1204                 if (evmask == 0 && pmask != NULL) {
1205                         for (pm = pmask; pm->pm_name; pm++)
1206                                 evmask |= pm->pm_value;
1207                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1208                 }
1209         }
1210
1211         if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
1212                 pmc_config->pm_md.pm_amd.pm_amd_config =
1213                     AMD_PMC_TO_UNITMASK(evmask);
1214
1215         return (0);
1216 }
1217
1218 #endif
1219
1220 #if defined(__amd64__) || defined(__i386__)
1221
1222 /*
1223  * Intel P4 PMCs
1224  */
1225
1226 static struct pmc_event_alias p4_aliases[] = {
1227         EV_ALIAS("branches",            "p4-branch-retired,mask=mmtp+mmtm"),
1228         EV_ALIAS("branch-mispredicts",  "p4-mispred-branch-retired"),
1229         EV_ALIAS("cycles",              "tsc"),
1230         EV_ALIAS("instructions",
1231             "p4-instr-retired,mask=nbogusntag+nbogustag"),
1232         EV_ALIAS("unhalted-cycles",     "p4-global-power-events"),
1233         EV_ALIAS(NULL, NULL)
1234 };
1235
1236 #define P4_KW_ACTIVE    "active"
1237 #define P4_KW_ACTIVE_ANY "any"
1238 #define P4_KW_ACTIVE_BOTH "both"
1239 #define P4_KW_ACTIVE_NONE "none"
1240 #define P4_KW_ACTIVE_SINGLE "single"
1241 #define P4_KW_BUSREQTYPE "busreqtype"
1242 #define P4_KW_CASCADE   "cascade"
1243 #define P4_KW_EDGE      "edge"
1244 #define P4_KW_INV       "complement"
1245 #define P4_KW_OS        "os"
1246 #define P4_KW_MASK      "mask"
1247 #define P4_KW_PRECISE   "precise"
1248 #define P4_KW_TAG       "tag"
1249 #define P4_KW_THRESHOLD "threshold"
1250 #define P4_KW_USR       "usr"
1251
1252 #define __P4MASK(N,V) PMCMASK(N, (1 << (V)))
1253
1254 static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */
1255         __P4MASK(dd, 0),
1256         __P4MASK(db, 1),
1257         __P4MASK(di, 2),
1258         __P4MASK(bd, 3),
1259         __P4MASK(bb, 4),
1260         __P4MASK(bi, 5),
1261         __P4MASK(id, 6),
1262         __P4MASK(ib, 7),
1263         NULLMASK
1264 };
1265
1266 static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */
1267         __P4MASK(tcmiss, 0),
1268         NULLMASK,
1269 };
1270
1271 static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */
1272         __P4MASK(hit, 0),
1273         __P4MASK(miss, 1),
1274         __P4MASK(hit-uc, 2),
1275         NULLMASK
1276 };
1277
1278 static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */
1279         __P4MASK(st-rb-full, 2),
1280         __P4MASK(64k-conf, 3),
1281         NULLMASK
1282 };
1283
1284 static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */
1285         __P4MASK(lsc, 0),
1286         __P4MASK(ssc, 1),
1287         NULLMASK
1288 };
1289
1290 static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */
1291         __P4MASK(split-ld, 1),
1292         NULLMASK
1293 };
1294
1295 static const struct pmc_masks p4_mask_spr[] = { /* store port replay */
1296         __P4MASK(split-st, 1),
1297         NULLMASK
1298 };
1299
1300 static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */
1301         __P4MASK(no-sta, 1),
1302         __P4MASK(no-std, 3),
1303         __P4MASK(partial-data, 4),
1304         __P4MASK(unalgn-addr, 5),
1305         NULLMASK
1306 };
1307
1308 static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */
1309         __P4MASK(dtmiss, 0),
1310         __P4MASK(itmiss, 1),
1311         NULLMASK
1312 };
1313
1314 static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */
1315         __P4MASK(rd-2ndl-hits, 0),
1316         __P4MASK(rd-2ndl-hite, 1),
1317         __P4MASK(rd-2ndl-hitm, 2),
1318         __P4MASK(rd-3rdl-hits, 3),
1319         __P4MASK(rd-3rdl-hite, 4),
1320         __P4MASK(rd-3rdl-hitm, 5),
1321         __P4MASK(rd-2ndl-miss, 8),
1322         __P4MASK(rd-3rdl-miss, 9),
1323         __P4MASK(wr-2ndl-miss, 10),
1324         NULLMASK
1325 };
1326
1327 static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */
1328         __P4MASK(all-read, 5),
1329         __P4MASK(all-write, 6),
1330         __P4MASK(mem-uc, 7),
1331         __P4MASK(mem-wc, 8),
1332         __P4MASK(mem-wt, 9),
1333         __P4MASK(mem-wp, 10),
1334         __P4MASK(mem-wb, 11),
1335         __P4MASK(own, 13),
1336         __P4MASK(other, 14),
1337         __P4MASK(prefetch, 15),
1338         NULLMASK
1339 };
1340
1341 static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */
1342         __P4MASK(all-read, 5),
1343         __P4MASK(all-write, 6),
1344         __P4MASK(mem-uc, 7),
1345         __P4MASK(mem-wc, 8),
1346         __P4MASK(mem-wt, 9),
1347         __P4MASK(mem-wp, 10),
1348         __P4MASK(mem-wb, 11),
1349         __P4MASK(own, 13),
1350         __P4MASK(other, 14),
1351         __P4MASK(prefetch, 15),
1352         NULLMASK
1353 };
1354
1355 static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */
1356         __P4MASK(drdy-drv, 0),
1357         __P4MASK(drdy-own, 1),
1358         __P4MASK(drdy-other, 2),
1359         __P4MASK(dbsy-drv, 3),
1360         __P4MASK(dbsy-own, 4),
1361         __P4MASK(dbsy-other, 5),
1362         NULLMASK
1363 };
1364
1365 static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */
1366         __P4MASK(req-type0, 0),
1367         __P4MASK(req-type1, 1),
1368         __P4MASK(req-len0, 2),
1369         __P4MASK(req-len1, 3),
1370         __P4MASK(req-io-type, 5),
1371         __P4MASK(req-lock-type, 6),
1372         __P4MASK(req-cache-type, 7),
1373         __P4MASK(req-split-type, 8),
1374         __P4MASK(req-dem-type, 9),
1375         __P4MASK(req-ord-type, 10),
1376         __P4MASK(mem-type0, 11),
1377         __P4MASK(mem-type1, 12),
1378         __P4MASK(mem-type2, 13),
1379         NULLMASK
1380 };
1381
1382 static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */
1383         __P4MASK(all, 15),
1384         NULLMASK
1385 };
1386
1387 static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */
1388         __P4MASK(all, 15),
1389         NULLMASK
1390 };
1391
1392 static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */
1393         __P4MASK(all, 15),
1394         NULLMASK
1395 };
1396
1397 static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */
1398         __P4MASK(all, 15),
1399         NULLMASK
1400 };
1401
1402 static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */
1403         __P4MASK(all, 15),
1404         NULLMASK
1405 };
1406
1407 static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */
1408         __P4MASK(all, 15),
1409         NULLMASK
1410 };
1411
1412 static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */
1413         __P4MASK(all, 15),
1414         NULLMASK
1415 };
1416
1417 static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */
1418         __P4MASK(all, 15),
1419         NULLMASK
1420 };
1421
1422 static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */
1423         __P4MASK(allp0, 3),
1424         __P4MASK(allp2, 4),
1425         NULLMASK
1426 };
1427
1428 static const struct pmc_masks p4_mask_gpe[] = { /* global power events */
1429         __P4MASK(running, 0),
1430         NULLMASK
1431 };
1432
1433 static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */
1434         __P4MASK(cisc, 0),
1435         NULLMASK
1436 };
1437
1438 static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */
1439         __P4MASK(from-tc-build, 0),
1440         __P4MASK(from-tc-deliver, 1),
1441         __P4MASK(from-rom, 2),
1442         NULLMASK
1443 };
1444
1445 static const struct pmc_masks p4_mask_rmbt[] = {
1446         /* retired mispred branch type */
1447         __P4MASK(conditional, 1),
1448         __P4MASK(call, 2),
1449         __P4MASK(return, 3),
1450         __P4MASK(indirect, 4),
1451         NULLMASK
1452 };
1453
1454 static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */
1455         __P4MASK(conditional, 1),
1456         __P4MASK(call, 2),
1457         __P4MASK(retired, 3),
1458         __P4MASK(indirect, 4),
1459         NULLMASK
1460 };
1461
1462 static const struct pmc_masks p4_mask_rs[] = { /* resource stall */
1463         __P4MASK(sbfull, 5),
1464         NULLMASK
1465 };
1466
1467 static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */
1468         __P4MASK(wcb-evicts, 0),
1469         __P4MASK(wcb-full-evict, 1),
1470         NULLMASK
1471 };
1472
1473 static const struct pmc_masks p4_mask_fee[] = { /* front end event */
1474         __P4MASK(nbogus, 0),
1475         __P4MASK(bogus, 1),
1476         NULLMASK
1477 };
1478
1479 static const struct pmc_masks p4_mask_ee[] = { /* execution event */
1480         __P4MASK(nbogus0, 0),
1481         __P4MASK(nbogus1, 1),
1482         __P4MASK(nbogus2, 2),
1483         __P4MASK(nbogus3, 3),
1484         __P4MASK(bogus0, 4),
1485         __P4MASK(bogus1, 5),
1486         __P4MASK(bogus2, 6),
1487         __P4MASK(bogus3, 7),
1488         NULLMASK
1489 };
1490
1491 static const struct pmc_masks p4_mask_re[] = { /* replay event */
1492         __P4MASK(nbogus, 0),
1493         __P4MASK(bogus, 1),
1494         NULLMASK
1495 };
1496
1497 static const struct pmc_masks p4_mask_insret[] = { /* instr retired */
1498         __P4MASK(nbogusntag, 0),
1499         __P4MASK(nbogustag, 1),
1500         __P4MASK(bogusntag, 2),
1501         __P4MASK(bogustag, 3),
1502         NULLMASK
1503 };
1504
1505 static const struct pmc_masks p4_mask_ur[] = { /* uops retired */
1506         __P4MASK(nbogus, 0),
1507         __P4MASK(bogus, 1),
1508         NULLMASK
1509 };
1510
1511 static const struct pmc_masks p4_mask_ut[] = { /* uop type */
1512         __P4MASK(tagloads, 1),
1513         __P4MASK(tagstores, 2),
1514         NULLMASK
1515 };
1516
1517 static const struct pmc_masks p4_mask_br[] = { /* branch retired */
1518         __P4MASK(mmnp, 0),
1519         __P4MASK(mmnm, 1),
1520         __P4MASK(mmtp, 2),
1521         __P4MASK(mmtm, 3),
1522         NULLMASK
1523 };
1524
1525 static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */
1526         __P4MASK(nbogus, 0),
1527         NULLMASK
1528 };
1529
1530 static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */
1531         __P4MASK(fpsu, 0),
1532         __P4MASK(fpso, 1),
1533         __P4MASK(poao, 2),
1534         __P4MASK(poau, 3),
1535         __P4MASK(prea, 4),
1536         NULLMASK
1537 };
1538
1539 static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */
1540         __P4MASK(clear, 0),
1541         __P4MASK(moclear, 2),
1542         __P4MASK(smclear, 3),
1543         NULLMASK
1544 };
1545
1546 /* P4 event parser */
1547 static int
1548 p4_allocate_pmc(enum pmc_event pe, char *ctrspec,
1549     struct pmc_op_pmcallocate *pmc_config)
1550 {
1551
1552         char    *e, *p, *q;
1553         int     count, has_tag, has_busreqtype, n;
1554         uint32_t evmask, cccractivemask;
1555         const struct pmc_masks *pm, *pmask;
1556
1557         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1558         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig =
1559             pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0;
1560
1561         pmask   = NULL;
1562         evmask  = 0;
1563         cccractivemask = 0x3;
1564         has_tag = has_busreqtype = 0;
1565
1566 #define __P4SETMASK(M) do {                             \
1567         pmask = p4_mask_##M;                            \
1568 } while (0)
1569
1570         switch (pe) {
1571         case PMC_EV_P4_TC_DELIVER_MODE:
1572                 __P4SETMASK(tcdm);
1573                 break;
1574         case PMC_EV_P4_BPU_FETCH_REQUEST:
1575                 __P4SETMASK(bfr);
1576                 break;
1577         case PMC_EV_P4_ITLB_REFERENCE:
1578                 __P4SETMASK(ir);
1579                 break;
1580         case PMC_EV_P4_MEMORY_CANCEL:
1581                 __P4SETMASK(memcan);
1582                 break;
1583         case PMC_EV_P4_MEMORY_COMPLETE:
1584                 __P4SETMASK(memcomp);
1585                 break;
1586         case PMC_EV_P4_LOAD_PORT_REPLAY:
1587                 __P4SETMASK(lpr);
1588                 break;
1589         case PMC_EV_P4_STORE_PORT_REPLAY:
1590                 __P4SETMASK(spr);
1591                 break;
1592         case PMC_EV_P4_MOB_LOAD_REPLAY:
1593                 __P4SETMASK(mlr);
1594                 break;
1595         case PMC_EV_P4_PAGE_WALK_TYPE:
1596                 __P4SETMASK(pwt);
1597                 break;
1598         case PMC_EV_P4_BSQ_CACHE_REFERENCE:
1599                 __P4SETMASK(bcr);
1600                 break;
1601         case PMC_EV_P4_IOQ_ALLOCATION:
1602                 __P4SETMASK(ia);
1603                 has_busreqtype = 1;
1604                 break;
1605         case PMC_EV_P4_IOQ_ACTIVE_ENTRIES:
1606                 __P4SETMASK(iae);
1607                 has_busreqtype = 1;
1608                 break;
1609         case PMC_EV_P4_FSB_DATA_ACTIVITY:
1610                 __P4SETMASK(fda);
1611                 break;
1612         case PMC_EV_P4_BSQ_ALLOCATION:
1613                 __P4SETMASK(ba);
1614                 break;
1615         case PMC_EV_P4_SSE_INPUT_ASSIST:
1616                 __P4SETMASK(sia);
1617                 break;
1618         case PMC_EV_P4_PACKED_SP_UOP:
1619                 __P4SETMASK(psu);
1620                 break;
1621         case PMC_EV_P4_PACKED_DP_UOP:
1622                 __P4SETMASK(pdu);
1623                 break;
1624         case PMC_EV_P4_SCALAR_SP_UOP:
1625                 __P4SETMASK(ssu);
1626                 break;
1627         case PMC_EV_P4_SCALAR_DP_UOP:
1628                 __P4SETMASK(sdu);
1629                 break;
1630         case PMC_EV_P4_64BIT_MMX_UOP:
1631                 __P4SETMASK(64bmu);
1632                 break;
1633         case PMC_EV_P4_128BIT_MMX_UOP:
1634                 __P4SETMASK(128bmu);
1635                 break;
1636         case PMC_EV_P4_X87_FP_UOP:
1637                 __P4SETMASK(xfu);
1638                 break;
1639         case PMC_EV_P4_X87_SIMD_MOVES_UOP:
1640                 __P4SETMASK(xsmu);
1641                 break;
1642         case PMC_EV_P4_GLOBAL_POWER_EVENTS:
1643                 __P4SETMASK(gpe);
1644                 break;
1645         case PMC_EV_P4_TC_MS_XFER:
1646                 __P4SETMASK(tmx);
1647                 break;
1648         case PMC_EV_P4_UOP_QUEUE_WRITES:
1649                 __P4SETMASK(uqw);
1650                 break;
1651         case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE:
1652                 __P4SETMASK(rmbt);
1653                 break;
1654         case PMC_EV_P4_RETIRED_BRANCH_TYPE:
1655                 __P4SETMASK(rbt);
1656                 break;
1657         case PMC_EV_P4_RESOURCE_STALL:
1658                 __P4SETMASK(rs);
1659                 break;
1660         case PMC_EV_P4_WC_BUFFER:
1661                 __P4SETMASK(wb);
1662                 break;
1663         case PMC_EV_P4_BSQ_ACTIVE_ENTRIES:
1664         case PMC_EV_P4_B2B_CYCLES:
1665         case PMC_EV_P4_BNR:
1666         case PMC_EV_P4_SNOOP:
1667         case PMC_EV_P4_RESPONSE:
1668                 break;
1669         case PMC_EV_P4_FRONT_END_EVENT:
1670                 __P4SETMASK(fee);
1671                 break;
1672         case PMC_EV_P4_EXECUTION_EVENT:
1673                 __P4SETMASK(ee);
1674                 break;
1675         case PMC_EV_P4_REPLAY_EVENT:
1676                 __P4SETMASK(re);
1677                 break;
1678         case PMC_EV_P4_INSTR_RETIRED:
1679                 __P4SETMASK(insret);
1680                 break;
1681         case PMC_EV_P4_UOPS_RETIRED:
1682                 __P4SETMASK(ur);
1683                 break;
1684         case PMC_EV_P4_UOP_TYPE:
1685                 __P4SETMASK(ut);
1686                 break;
1687         case PMC_EV_P4_BRANCH_RETIRED:
1688                 __P4SETMASK(br);
1689                 break;
1690         case PMC_EV_P4_MISPRED_BRANCH_RETIRED:
1691                 __P4SETMASK(mbr);
1692                 break;
1693         case PMC_EV_P4_X87_ASSIST:
1694                 __P4SETMASK(xa);
1695                 break;
1696         case PMC_EV_P4_MACHINE_CLEAR:
1697                 __P4SETMASK(machclr);
1698                 break;
1699         default:
1700                 return (-1);
1701         }
1702
1703         /* process additional flags */
1704         while ((p = strsep(&ctrspec, ",")) != NULL) {
1705                 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) {
1706                         q = strchr(p, '=');
1707                         if (*++q == '\0') /* skip '=' */
1708                                 return (-1);
1709
1710                         if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0)
1711                                 cccractivemask = 0x0;
1712                         else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0)
1713                                 cccractivemask = 0x1;
1714                         else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0)
1715                                 cccractivemask = 0x2;
1716                         else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0)
1717                                 cccractivemask = 0x3;
1718                         else
1719                                 return (-1);
1720
1721                 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) {
1722                         if (has_busreqtype == 0)
1723                                 return (-1);
1724
1725                         q = strchr(p, '=');
1726                         if (*++q == '\0') /* skip '=' */
1727                                 return (-1);
1728
1729                         count = strtol(q, &e, 0);
1730                         if (e == q || *e != '\0')
1731                                 return (-1);
1732                         evmask = (evmask & ~0x1F) | (count & 0x1F);
1733                 } else if (KWMATCH(p, P4_KW_CASCADE))
1734                         pmc_config->pm_caps |= PMC_CAP_CASCADE;
1735                 else if (KWMATCH(p, P4_KW_EDGE))
1736                         pmc_config->pm_caps |= PMC_CAP_EDGE;
1737                 else if (KWMATCH(p, P4_KW_INV))
1738                         pmc_config->pm_caps |= PMC_CAP_INVERT;
1739                 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) {
1740                         if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1741                                 return (-1);
1742                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1743                 } else if (KWMATCH(p, P4_KW_OS))
1744                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1745                 else if (KWMATCH(p, P4_KW_PRECISE))
1746                         pmc_config->pm_caps |= PMC_CAP_PRECISE;
1747                 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) {
1748                         if (has_tag == 0)
1749                                 return (-1);
1750
1751                         q = strchr(p, '=');
1752                         if (*++q == '\0') /* skip '=' */
1753                                 return (-1);
1754
1755                         count = strtol(q, &e, 0);
1756                         if (e == q || *e != '\0')
1757                                 return (-1);
1758
1759                         pmc_config->pm_caps |= PMC_CAP_TAGGING;
1760                         pmc_config->pm_md.pm_p4.pm_p4_escrconfig |=
1761                             P4_ESCR_TO_TAG_VALUE(count);
1762                 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) {
1763                         q = strchr(p, '=');
1764                         if (*++q == '\0') /* skip '=' */
1765                                 return (-1);
1766
1767                         count = strtol(q, &e, 0);
1768                         if (e == q || *e != '\0')
1769                                 return (-1);
1770
1771                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1772                         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &=
1773                             ~P4_CCCR_THRESHOLD_MASK;
1774                         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |=
1775                             P4_CCCR_TO_THRESHOLD(count);
1776                 } else if (KWMATCH(p, P4_KW_USR))
1777                         pmc_config->pm_caps |= PMC_CAP_USER;
1778                 else
1779                         return (-1);
1780         }
1781
1782         /* other post processing */
1783         if (pe == PMC_EV_P4_IOQ_ALLOCATION ||
1784             pe == PMC_EV_P4_FSB_DATA_ACTIVITY ||
1785             pe == PMC_EV_P4_BSQ_ALLOCATION)
1786                 pmc_config->pm_caps |= PMC_CAP_EDGE;
1787
1788         /* fill in thread activity mask */
1789         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |=
1790             P4_CCCR_TO_ACTIVE_THREAD(cccractivemask);
1791
1792         if (evmask)
1793                 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1794
1795         switch (pe) {
1796         case PMC_EV_P4_FSB_DATA_ACTIVITY:
1797                 if ((evmask & 0x06) == 0x06 ||
1798                     (evmask & 0x18) == 0x18)
1799                         return (-1); /* can't have own+other bits together */
1800                 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */
1801                         evmask = 0x1D;
1802                 break;
1803         case PMC_EV_P4_MACHINE_CLEAR:
1804                 /* only one bit is allowed to be set */
1805                 if ((evmask & (evmask - 1)) != 0)
1806                         return (-1);
1807                 if (evmask == 0) {
1808                         evmask = 0x1;   /* 'CLEAR' */
1809                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1810                 }
1811                 break;
1812         default:
1813                 if (evmask == 0 && pmask) {
1814                         for (pm = pmask; pm->pm_name; pm++)
1815                                 evmask |= pm->pm_value;
1816                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1817                 }
1818         }
1819
1820         pmc_config->pm_md.pm_p4.pm_p4_escrconfig =
1821             P4_ESCR_TO_EVENT_MASK(evmask);
1822
1823         return (0);
1824 }
1825
1826 #endif
1827
1828 #if defined(__i386__)
1829
1830 /*
1831  * Pentium style PMCs
1832  */
1833
1834 static struct pmc_event_alias p5_aliases[] = {
1835         EV_ALIAS("branches",            "p5-taken-branches"),
1836         EV_ALIAS("cycles",              "tsc"),
1837         EV_ALIAS("dc-misses",           "p5-data-read-miss-or-write-miss"),
1838         EV_ALIAS("ic-misses",           "p5-code-cache-miss"),
1839         EV_ALIAS("instructions",        "p5-instructions-executed"),
1840         EV_ALIAS("interrupts",          "p5-hardware-interrupts"),
1841         EV_ALIAS("unhalted-cycles",
1842             "p5-number-of-cycles-not-in-halt-state"),
1843         EV_ALIAS(NULL, NULL)
1844 };
1845
1846 static int
1847 p5_allocate_pmc(enum pmc_event pe, char *ctrspec,
1848     struct pmc_op_pmcallocate *pmc_config)
1849 {
1850         return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */
1851 }
1852
1853 /*
1854  * Pentium Pro style PMCs.  These PMCs are found in Pentium II, Pentium III,
1855  * and Pentium M CPUs.
1856  */
1857
1858 static struct pmc_event_alias p6_aliases[] = {
1859         EV_ALIAS("branches",            "p6-br-inst-retired"),
1860         EV_ALIAS("branch-mispredicts",  "p6-br-miss-pred-retired"),
1861         EV_ALIAS("cycles",              "tsc"),
1862         EV_ALIAS("dc-misses",           "p6-dcu-lines-in"),
1863         EV_ALIAS("ic-misses",           "p6-ifu-fetch-miss"),
1864         EV_ALIAS("instructions",        "p6-inst-retired"),
1865         EV_ALIAS("interrupts",          "p6-hw-int-rx"),
1866         EV_ALIAS("unhalted-cycles",     "p6-cpu-clk-unhalted"),
1867         EV_ALIAS(NULL, NULL)
1868 };
1869
1870 #define P6_KW_CMASK     "cmask"
1871 #define P6_KW_EDGE      "edge"
1872 #define P6_KW_INV       "inv"
1873 #define P6_KW_OS        "os"
1874 #define P6_KW_UMASK     "umask"
1875 #define P6_KW_USR       "usr"
1876
1877 static struct pmc_masks p6_mask_mesi[] = {
1878         PMCMASK(m,      0x01),
1879         PMCMASK(e,      0x02),
1880         PMCMASK(s,      0x04),
1881         PMCMASK(i,      0x08),
1882         NULLMASK
1883 };
1884
1885 static struct pmc_masks p6_mask_mesihw[] = {
1886         PMCMASK(m,      0x01),
1887         PMCMASK(e,      0x02),
1888         PMCMASK(s,      0x04),
1889         PMCMASK(i,      0x08),
1890         PMCMASK(nonhw,  0x00),
1891         PMCMASK(hw,     0x10),
1892         PMCMASK(both,   0x30),
1893         NULLMASK
1894 };
1895
1896 static struct pmc_masks p6_mask_hw[] = {
1897         PMCMASK(nonhw,  0x00),
1898         PMCMASK(hw,     0x10),
1899         PMCMASK(both,   0x30),
1900         NULLMASK
1901 };
1902
1903 static struct pmc_masks p6_mask_any[] = {
1904         PMCMASK(self,   0x00),
1905         PMCMASK(any,    0x20),
1906         NULLMASK
1907 };
1908
1909 static struct pmc_masks p6_mask_ekp[] = {
1910         PMCMASK(nta,    0x00),
1911         PMCMASK(t1,     0x01),
1912         PMCMASK(t2,     0x02),
1913         PMCMASK(wos,    0x03),
1914         NULLMASK
1915 };
1916
1917 static struct pmc_masks p6_mask_pps[] = {
1918         PMCMASK(packed-and-scalar, 0x00),
1919         PMCMASK(scalar, 0x01),
1920         NULLMASK
1921 };
1922
1923 static struct pmc_masks p6_mask_mite[] = {
1924         PMCMASK(packed-multiply,         0x01),
1925         PMCMASK(packed-shift,           0x02),
1926         PMCMASK(pack,                   0x04),
1927         PMCMASK(unpack,                 0x08),
1928         PMCMASK(packed-logical,         0x10),
1929         PMCMASK(packed-arithmetic,      0x20),
1930         NULLMASK
1931 };
1932
1933 static struct pmc_masks p6_mask_fmt[] = {
1934         PMCMASK(mmxtofp,        0x00),
1935         PMCMASK(fptommx,        0x01),
1936         NULLMASK
1937 };
1938
1939 static struct pmc_masks p6_mask_sr[] = {
1940         PMCMASK(es,     0x01),
1941         PMCMASK(ds,     0x02),
1942         PMCMASK(fs,     0x04),
1943         PMCMASK(gs,     0x08),
1944         NULLMASK
1945 };
1946
1947 static struct pmc_masks p6_mask_eet[] = {
1948         PMCMASK(all,    0x00),
1949         PMCMASK(freq,   0x02),
1950         NULLMASK
1951 };
1952
1953 static struct pmc_masks p6_mask_efur[] = {
1954         PMCMASK(all,    0x00),
1955         PMCMASK(loadop, 0x01),
1956         PMCMASK(stdsta, 0x02),
1957         NULLMASK
1958 };
1959
1960 static struct pmc_masks p6_mask_essir[] = {
1961         PMCMASK(sse-packed-single,      0x00),
1962         PMCMASK(sse-packed-single-scalar-single, 0x01),
1963         PMCMASK(sse2-packed-double,     0x02),
1964         PMCMASK(sse2-scalar-double,     0x03),
1965         NULLMASK
1966 };
1967
1968 static struct pmc_masks p6_mask_esscir[] = {
1969         PMCMASK(sse-packed-single,      0x00),
1970         PMCMASK(sse-scalar-single,      0x01),
1971         PMCMASK(sse2-packed-double,     0x02),
1972         PMCMASK(sse2-scalar-double,     0x03),
1973         NULLMASK
1974 };
1975
1976 /* P6 event parser */
1977 static int
1978 p6_allocate_pmc(enum pmc_event pe, char *ctrspec,
1979     struct pmc_op_pmcallocate *pmc_config)
1980 {
1981         char *e, *p, *q;
1982         uint32_t evmask;
1983         int count, n;
1984         const struct pmc_masks *pm, *pmask;
1985
1986         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1987         pmc_config->pm_md.pm_ppro.pm_ppro_config = 0;
1988
1989         evmask = 0;
1990
1991 #define P6MASKSET(M)    pmask = p6_mask_ ## M
1992
1993         switch(pe) {
1994         case PMC_EV_P6_L2_IFETCH:       P6MASKSET(mesi); break;
1995         case PMC_EV_P6_L2_LD:           P6MASKSET(mesi); break;
1996         case PMC_EV_P6_L2_ST:           P6MASKSET(mesi); break;
1997         case PMC_EV_P6_L2_RQSTS:        P6MASKSET(mesi); break;
1998         case PMC_EV_P6_BUS_DRDY_CLOCKS:
1999         case PMC_EV_P6_BUS_LOCK_CLOCKS:
2000         case PMC_EV_P6_BUS_TRAN_BRD:
2001         case PMC_EV_P6_BUS_TRAN_RFO:
2002         case PMC_EV_P6_BUS_TRANS_WB:
2003         case PMC_EV_P6_BUS_TRAN_IFETCH:
2004         case PMC_EV_P6_BUS_TRAN_INVAL:
2005         case PMC_EV_P6_BUS_TRAN_PWR:
2006         case PMC_EV_P6_BUS_TRANS_P:
2007         case PMC_EV_P6_BUS_TRANS_IO:
2008         case PMC_EV_P6_BUS_TRAN_DEF:
2009         case PMC_EV_P6_BUS_TRAN_BURST:
2010         case PMC_EV_P6_BUS_TRAN_ANY:
2011         case PMC_EV_P6_BUS_TRAN_MEM:
2012                 P6MASKSET(any); break;
2013         case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED:
2014         case PMC_EV_P6_EMON_KNI_PREF_MISS:
2015                 P6MASKSET(ekp); break;
2016         case PMC_EV_P6_EMON_KNI_INST_RETIRED:
2017         case PMC_EV_P6_EMON_KNI_COMP_INST_RET:
2018                 P6MASKSET(pps); break;
2019         case PMC_EV_P6_MMX_INSTR_TYPE_EXEC:
2020                 P6MASKSET(mite); break;
2021         case PMC_EV_P6_FP_MMX_TRANS:
2022                 P6MASKSET(fmt); break;
2023         case PMC_EV_P6_SEG_RENAME_STALLS:
2024         case PMC_EV_P6_SEG_REG_RENAMES:
2025                 P6MASKSET(sr);  break;
2026         case PMC_EV_P6_EMON_EST_TRANS:
2027                 P6MASKSET(eet); break;
2028         case PMC_EV_P6_EMON_FUSED_UOPS_RET:
2029                 P6MASKSET(efur); break;
2030         case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED:
2031                 P6MASKSET(essir); break;
2032         case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED:
2033                 P6MASKSET(esscir); break;
2034         default:
2035                 pmask = NULL;
2036                 break;
2037         }
2038
2039         /* Pentium M PMCs have a few events with different semantics */
2040         if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) {
2041                 if (pe == PMC_EV_P6_L2_LD ||
2042                     pe == PMC_EV_P6_L2_LINES_IN ||
2043                     pe == PMC_EV_P6_L2_LINES_OUT)
2044                         P6MASKSET(mesihw);
2045                 else if (pe == PMC_EV_P6_L2_M_LINES_OUTM)
2046                         P6MASKSET(hw);
2047         }
2048
2049         /* Parse additional modifiers if present */
2050         while ((p = strsep(&ctrspec, ",")) != NULL) {
2051                 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) {
2052                         q = strchr(p, '=');
2053                         if (*++q == '\0') /* skip '=' */
2054                                 return (-1);
2055                         count = strtol(q, &e, 0);
2056                         if (e == q || *e != '\0')
2057                                 return (-1);
2058                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
2059                         pmc_config->pm_md.pm_ppro.pm_ppro_config |=
2060                             P6_EVSEL_TO_CMASK(count);
2061                 } else if (KWMATCH(p, P6_KW_EDGE)) {
2062                         pmc_config->pm_caps |= PMC_CAP_EDGE;
2063                 } else if (KWMATCH(p, P6_KW_INV)) {
2064                         pmc_config->pm_caps |= PMC_CAP_INVERT;
2065                 } else if (KWMATCH(p, P6_KW_OS)) {
2066                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2067                 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) {
2068                         evmask = 0;
2069                         if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
2070                                 return (-1);
2071                         if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS ||
2072                              pe == PMC_EV_P6_BUS_LOCK_CLOCKS ||
2073                              pe == PMC_EV_P6_BUS_TRAN_BRD ||
2074                              pe == PMC_EV_P6_BUS_TRAN_RFO ||
2075                              pe == PMC_EV_P6_BUS_TRAN_IFETCH ||
2076                              pe == PMC_EV_P6_BUS_TRAN_INVAL ||
2077                              pe == PMC_EV_P6_BUS_TRAN_PWR ||
2078                              pe == PMC_EV_P6_BUS_TRAN_DEF ||
2079                              pe == PMC_EV_P6_BUS_TRAN_BURST ||
2080                              pe == PMC_EV_P6_BUS_TRAN_ANY ||
2081                              pe == PMC_EV_P6_BUS_TRAN_MEM ||
2082                              pe == PMC_EV_P6_BUS_TRANS_IO ||
2083                              pe == PMC_EV_P6_BUS_TRANS_P ||
2084                              pe == PMC_EV_P6_BUS_TRANS_WB ||
2085                              pe == PMC_EV_P6_EMON_EST_TRANS ||
2086                              pe == PMC_EV_P6_EMON_FUSED_UOPS_RET ||
2087                              pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET ||
2088                              pe == PMC_EV_P6_EMON_KNI_INST_RETIRED ||
2089                              pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED ||
2090                              pe == PMC_EV_P6_EMON_KNI_PREF_MISS ||
2091                              pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED ||
2092                              pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED ||
2093                              pe == PMC_EV_P6_FP_MMX_TRANS)
2094                             && (n > 1)) /* Only one mask keyword is allowed. */
2095                                 return (-1);
2096                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
2097                 } else if (KWMATCH(p, P6_KW_USR)) {
2098                         pmc_config->pm_caps |= PMC_CAP_USER;
2099                 } else
2100                         return (-1);
2101         }
2102
2103         /* post processing */
2104         switch (pe) {
2105
2106                 /*
2107                  * The following events default to an evmask of 0
2108                  */
2109
2110                 /* default => 'self' */
2111         case PMC_EV_P6_BUS_DRDY_CLOCKS:
2112         case PMC_EV_P6_BUS_LOCK_CLOCKS:
2113         case PMC_EV_P6_BUS_TRAN_BRD:
2114         case PMC_EV_P6_BUS_TRAN_RFO:
2115         case PMC_EV_P6_BUS_TRANS_WB:
2116         case PMC_EV_P6_BUS_TRAN_IFETCH:
2117         case PMC_EV_P6_BUS_TRAN_INVAL:
2118         case PMC_EV_P6_BUS_TRAN_PWR:
2119         case PMC_EV_P6_BUS_TRANS_P:
2120         case PMC_EV_P6_BUS_TRANS_IO:
2121         case PMC_EV_P6_BUS_TRAN_DEF:
2122         case PMC_EV_P6_BUS_TRAN_BURST:
2123         case PMC_EV_P6_BUS_TRAN_ANY:
2124         case PMC_EV_P6_BUS_TRAN_MEM:
2125
2126                 /* default => 'nta' */
2127         case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED:
2128         case PMC_EV_P6_EMON_KNI_PREF_MISS:
2129
2130                 /* default => 'packed and scalar' */
2131         case PMC_EV_P6_EMON_KNI_INST_RETIRED:
2132         case PMC_EV_P6_EMON_KNI_COMP_INST_RET:
2133
2134                 /* default => 'mmx to fp transitions' */
2135         case PMC_EV_P6_FP_MMX_TRANS:
2136
2137                 /* default => 'SSE Packed Single' */
2138         case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED:
2139         case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED:
2140
2141                 /* default => 'all fused micro-ops' */
2142         case PMC_EV_P6_EMON_FUSED_UOPS_RET:
2143
2144                 /* default => 'all transitions' */
2145         case PMC_EV_P6_EMON_EST_TRANS:
2146                 break;
2147
2148         case PMC_EV_P6_MMX_UOPS_EXEC:
2149                 evmask = 0x0F;          /* only value allowed */
2150                 break;
2151
2152         default:
2153                 /*
2154                  * For all other events, set the default event mask
2155                  * to a logical OR of all the allowed event mask bits.
2156                  */
2157                 if (evmask == 0 && pmask) {
2158                         for (pm = pmask; pm->pm_name; pm++)
2159                                 evmask |= pm->pm_value;
2160                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
2161                 }
2162
2163                 break;
2164         }
2165
2166         if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
2167                 pmc_config->pm_md.pm_ppro.pm_ppro_config |=
2168                     P6_EVSEL_TO_UMASK(evmask);
2169
2170         return (0);
2171 }
2172
2173 #endif
2174
2175 #if     defined(__i386__) || defined(__amd64__)
2176 static int
2177 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec,
2178     struct pmc_op_pmcallocate *pmc_config)
2179 {
2180         if (pe != PMC_EV_TSC_TSC)
2181                 return (-1);
2182
2183         /* TSC events must be unqualified. */
2184         if (ctrspec && *ctrspec != '\0')
2185                 return (-1);
2186
2187         pmc_config->pm_md.pm_amd.pm_amd_config = 0;
2188         pmc_config->pm_caps |= PMC_CAP_READ;
2189
2190         return (0);
2191 }
2192 #endif
2193
2194 static struct pmc_event_alias generic_aliases[] = {
2195         EV_ALIAS("instructions",                "SOFT-CLOCK.HARD"),
2196         EV_ALIAS(NULL, NULL)
2197 };
2198
2199 static int
2200 soft_allocate_pmc(enum pmc_event pe, char *ctrspec,
2201     struct pmc_op_pmcallocate *pmc_config)
2202 {
2203         (void)ctrspec;
2204         (void)pmc_config;
2205
2206         if (pe < PMC_EV_SOFT_FIRST || pe > PMC_EV_SOFT_LAST)
2207                 return (-1);
2208
2209         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2210         return (0);
2211 }
2212
2213 #if     defined(__XSCALE__)
2214
2215 static struct pmc_event_alias xscale_aliases[] = {
2216         EV_ALIAS("branches",            "BRANCH_RETIRED"),
2217         EV_ALIAS("branch-mispredicts",  "BRANCH_MISPRED"),
2218         EV_ALIAS("dc-misses",           "DC_MISS"),
2219         EV_ALIAS("ic-misses",           "IC_MISS"),
2220         EV_ALIAS("instructions",        "INSTR_RETIRED"),
2221         EV_ALIAS(NULL, NULL)
2222 };
2223 static int
2224 xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2225     struct pmc_op_pmcallocate *pmc_config __unused)
2226 {
2227         switch (pe) {
2228         default:
2229                 break;
2230         }
2231
2232         return (0);
2233 }
2234 #endif
2235
2236 #if defined(__mips__)
2237
2238 static struct pmc_event_alias mips24k_aliases[] = {
2239         EV_ALIAS("instructions",        "INSTR_EXECUTED"),
2240         EV_ALIAS("branches",            "BRANCH_COMPLETED"),
2241         EV_ALIAS("branch-mispredicts",  "BRANCH_MISPRED"),
2242         EV_ALIAS(NULL, NULL)
2243 };
2244
2245 #define MIPS24K_KW_OS           "os"
2246 #define MIPS24K_KW_USR          "usr"
2247 #define MIPS24K_KW_ANYTHREAD    "anythread"
2248
2249 static int
2250 mips24k_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2251                   struct pmc_op_pmcallocate *pmc_config __unused)
2252 {
2253         char *p;
2254
2255         (void) pe;
2256
2257         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2258
2259         while ((p = strsep(&ctrspec, ",")) != NULL) {
2260                 if (KWMATCH(p, MIPS24K_KW_OS))
2261                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2262                 else if (KWMATCH(p, MIPS24K_KW_USR))
2263                         pmc_config->pm_caps |= PMC_CAP_USER;
2264                 else if (KWMATCH(p, MIPS24K_KW_ANYTHREAD))
2265                         pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
2266                 else
2267                         return (-1);
2268         }
2269
2270         return (0);
2271 }
2272 #endif /* __mips__ */
2273
2274 #if defined(__powerpc__)
2275
2276 static struct pmc_event_alias ppc7450_aliases[] = {
2277         EV_ALIAS("instructions",        "INSTR_COMPLETED"),
2278         EV_ALIAS("branches",            "BRANCHES_COMPLETED"),
2279         EV_ALIAS("branch-mispredicts",  "MISPREDICTED_BRANCHES"),
2280         EV_ALIAS(NULL, NULL)
2281 };
2282
2283 #define PPC7450_KW_OS           "os"
2284 #define PPC7450_KW_USR          "usr"
2285 #define PPC7450_KW_ANYTHREAD    "anythread"
2286
2287 static int
2288 ppc7450_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2289                   struct pmc_op_pmcallocate *pmc_config __unused)
2290 {
2291         char *p;
2292
2293         (void) pe;
2294
2295         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2296
2297         while ((p = strsep(&ctrspec, ",")) != NULL) {
2298                 if (KWMATCH(p, PPC7450_KW_OS))
2299                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2300                 else if (KWMATCH(p, PPC7450_KW_USR))
2301                         pmc_config->pm_caps |= PMC_CAP_USER;
2302                 else if (KWMATCH(p, PPC7450_KW_ANYTHREAD))
2303                         pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
2304                 else
2305                         return (-1);
2306         }
2307
2308         return (0);
2309 }
2310 #endif /* __powerpc__ */
2311
2312
2313 /*
2314  * Match an event name `name' with its canonical form.
2315  *
2316  * Matches are case insensitive and spaces, periods, underscores and
2317  * hyphen characters are considered to match each other.
2318  *
2319  * Returns 1 for a match, 0 otherwise.
2320  */
2321
2322 static int
2323 pmc_match_event_name(const char *name, const char *canonicalname)
2324 {
2325         int cc, nc;
2326         const unsigned char *c, *n;
2327
2328         c = (const unsigned char *) canonicalname;
2329         n = (const unsigned char *) name;
2330
2331         for (; (nc = *n) && (cc = *c); n++, c++) {
2332
2333                 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') &&
2334                     (cc == ' ' || cc == '_' || cc == '-' || cc == '.'))
2335                         continue;
2336
2337                 if (toupper(nc) == toupper(cc))
2338                         continue;
2339
2340
2341                 return (0);
2342         }
2343
2344         if (*n == '\0' && *c == '\0')
2345                 return (1);
2346
2347         return (0);
2348 }
2349
2350 /*
2351  * Match an event name against all the event named supported by a
2352  * PMC class.
2353  *
2354  * Returns an event descriptor pointer on match or NULL otherwise.
2355  */
2356 static const struct pmc_event_descr *
2357 pmc_match_event_class(const char *name,
2358     const struct pmc_class_descr *pcd)
2359 {
2360         size_t n;
2361         const struct pmc_event_descr *ev;
2362
2363         ev = pcd->pm_evc_event_table;
2364         for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++)
2365                 if (pmc_match_event_name(name, ev->pm_ev_name))
2366                         return (ev);
2367
2368         return (NULL);
2369 }
2370
2371 static int
2372 pmc_mdep_is_compatible_class(enum pmc_class pc)
2373 {
2374         size_t n;
2375
2376         for (n = 0; n < pmc_mdep_class_list_size; n++)
2377                 if (pmc_mdep_class_list[n] == pc)
2378                         return (1);
2379         return (0);
2380 }
2381
2382 /*
2383  * API entry points
2384  */
2385
2386 int
2387 pmc_allocate(const char *ctrspec, enum pmc_mode mode,
2388     uint32_t flags, int cpu, pmc_id_t *pmcid)
2389 {
2390         size_t n;
2391         int retval;
2392         char *r, *spec_copy;
2393         const char *ctrname;
2394         const struct pmc_event_descr *ev;
2395         const struct pmc_event_alias *alias;
2396         struct pmc_op_pmcallocate pmc_config;
2397         const struct pmc_class_descr *pcd;
2398
2399         spec_copy = NULL;
2400         retval    = -1;
2401
2402         if (mode != PMC_MODE_SS && mode != PMC_MODE_TS &&
2403             mode != PMC_MODE_SC && mode != PMC_MODE_TC) {
2404                 errno = EINVAL;
2405                 goto out;
2406         }
2407
2408         /* replace an event alias with the canonical event specifier */
2409         if (pmc_mdep_event_aliases)
2410                 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++)
2411                         if (!strcasecmp(ctrspec, alias->pm_alias)) {
2412                                 spec_copy = strdup(alias->pm_spec);
2413                                 break;
2414                         }
2415
2416         if (spec_copy == NULL)
2417                 spec_copy = strdup(ctrspec);
2418
2419         r = spec_copy;
2420         ctrname = strsep(&r, ",");
2421
2422         /*
2423          * If a explicit class prefix was given by the user, restrict the
2424          * search for the event to the specified PMC class.
2425          */
2426         ev = NULL;
2427         for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) {
2428                 pcd = pmc_class_table[n];
2429                 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) &&
2430                     strncasecmp(ctrname, pcd->pm_evc_name,
2431                                 pcd->pm_evc_name_size) == 0) {
2432                         if ((ev = pmc_match_event_class(ctrname +
2433                             pcd->pm_evc_name_size, pcd)) == NULL) {
2434                                 errno = EINVAL;
2435                                 goto out;
2436                         }
2437                         break;
2438                 }
2439         }
2440
2441         /*
2442          * Otherwise, search for this event in all compatible PMC
2443          * classes.
2444          */
2445         for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) {
2446                 pcd = pmc_class_table[n];
2447                 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class))
2448                         ev = pmc_match_event_class(ctrname, pcd);
2449         }
2450
2451         if (ev == NULL) {
2452                 errno = EINVAL;
2453                 goto out;
2454         }
2455
2456         bzero(&pmc_config, sizeof(pmc_config));
2457         pmc_config.pm_ev    = ev->pm_ev_code;
2458         pmc_config.pm_class = pcd->pm_evc_class;
2459         pmc_config.pm_cpu   = cpu;
2460         pmc_config.pm_mode  = mode;
2461         pmc_config.pm_flags = flags;
2462
2463         if (PMC_IS_SAMPLING_MODE(mode))
2464                 pmc_config.pm_caps |= PMC_CAP_INTERRUPT;
2465
2466         if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) {
2467                 errno = EINVAL;
2468                 goto out;
2469         }
2470
2471         if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0)
2472                 goto out;
2473
2474         *pmcid = pmc_config.pm_pmcid;
2475
2476         retval = 0;
2477
2478  out:
2479         if (spec_copy)
2480                 free(spec_copy);
2481
2482         return (retval);
2483 }
2484
2485 int
2486 pmc_attach(pmc_id_t pmc, pid_t pid)
2487 {
2488         struct pmc_op_pmcattach pmc_attach_args;
2489
2490         pmc_attach_args.pm_pmc = pmc;
2491         pmc_attach_args.pm_pid = pid;
2492
2493         return (PMC_CALL(PMCATTACH, &pmc_attach_args));
2494 }
2495
2496 int
2497 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps)
2498 {
2499         unsigned int i;
2500         enum pmc_class cl;
2501
2502         cl = PMC_ID_TO_CLASS(pmcid);
2503         for (i = 0; i < cpu_info.pm_nclass; i++)
2504                 if (cpu_info.pm_classes[i].pm_class == cl) {
2505                         *caps = cpu_info.pm_classes[i].pm_caps;
2506                         return (0);
2507                 }
2508         errno = EINVAL;
2509         return (-1);
2510 }
2511
2512 int
2513 pmc_configure_logfile(int fd)
2514 {
2515         struct pmc_op_configurelog cla;
2516
2517         cla.pm_logfd = fd;
2518         if (PMC_CALL(CONFIGURELOG, &cla) < 0)
2519                 return (-1);
2520         return (0);
2521 }
2522
2523 int
2524 pmc_cpuinfo(const struct pmc_cpuinfo **pci)
2525 {
2526         if (pmc_syscall == -1) {
2527                 errno = ENXIO;
2528                 return (-1);
2529         }
2530
2531         *pci = &cpu_info;
2532         return (0);
2533 }
2534
2535 int
2536 pmc_detach(pmc_id_t pmc, pid_t pid)
2537 {
2538         struct pmc_op_pmcattach pmc_detach_args;
2539
2540         pmc_detach_args.pm_pmc = pmc;
2541         pmc_detach_args.pm_pid = pid;
2542         return (PMC_CALL(PMCDETACH, &pmc_detach_args));
2543 }
2544
2545 int
2546 pmc_disable(int cpu, int pmc)
2547 {
2548         struct pmc_op_pmcadmin ssa;
2549
2550         ssa.pm_cpu = cpu;
2551         ssa.pm_pmc = pmc;
2552         ssa.pm_state = PMC_STATE_DISABLED;
2553         return (PMC_CALL(PMCADMIN, &ssa));
2554 }
2555
2556 int
2557 pmc_enable(int cpu, int pmc)
2558 {
2559         struct pmc_op_pmcadmin ssa;
2560
2561         ssa.pm_cpu = cpu;
2562         ssa.pm_pmc = pmc;
2563         ssa.pm_state = PMC_STATE_FREE;
2564         return (PMC_CALL(PMCADMIN, &ssa));
2565 }
2566
2567 /*
2568  * Return a list of events known to a given PMC class.  'cl' is the
2569  * PMC class identifier, 'eventnames' is the returned list of 'const
2570  * char *' pointers pointing to the names of the events. 'nevents' is
2571  * the number of event name pointers returned.
2572  *
2573  * The space for 'eventnames' is allocated using malloc(3).  The caller
2574  * is responsible for freeing this space when done.
2575  */
2576 int
2577 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
2578     int *nevents)
2579 {
2580         int count;
2581         const char **names;
2582         const struct pmc_event_descr *ev;
2583
2584         switch (cl)
2585         {
2586         case PMC_CLASS_IAF:
2587                 ev = iaf_event_table;
2588                 count = PMC_EVENT_TABLE_SIZE(iaf);
2589                 break;
2590         case PMC_CLASS_IAP:
2591                 /*
2592                  * Return the most appropriate set of event name
2593                  * spellings for the current CPU.
2594                  */
2595                 switch (cpu_info.pm_cputype) {
2596                 default:
2597                 case PMC_CPU_INTEL_ATOM:
2598                         ev = atom_event_table;
2599                         count = PMC_EVENT_TABLE_SIZE(atom);
2600                         break;
2601                 case PMC_CPU_INTEL_CORE:
2602                         ev = core_event_table;
2603                         count = PMC_EVENT_TABLE_SIZE(core);
2604                         break;
2605                 case PMC_CPU_INTEL_CORE2:
2606                 case PMC_CPU_INTEL_CORE2EXTREME:
2607                         ev = core2_event_table;
2608                         count = PMC_EVENT_TABLE_SIZE(core2);
2609                         break;
2610                 case PMC_CPU_INTEL_COREI7:
2611                         ev = corei7_event_table;
2612                         count = PMC_EVENT_TABLE_SIZE(corei7);
2613                         break;
2614                 case PMC_CPU_INTEL_SANDYBRIDGE:
2615                         ev = sandybridge_event_table;
2616                         count = PMC_EVENT_TABLE_SIZE(sandybridge);
2617                         break;
2618                 case PMC_CPU_INTEL_WESTMERE:
2619                         ev = westmere_event_table;
2620                         count = PMC_EVENT_TABLE_SIZE(westmere);
2621                         break;
2622                 }
2623                 break;
2624         case PMC_CLASS_UCF:
2625                 ev = ucf_event_table;
2626                 count = PMC_EVENT_TABLE_SIZE(ucf);
2627                 break;
2628         case PMC_CLASS_UCP:
2629                 /*
2630                  * Return the most appropriate set of event name
2631                  * spellings for the current CPU.
2632                  */
2633                 switch (cpu_info.pm_cputype) {
2634                 default:
2635                 case PMC_CPU_INTEL_COREI7:
2636                         ev = corei7uc_event_table;
2637                         count = PMC_EVENT_TABLE_SIZE(corei7uc);
2638                         break;
2639                 case PMC_CPU_INTEL_SANDYBRIDGE:
2640                         ev = sandybridgeuc_event_table;
2641                         count = PMC_EVENT_TABLE_SIZE(sandybridgeuc);
2642                         break;
2643                 case PMC_CPU_INTEL_WESTMERE:
2644                         ev = westmereuc_event_table;
2645                         count = PMC_EVENT_TABLE_SIZE(westmereuc);
2646                         break;
2647                 }
2648                 break;
2649         case PMC_CLASS_TSC:
2650                 ev = tsc_event_table;
2651                 count = PMC_EVENT_TABLE_SIZE(tsc);
2652                 break;
2653         case PMC_CLASS_K7:
2654                 ev = k7_event_table;
2655                 count = PMC_EVENT_TABLE_SIZE(k7);
2656                 break;
2657         case PMC_CLASS_K8:
2658                 ev = k8_event_table;
2659                 count = PMC_EVENT_TABLE_SIZE(k8);
2660                 break;
2661         case PMC_CLASS_P4:
2662                 ev = p4_event_table;
2663                 count = PMC_EVENT_TABLE_SIZE(p4);
2664                 break;
2665         case PMC_CLASS_P5:
2666                 ev = p5_event_table;
2667                 count = PMC_EVENT_TABLE_SIZE(p5);
2668                 break;
2669         case PMC_CLASS_P6:
2670                 ev = p6_event_table;
2671                 count = PMC_EVENT_TABLE_SIZE(p6);
2672                 break;
2673         case PMC_CLASS_XSCALE:
2674                 ev = xscale_event_table;
2675                 count = PMC_EVENT_TABLE_SIZE(xscale);
2676                 break;
2677         case PMC_CLASS_MIPS24K:
2678                 ev = mips24k_event_table;
2679                 count = PMC_EVENT_TABLE_SIZE(mips24k);
2680                 break;
2681         case PMC_CLASS_PPC7450:
2682                 ev = ppc7450_event_table;
2683                 count = PMC_EVENT_TABLE_SIZE(ppc7450);
2684                 break;
2685         case PMC_CLASS_SOFT:
2686                 ev = soft_event_table;
2687                 count = soft_event_info.pm_nevent;
2688                 break;
2689         default:
2690                 errno = EINVAL;
2691                 return (-1);
2692         }
2693
2694         if ((names = malloc(count * sizeof(const char *))) == NULL)
2695                 return (-1);
2696
2697         *eventnames = names;
2698         *nevents = count;
2699
2700         for (;count--; ev++, names++)
2701                 *names = ev->pm_ev_name;
2702
2703         return (0);
2704 }
2705
2706 int
2707 pmc_flush_logfile(void)
2708 {
2709         return (PMC_CALL(FLUSHLOG,0));
2710 }
2711
2712 int
2713 pmc_close_logfile(void)
2714 {
2715         return (PMC_CALL(CLOSELOG,0));
2716 }
2717
2718 int
2719 pmc_get_driver_stats(struct pmc_driverstats *ds)
2720 {
2721         struct pmc_op_getdriverstats gms;
2722
2723         if (PMC_CALL(GETDRIVERSTATS, &gms) < 0)
2724                 return (-1);
2725
2726         /* copy out fields in the current userland<->library interface */
2727         ds->pm_intr_ignored    = gms.pm_intr_ignored;
2728         ds->pm_intr_processed  = gms.pm_intr_processed;
2729         ds->pm_intr_bufferfull = gms.pm_intr_bufferfull;
2730         ds->pm_syscalls        = gms.pm_syscalls;
2731         ds->pm_syscall_errors  = gms.pm_syscall_errors;
2732         ds->pm_buffer_requests = gms.pm_buffer_requests;
2733         ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed;
2734         ds->pm_log_sweeps      = gms.pm_log_sweeps;
2735         return (0);
2736 }
2737
2738 int
2739 pmc_get_msr(pmc_id_t pmc, uint32_t *msr)
2740 {
2741         struct pmc_op_getmsr gm;
2742
2743         gm.pm_pmcid = pmc;
2744         if (PMC_CALL(PMCGETMSR, &gm) < 0)
2745                 return (-1);
2746         *msr = gm.pm_msr;
2747         return (0);
2748 }
2749
2750 int
2751 pmc_init(void)
2752 {
2753         int error, pmc_mod_id;
2754         unsigned int n;
2755         uint32_t abi_version;
2756         struct module_stat pmc_modstat;
2757         struct pmc_op_getcpuinfo op_cpu_info;
2758 #if defined(__amd64__) || defined(__i386__)
2759         int cpu_has_iaf_counters;
2760         unsigned int t;
2761 #endif
2762
2763         if (pmc_syscall != -1) /* already inited */
2764                 return (0);
2765
2766         /* retrieve the system call number from the KLD */
2767         if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0)
2768                 return (-1);
2769
2770         pmc_modstat.version = sizeof(struct module_stat);
2771         if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0)
2772                 return (-1);
2773
2774         pmc_syscall = pmc_modstat.data.intval;
2775
2776         /* check the kernel module's ABI against our compiled-in version */
2777         abi_version = PMC_VERSION;
2778         if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0)
2779                 return (pmc_syscall = -1);
2780
2781         /* ignore patch & minor numbers for the comparision */
2782         if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) {
2783                 errno  = EPROGMISMATCH;
2784                 return (pmc_syscall = -1);
2785         }
2786
2787         if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0)
2788                 return (pmc_syscall = -1);
2789
2790         cpu_info.pm_cputype = op_cpu_info.pm_cputype;
2791         cpu_info.pm_ncpu    = op_cpu_info.pm_ncpu;
2792         cpu_info.pm_npmc    = op_cpu_info.pm_npmc;
2793         cpu_info.pm_nclass  = op_cpu_info.pm_nclass;
2794         for (n = 0; n < cpu_info.pm_nclass; n++)
2795                 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n];
2796
2797         pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE *
2798             sizeof(struct pmc_class_descr *));
2799
2800         if (pmc_class_table == NULL)
2801                 return (-1);
2802
2803         for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++)
2804                 pmc_class_table[n] = NULL;
2805
2806         /*
2807          * Get soft events list.
2808          */
2809         soft_event_info.pm_class = PMC_CLASS_SOFT;
2810         if (PMC_CALL(GETDYNEVENTINFO, &soft_event_info) < 0)
2811                 return (pmc_syscall = -1);
2812
2813         /* Map soft events to static list. */
2814         for (n = 0; n < soft_event_info.pm_nevent; n++) {
2815                 soft_event_table[n].pm_ev_name =
2816                     soft_event_info.pm_events[n].pm_ev_name;
2817                 soft_event_table[n].pm_ev_code =
2818                     soft_event_info.pm_events[n].pm_ev_code;
2819         }
2820         soft_class_table_descr.pm_evc_event_table_size = \
2821             soft_event_info.pm_nevent;
2822         soft_class_table_descr.pm_evc_event_table = \
2823             soft_event_table;
2824
2825         /*
2826          * Fill in the class table.
2827          */
2828         n = 0;
2829
2830         /* Fill soft events information. */
2831         pmc_class_table[n++] = &soft_class_table_descr;
2832 #if defined(__amd64__) || defined(__i386__)
2833         if (cpu_info.pm_cputype != PMC_CPU_GENERIC)
2834                 pmc_class_table[n++] = &tsc_class_table_descr;
2835
2836         /*
2837          * Check if this CPU has fixed function counters.
2838          */
2839         cpu_has_iaf_counters = 0;
2840         for (t = 0; t < cpu_info.pm_nclass; t++)
2841                 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF &&
2842                     cpu_info.pm_classes[t].pm_num > 0)
2843                         cpu_has_iaf_counters = 1;
2844 #endif
2845
2846 #define PMC_MDEP_INIT(C) do {                                   \
2847                 pmc_mdep_event_aliases    = C##_aliases;        \
2848                 pmc_mdep_class_list  = C##_pmc_classes;         \
2849                 pmc_mdep_class_list_size =                      \
2850                     PMC_TABLE_SIZE(C##_pmc_classes);            \
2851         } while (0)
2852
2853 #define PMC_MDEP_INIT_INTEL_V2(C) do {                                  \
2854                 PMC_MDEP_INIT(C);                                       \
2855                 pmc_class_table[n++] = &iaf_class_table_descr;          \
2856                 if (!cpu_has_iaf_counters)                              \
2857                         pmc_mdep_event_aliases =                        \
2858                                 C##_aliases_without_iaf;                \
2859                 pmc_class_table[n] = &C##_class_table_descr;            \
2860         } while (0)
2861
2862         /* Configure the event name parser. */
2863         switch (cpu_info.pm_cputype) {
2864 #if defined(__i386__)
2865         case PMC_CPU_AMD_K7:
2866                 PMC_MDEP_INIT(k7);
2867                 pmc_class_table[n] = &k7_class_table_descr;
2868                 break;
2869         case PMC_CPU_INTEL_P5:
2870                 PMC_MDEP_INIT(p5);
2871                 pmc_class_table[n]  = &p5_class_table_descr;
2872                 break;
2873         case PMC_CPU_INTEL_P6:          /* P6 ... Pentium M CPUs have */
2874         case PMC_CPU_INTEL_PII:         /* similar PMCs. */
2875         case PMC_CPU_INTEL_PIII:
2876         case PMC_CPU_INTEL_PM:
2877                 PMC_MDEP_INIT(p6);
2878                 pmc_class_table[n] = &p6_class_table_descr;
2879                 break;
2880 #endif
2881 #if defined(__amd64__) || defined(__i386__)
2882         case PMC_CPU_AMD_K8:
2883                 PMC_MDEP_INIT(k8);
2884                 pmc_class_table[n] = &k8_class_table_descr;
2885                 break;
2886         case PMC_CPU_INTEL_ATOM:
2887                 PMC_MDEP_INIT_INTEL_V2(atom);
2888                 break;
2889         case PMC_CPU_INTEL_CORE:
2890                 PMC_MDEP_INIT(core);
2891                 pmc_class_table[n] = &core_class_table_descr;
2892                 break;
2893         case PMC_CPU_INTEL_CORE2:
2894         case PMC_CPU_INTEL_CORE2EXTREME:
2895                 PMC_MDEP_INIT_INTEL_V2(core2);
2896                 break;
2897         case PMC_CPU_INTEL_COREI7:
2898                 pmc_class_table[n++] = &ucf_class_table_descr;
2899                 pmc_class_table[n++] = &corei7uc_class_table_descr;
2900                 PMC_MDEP_INIT_INTEL_V2(corei7);
2901                 break;
2902         case PMC_CPU_INTEL_SANDYBRIDGE:
2903                 pmc_class_table[n++] = &ucf_class_table_descr;
2904                 pmc_class_table[n++] = &sandybridgeuc_class_table_descr;
2905                 PMC_MDEP_INIT_INTEL_V2(sandybridge);
2906                 break;
2907         case PMC_CPU_INTEL_WESTMERE:
2908                 pmc_class_table[n++] = &ucf_class_table_descr;
2909                 pmc_class_table[n++] = &westmereuc_class_table_descr;
2910                 PMC_MDEP_INIT_INTEL_V2(westmere);
2911                 break;
2912         case PMC_CPU_INTEL_PIV:
2913                 PMC_MDEP_INIT(p4);
2914                 pmc_class_table[n] = &p4_class_table_descr;
2915                 break;
2916 #endif
2917         case PMC_CPU_GENERIC:
2918                 PMC_MDEP_INIT(generic);
2919                 break;
2920 #if defined(__XSCALE__)
2921         case PMC_CPU_INTEL_XSCALE:
2922                 PMC_MDEP_INIT(xscale);
2923                 pmc_class_table[n] = &xscale_class_table_descr;
2924                 break;
2925 #endif
2926 #if defined(__mips__)
2927         case PMC_CPU_MIPS_24K:
2928                 PMC_MDEP_INIT(mips24k);
2929                 pmc_class_table[n] = &mips24k_class_table_descr;
2930                 break;
2931 #endif /* __mips__ */
2932 #if defined(__powerpc__)
2933         case PMC_CPU_PPC_7450:
2934                 PMC_MDEP_INIT(ppc7450);
2935                 pmc_class_table[n] = &ppc7450_class_table_descr;
2936                 break;
2937 #endif
2938         default:
2939                 /*
2940                  * Some kind of CPU this version of the library knows nothing
2941                  * about.  This shouldn't happen since the abi version check
2942                  * should have caught this.
2943                  */
2944                 errno = ENXIO;
2945                 return (pmc_syscall = -1);
2946         }
2947
2948         return (0);
2949 }
2950
2951 const char *
2952 pmc_name_of_capability(enum pmc_caps cap)
2953 {
2954         int i;
2955
2956         /*
2957          * 'cap' should have a single bit set and should be in
2958          * range.
2959          */
2960         if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST ||
2961             cap > PMC_CAP_LAST) {
2962                 errno = EINVAL;
2963                 return (NULL);
2964         }
2965
2966         i = ffs(cap);
2967         return (pmc_capability_names[i - 1]);
2968 }
2969
2970 const char *
2971 pmc_name_of_class(enum pmc_class pc)
2972 {
2973         if ((int) pc >= PMC_CLASS_FIRST &&
2974             pc <= PMC_CLASS_LAST)
2975                 return (pmc_class_names[pc]);
2976
2977         errno = EINVAL;
2978         return (NULL);
2979 }
2980
2981 const char *
2982 pmc_name_of_cputype(enum pmc_cputype cp)
2983 {
2984         size_t n;
2985
2986         for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++)
2987                 if (cp == pmc_cputype_names[n].pm_cputype)
2988                         return (pmc_cputype_names[n].pm_name);
2989
2990         errno = EINVAL;
2991         return (NULL);
2992 }
2993
2994 const char *
2995 pmc_name_of_disposition(enum pmc_disp pd)
2996 {
2997         if ((int) pd >= PMC_DISP_FIRST &&
2998             pd <= PMC_DISP_LAST)
2999                 return (pmc_disposition_names[pd]);
3000
3001         errno = EINVAL;
3002         return (NULL);
3003 }
3004
3005 const char *
3006 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
3007 {
3008         const struct pmc_event_descr *ev, *evfence;
3009
3010         ev = evfence = NULL;
3011         if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) {
3012                 ev = iaf_event_table;
3013                 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf);
3014         } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) {
3015                 switch (cpu) {
3016                 case PMC_CPU_INTEL_ATOM:
3017                         ev = atom_event_table;
3018                         evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom);
3019                         break;
3020                 case PMC_CPU_INTEL_CORE:
3021                         ev = core_event_table;
3022                         evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core);
3023                         break;
3024                 case PMC_CPU_INTEL_CORE2:
3025                 case PMC_CPU_INTEL_CORE2EXTREME:
3026                         ev = core2_event_table;
3027                         evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2);
3028                         break;
3029                 case PMC_CPU_INTEL_COREI7:
3030                         ev = corei7_event_table;
3031                         evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7);
3032                         break;
3033                 case PMC_CPU_INTEL_SANDYBRIDGE:
3034                         ev = sandybridge_event_table;
3035                         evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge);
3036                         break;
3037                 case PMC_CPU_INTEL_WESTMERE:
3038                         ev = westmere_event_table;
3039                         evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere);
3040                         break;
3041                 default:        /* Unknown CPU type. */
3042                         break;
3043                 }
3044         } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) {
3045                 ev = ucf_event_table;
3046                 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf);
3047         } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) {
3048                 switch (cpu) {
3049                 case PMC_CPU_INTEL_COREI7:
3050                         ev = corei7uc_event_table;
3051                         evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc);
3052                         break;
3053                 case PMC_CPU_INTEL_SANDYBRIDGE:
3054                         ev = sandybridgeuc_event_table;
3055                         evfence = sandybridgeuc_event_table + PMC_EVENT_TABLE_SIZE(sandybridgeuc);
3056                         break;
3057                 case PMC_CPU_INTEL_WESTMERE:
3058                         ev = westmereuc_event_table;
3059                         evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc);
3060                         break;
3061                 default:        /* Unknown CPU type. */
3062                         break;
3063                 }
3064         } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) {
3065                 ev = k7_event_table;
3066                 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7);
3067         } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
3068                 ev = k8_event_table;
3069                 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
3070         } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) {
3071                 ev = p4_event_table;
3072                 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4);
3073         } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) {
3074                 ev = p5_event_table;
3075                 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5);
3076         } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) {
3077                 ev = p6_event_table;
3078                 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6);
3079         } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) {
3080                 ev = xscale_event_table;
3081                 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale);
3082         } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) {
3083                 ev = mips24k_event_table;
3084                 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k);
3085         } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) {
3086                 ev = ppc7450_event_table;
3087                 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450);
3088         } else if (pe == PMC_EV_TSC_TSC) {
3089                 ev = tsc_event_table;
3090                 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc);
3091         } else if (pe >= PMC_EV_SOFT_FIRST && pe <= PMC_EV_SOFT_LAST) {
3092                 ev = soft_event_table;
3093                 evfence = soft_event_table + soft_event_info.pm_nevent;
3094         }
3095
3096         for (; ev != evfence; ev++)
3097                 if (pe == ev->pm_ev_code)
3098                         return (ev->pm_ev_name);
3099
3100         return (NULL);
3101 }
3102
3103 const char *
3104 pmc_name_of_event(enum pmc_event pe)
3105 {
3106         const char *n;
3107
3108         if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL)
3109                 return (n);
3110
3111         errno = EINVAL;
3112         return (NULL);
3113 }
3114
3115 const char *
3116 pmc_name_of_mode(enum pmc_mode pm)
3117 {
3118         if ((int) pm >= PMC_MODE_FIRST &&
3119             pm <= PMC_MODE_LAST)
3120                 return (pmc_mode_names[pm]);
3121
3122         errno = EINVAL;
3123         return (NULL);
3124 }
3125
3126 const char *
3127 pmc_name_of_state(enum pmc_state ps)
3128 {
3129         if ((int) ps >= PMC_STATE_FIRST &&
3130             ps <= PMC_STATE_LAST)
3131                 return (pmc_state_names[ps]);
3132
3133         errno = EINVAL;
3134         return (NULL);
3135 }
3136
3137 int
3138 pmc_ncpu(void)
3139 {
3140         if (pmc_syscall == -1) {
3141                 errno = ENXIO;
3142                 return (-1);
3143         }
3144
3145         return (cpu_info.pm_ncpu);
3146 }
3147
3148 int
3149 pmc_npmc(int cpu)
3150 {
3151         if (pmc_syscall == -1) {
3152                 errno = ENXIO;
3153                 return (-1);
3154         }
3155
3156         if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) {
3157                 errno = EINVAL;
3158                 return (-1);
3159         }
3160
3161         return (cpu_info.pm_npmc);
3162 }
3163
3164 int
3165 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci)
3166 {
3167         int nbytes, npmc;
3168         struct pmc_op_getpmcinfo *pmci;
3169
3170         if ((npmc = pmc_npmc(cpu)) < 0)
3171                 return (-1);
3172
3173         nbytes = sizeof(struct pmc_op_getpmcinfo) +
3174             npmc * sizeof(struct pmc_info);
3175
3176         if ((pmci = calloc(1, nbytes)) == NULL)
3177                 return (-1);
3178
3179         pmci->pm_cpu  = cpu;
3180
3181         if (PMC_CALL(GETPMCINFO, pmci) < 0) {
3182                 free(pmci);
3183                 return (-1);
3184         }
3185
3186         /* kernel<->library, library<->userland interfaces are identical */
3187         *ppmci = (struct pmc_pmcinfo *) pmci;
3188         return (0);
3189 }
3190
3191 int
3192 pmc_read(pmc_id_t pmc, pmc_value_t *value)
3193 {
3194         struct pmc_op_pmcrw pmc_read_op;
3195
3196         pmc_read_op.pm_pmcid = pmc;
3197         pmc_read_op.pm_flags = PMC_F_OLDVALUE;
3198         pmc_read_op.pm_value = -1;
3199
3200         if (PMC_CALL(PMCRW, &pmc_read_op) < 0)
3201                 return (-1);
3202
3203         *value = pmc_read_op.pm_value;
3204         return (0);
3205 }
3206
3207 int
3208 pmc_release(pmc_id_t pmc)
3209 {
3210         struct pmc_op_simple    pmc_release_args;
3211
3212         pmc_release_args.pm_pmcid = pmc;
3213         return (PMC_CALL(PMCRELEASE, &pmc_release_args));
3214 }
3215
3216 int
3217 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep)
3218 {
3219         struct pmc_op_pmcrw pmc_rw_op;
3220
3221         pmc_rw_op.pm_pmcid = pmc;
3222         pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE;
3223         pmc_rw_op.pm_value = newvalue;
3224
3225         if (PMC_CALL(PMCRW, &pmc_rw_op) < 0)
3226                 return (-1);
3227
3228         *oldvaluep = pmc_rw_op.pm_value;
3229         return (0);
3230 }
3231
3232 int
3233 pmc_set(pmc_id_t pmc, pmc_value_t value)
3234 {
3235         struct pmc_op_pmcsetcount sc;
3236
3237         sc.pm_pmcid = pmc;
3238         sc.pm_count = value;
3239
3240         if (PMC_CALL(PMCSETCOUNT, &sc) < 0)
3241                 return (-1);
3242         return (0);
3243 }
3244
3245 int
3246 pmc_start(pmc_id_t pmc)
3247 {
3248         struct pmc_op_simple    pmc_start_args;
3249
3250         pmc_start_args.pm_pmcid = pmc;
3251         return (PMC_CALL(PMCSTART, &pmc_start_args));
3252 }
3253
3254 int
3255 pmc_stop(pmc_id_t pmc)
3256 {
3257         struct pmc_op_simple    pmc_stop_args;
3258
3259         pmc_stop_args.pm_pmcid = pmc;
3260         return (PMC_CALL(PMCSTOP, &pmc_stop_args));
3261 }
3262
3263 int
3264 pmc_width(pmc_id_t pmcid, uint32_t *width)
3265 {
3266         unsigned int i;
3267         enum pmc_class cl;
3268
3269         cl = PMC_ID_TO_CLASS(pmcid);
3270         for (i = 0; i < cpu_info.pm_nclass; i++)
3271                 if (cpu_info.pm_classes[i].pm_class == cl) {
3272                         *width = cpu_info.pm_classes[i].pm_width;
3273                         return (0);
3274                 }
3275         errno = EINVAL;
3276         return (-1);
3277 }
3278
3279 int
3280 pmc_write(pmc_id_t pmc, pmc_value_t value)
3281 {
3282         struct pmc_op_pmcrw pmc_write_op;
3283
3284         pmc_write_op.pm_pmcid = pmc;
3285         pmc_write_op.pm_flags = PMC_F_NEWVALUE;
3286         pmc_write_op.pm_value = value;
3287         return (PMC_CALL(PMCRW, &pmc_write_op));
3288 }
3289
3290 int
3291 pmc_writelog(uint32_t userdata)
3292 {
3293         struct pmc_op_writelog wl;
3294
3295         wl.pm_userdata = userdata;
3296         return (PMC_CALL(WRITELOG, &wl));
3297 }