2 * Copyright (c) 2003-2008 Joseph Koshy
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/types.h>
31 #include <sys/module.h>
33 #include <sys/syscall.h>
45 #include "libpmcinternal.h"
47 /* Function prototypes */
49 static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
50 struct pmc_op_pmcallocate *_pmc_config);
52 #if defined(__amd64__) || defined(__i386__)
53 static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
54 struct pmc_op_pmcallocate *_pmc_config);
55 static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
56 struct pmc_op_pmcallocate *_pmc_config);
57 static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
58 struct pmc_op_pmcallocate *_pmc_config);
59 static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
60 struct pmc_op_pmcallocate *_pmc_config);
61 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
62 struct pmc_op_pmcallocate *_pmc_config);
63 static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
64 struct pmc_op_pmcallocate *_pmc_config);
67 static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
68 struct pmc_op_pmcallocate *_pmc_config);
69 static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
70 struct pmc_op_pmcallocate *_pmc_config);
72 #if defined(__amd64__) || defined(__i386__)
73 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
74 struct pmc_op_pmcallocate *_pmc_config);
76 #if defined(__XSCALE__)
77 static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
78 struct pmc_op_pmcallocate *_pmc_config);
81 static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec,
82 struct pmc_op_pmcallocate *_pmc_config);
84 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
85 struct pmc_op_pmcallocate *_pmc_config);
87 #if defined(__powerpc__)
88 static int ppc7450_allocate_pmc(enum pmc_event _pe, char* ctrspec,
89 struct pmc_op_pmcallocate *_pmc_config);
90 #endif /* __powerpc__ */
92 #define PMC_CALL(cmd, params) \
93 syscall(pmc_syscall, PMC_OP_##cmd, (params))
96 * Event aliases provide a way for the user to ask for generic events
97 * like "cache-misses", or "instructions-retired". These aliases are
98 * mapped to the appropriate canonical event descriptions using a
101 struct pmc_event_alias {
102 const char *pm_alias;
106 static const struct pmc_event_alias *pmc_mdep_event_aliases;
109 * The pmc_event_descr structure maps symbolic names known to the user
110 * to integer codes used by the PMC KLD.
112 struct pmc_event_descr {
113 const char *pm_ev_name;
114 enum pmc_event pm_ev_code;
118 * The pmc_class_descr structure maps class name prefixes for
119 * event names to event tables and other PMC class data.
121 struct pmc_class_descr {
122 const char *pm_evc_name;
123 size_t pm_evc_name_size;
124 enum pmc_class pm_evc_class;
125 const struct pmc_event_descr *pm_evc_event_table;
126 size_t pm_evc_event_table_size;
127 int (*pm_evc_allocate_pmc)(enum pmc_event _pe,
128 char *_ctrspec, struct pmc_op_pmcallocate *_pa);
131 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0]))
132 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table)
135 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N },
138 * PMC_CLASSDEP_TABLE(NAME, CLASS)
140 * Define a table mapping event names and aliases to HWPMC event IDs.
142 #define PMC_CLASSDEP_TABLE(N, C) \
143 static const struct pmc_event_descr N##_event_table[] = \
148 PMC_CLASSDEP_TABLE(iaf, IAF);
149 PMC_CLASSDEP_TABLE(k7, K7);
150 PMC_CLASSDEP_TABLE(k8, K8);
151 PMC_CLASSDEP_TABLE(p4, P4);
152 PMC_CLASSDEP_TABLE(p5, P5);
153 PMC_CLASSDEP_TABLE(p6, P6);
154 PMC_CLASSDEP_TABLE(xscale, XSCALE);
155 PMC_CLASSDEP_TABLE(mips24k, MIPS24K);
156 PMC_CLASSDEP_TABLE(octeon, OCTEON);
157 PMC_CLASSDEP_TABLE(ucf, UCF);
158 PMC_CLASSDEP_TABLE(ppc7450, PPC7450);
160 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT];
162 #undef __PMC_EV_ALIAS
163 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE },
165 static const struct pmc_event_descr atom_event_table[] =
167 __PMC_EV_ALIAS_ATOM()
170 static const struct pmc_event_descr core_event_table[] =
172 __PMC_EV_ALIAS_CORE()
176 static const struct pmc_event_descr core2_event_table[] =
178 __PMC_EV_ALIAS_CORE2()
181 static const struct pmc_event_descr corei7_event_table[] =
183 __PMC_EV_ALIAS_COREI7()
186 static const struct pmc_event_descr ivybridge_event_table[] =
188 __PMC_EV_ALIAS_IVYBRIDGE()
191 static const struct pmc_event_descr ivybridge_xeon_event_table[] =
193 __PMC_EV_ALIAS_IVYBRIDGE_XEON()
196 static const struct pmc_event_descr sandybridge_event_table[] =
198 __PMC_EV_ALIAS_SANDYBRIDGE()
201 static const struct pmc_event_descr sandybridge_xeon_event_table[] =
203 __PMC_EV_ALIAS_SANDYBRIDGE_XEON()
206 static const struct pmc_event_descr westmere_event_table[] =
208 __PMC_EV_ALIAS_WESTMERE()
211 static const struct pmc_event_descr corei7uc_event_table[] =
213 __PMC_EV_ALIAS_COREI7UC()
216 static const struct pmc_event_descr sandybridgeuc_event_table[] =
218 __PMC_EV_ALIAS_SANDYBRIDGEUC()
221 static const struct pmc_event_descr westmereuc_event_table[] =
223 __PMC_EV_ALIAS_WESTMEREUC()
227 * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...)
229 * Map a CPU to the PMC classes it supports.
231 #define PMC_MDEP_TABLE(N,C,...) \
232 static const enum pmc_class N##_pmc_classes[] = { \
233 PMC_CLASS_##C, __VA_ARGS__ \
236 PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
237 PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC);
238 PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
239 PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
240 PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
241 PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
242 PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
243 PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
244 PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
245 PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC);
246 PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC);
247 PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC);
248 PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC);
249 PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC);
250 PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE);
251 PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K);
252 PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON);
253 PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450);
254 PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT);
256 static const struct pmc_event_descr tsc_event_table[] =
261 #undef PMC_CLASS_TABLE_DESC
262 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \
263 static const struct pmc_class_descr NAME##_class_table_descr = \
265 .pm_evc_name = #CLASS "-", \
266 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \
267 .pm_evc_class = PMC_CLASS_##CLASS , \
268 .pm_evc_event_table = EVENTS##_event_table , \
269 .pm_evc_event_table_size = \
270 PMC_EVENT_TABLE_SIZE(EVENTS), \
271 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \
274 #if defined(__i386__) || defined(__amd64__)
275 PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf);
276 PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap);
277 PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
278 PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
279 PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
280 PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap);
281 PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap);
282 PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap);
283 PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap);
284 PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
285 PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
286 PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
287 PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp);
288 PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp);
290 #if defined(__i386__)
291 PMC_CLASS_TABLE_DESC(k7, K7, k7, k7);
293 #if defined(__i386__) || defined(__amd64__)
294 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
295 PMC_CLASS_TABLE_DESC(p4, P4, p4, p4);
297 #if defined(__i386__)
298 PMC_CLASS_TABLE_DESC(p5, P5, p5, p5);
299 PMC_CLASS_TABLE_DESC(p6, P6, p6, p6);
301 #if defined(__i386__) || defined(__amd64__)
302 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);
304 #if defined(__XSCALE__)
305 PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale);
307 #if defined(__mips__)
308 PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips);
309 PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips);
310 #endif /* __mips__ */
311 #if defined(__powerpc__)
312 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, ppc7450);
315 static struct pmc_class_descr soft_class_table_descr =
317 .pm_evc_name = "SOFT-",
318 .pm_evc_name_size = sizeof("SOFT-") - 1,
319 .pm_evc_class = PMC_CLASS_SOFT,
320 .pm_evc_event_table = NULL,
321 .pm_evc_event_table_size = 0,
322 .pm_evc_allocate_pmc = soft_allocate_pmc
325 #undef PMC_CLASS_TABLE_DESC
327 static const struct pmc_class_descr **pmc_class_table;
328 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass
330 static const enum pmc_class *pmc_mdep_class_list;
331 static size_t pmc_mdep_class_list_size;
334 * Mapping tables, mapping enumeration values to human readable
338 static const char * pmc_capability_names[] = {
340 #define __PMC_CAP(N,V,D) #N ,
344 static const char * pmc_class_names[] = {
346 #define __PMC_CLASS(C) #C ,
350 struct pmc_cputype_map {
351 enum pmc_cputype pm_cputype;
355 static const struct pmc_cputype_map pmc_cputype_names[] = {
357 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } ,
361 static const char * pmc_disposition_names[] = {
363 #define __PMC_DISP(D) #D ,
367 static const char * pmc_mode_names[] = {
369 #define __PMC_MODE(M,N) #M ,
373 static const char * pmc_state_names[] = {
375 #define __PMC_STATE(S) #S ,
380 * Filled in by pmc_init().
382 static int pmc_syscall = -1;
383 static struct pmc_cpuinfo cpu_info;
384 static struct pmc_op_getdyneventinfo soft_event_info;
386 /* Event masks for events */
389 const uint64_t pm_value;
391 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) }
392 #define NULLMASK { .pm_name = NULL }
394 #if defined(__amd64__) || defined(__i386__)
396 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask)
398 const struct pmc_masks *pm;
402 if (pmask == NULL) /* no mask keywords */
404 q = strchr(p, '='); /* skip '=' */
405 if (*++q == '\0') /* no more data */
407 c = 0; /* count of mask keywords seen */
408 while ((r = strsep(&q, "+")) != NULL) {
409 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name);
412 if (pm->pm_name == NULL) /* not found */
414 *evmask |= pm->pm_value;
421 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0)
422 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0)
423 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S }
425 #if defined(__i386__)
428 * AMD K7 (Athlon) CPUs.
431 static struct pmc_event_alias k7_aliases[] = {
432 EV_ALIAS("branches", "k7-retired-branches"),
433 EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"),
434 EV_ALIAS("cycles", "tsc"),
435 EV_ALIAS("dc-misses", "k7-dc-misses"),
436 EV_ALIAS("ic-misses", "k7-ic-misses"),
437 EV_ALIAS("instructions", "k7-retired-instructions"),
438 EV_ALIAS("interrupts", "k7-hardware-interrupts"),
442 #define K7_KW_COUNT "count"
443 #define K7_KW_EDGE "edge"
444 #define K7_KW_INV "inv"
445 #define K7_KW_OS "os"
446 #define K7_KW_UNITMASK "unitmask"
447 #define K7_KW_USR "usr"
450 k7_allocate_pmc(enum pmc_event pe, char *ctrspec,
451 struct pmc_op_pmcallocate *pmc_config)
455 uint32_t count, unitmask;
457 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
458 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
460 if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 ||
461 pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM ||
462 pe == PMC_EV_K7_DC_WRITEBACKS) {
464 unitmask = AMD_PMC_UNITMASK_MOESI;
466 unitmask = has_unitmask = 0;
468 while ((p = strsep(&ctrspec, ",")) != NULL) {
469 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) {
471 if (*++q == '\0') /* skip '=' */
474 count = strtol(q, &e, 0);
475 if (e == q || *e != '\0')
478 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
479 pmc_config->pm_md.pm_amd.pm_amd_config |=
480 AMD_PMC_TO_COUNTER(count);
482 } else if (KWMATCH(p, K7_KW_EDGE)) {
483 pmc_config->pm_caps |= PMC_CAP_EDGE;
484 } else if (KWMATCH(p, K7_KW_INV)) {
485 pmc_config->pm_caps |= PMC_CAP_INVERT;
486 } else if (KWMATCH(p, K7_KW_OS)) {
487 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
488 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) {
489 if (has_unitmask == 0)
493 if (*++q == '\0') /* skip '=' */
496 while ((c = tolower(*q++)) != 0)
498 unitmask |= AMD_PMC_UNITMASK_M;
500 unitmask |= AMD_PMC_UNITMASK_O;
502 unitmask |= AMD_PMC_UNITMASK_E;
504 unitmask |= AMD_PMC_UNITMASK_S;
506 unitmask |= AMD_PMC_UNITMASK_I;
515 } else if (KWMATCH(p, K7_KW_USR)) {
516 pmc_config->pm_caps |= PMC_CAP_USER;
522 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
523 pmc_config->pm_md.pm_amd.pm_amd_config |=
524 AMD_PMC_TO_UNITMASK(unitmask);
533 #if defined(__amd64__) || defined(__i386__)
536 * Intel Core (Family 6, Model E) PMCs.
539 static struct pmc_event_alias core_aliases[] = {
540 EV_ALIAS("branches", "iap-br-instr-ret"),
541 EV_ALIAS("branch-mispredicts", "iap-br-mispred-ret"),
542 EV_ALIAS("cycles", "tsc-tsc"),
543 EV_ALIAS("ic-misses", "iap-icache-misses"),
544 EV_ALIAS("instructions", "iap-instr-ret"),
545 EV_ALIAS("interrupts", "iap-core-hw-int-rx"),
546 EV_ALIAS("unhalted-cycles", "iap-unhalted-core-cycles"),
551 * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H)
552 * and Atom (Family 6, model 1CH) PMCs.
554 * We map aliases to events on the fixed-function counters if these
555 * are present. Note that not all CPUs in this family contain fixed-function
559 static struct pmc_event_alias core2_aliases[] = {
560 EV_ALIAS("branches", "iap-br-inst-retired.any"),
561 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"),
562 EV_ALIAS("cycles", "tsc-tsc"),
563 EV_ALIAS("ic-misses", "iap-l1i-misses"),
564 EV_ALIAS("instructions", "iaf-instr-retired.any"),
565 EV_ALIAS("interrupts", "iap-hw-int-rcv"),
566 EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"),
570 static struct pmc_event_alias core2_aliases_without_iaf[] = {
571 EV_ALIAS("branches", "iap-br-inst-retired.any"),
572 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"),
573 EV_ALIAS("cycles", "tsc-tsc"),
574 EV_ALIAS("ic-misses", "iap-l1i-misses"),
575 EV_ALIAS("instructions", "iap-inst-retired.any_p"),
576 EV_ALIAS("interrupts", "iap-hw-int-rcv"),
577 EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"),
581 #define atom_aliases core2_aliases
582 #define atom_aliases_without_iaf core2_aliases_without_iaf
583 #define corei7_aliases core2_aliases
584 #define corei7_aliases_without_iaf core2_aliases_without_iaf
585 #define ivybridge_aliases core2_aliases
586 #define ivybridge_aliases_without_iaf core2_aliases_without_iaf
587 #define ivybridge_xeon_aliases core2_aliases
588 #define ivybridge_xeon_aliases_without_iaf core2_aliases_without_iaf
589 #define sandybridge_aliases core2_aliases
590 #define sandybridge_aliases_without_iaf core2_aliases_without_iaf
591 #define sandybridge_xeon_aliases core2_aliases
592 #define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf
593 #define westmere_aliases core2_aliases
594 #define westmere_aliases_without_iaf core2_aliases_without_iaf
596 #define IAF_KW_OS "os"
597 #define IAF_KW_USR "usr"
598 #define IAF_KW_ANYTHREAD "anythread"
601 * Parse an event specifier for Intel fixed function counters.
604 iaf_allocate_pmc(enum pmc_event pe, char *ctrspec,
605 struct pmc_op_pmcallocate *pmc_config)
611 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
612 pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0;
614 while ((p = strsep(&ctrspec, ",")) != NULL) {
615 if (KWMATCH(p, IAF_KW_OS))
616 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
617 else if (KWMATCH(p, IAF_KW_USR))
618 pmc_config->pm_caps |= PMC_CAP_USER;
619 else if (KWMATCH(p, IAF_KW_ANYTHREAD))
620 pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY;
629 * Core/Core2 support.
632 #define IAP_KW_AGENT "agent"
633 #define IAP_KW_ANYTHREAD "anythread"
634 #define IAP_KW_CACHESTATE "cachestate"
635 #define IAP_KW_CMASK "cmask"
636 #define IAP_KW_CORE "core"
637 #define IAP_KW_EDGE "edge"
638 #define IAP_KW_INV "inv"
639 #define IAP_KW_OS "os"
640 #define IAP_KW_PREFETCH "prefetch"
641 #define IAP_KW_SNOOPRESPONSE "snoopresponse"
642 #define IAP_KW_SNOOPTYPE "snooptype"
643 #define IAP_KW_TRANSITION "trans"
644 #define IAP_KW_USR "usr"
645 #define IAP_KW_RSP "rsp"
647 static struct pmc_masks iap_core_mask[] = {
648 PMCMASK(all, (0x3 << 14)),
649 PMCMASK(this, (0x1 << 14)),
653 static struct pmc_masks iap_agent_mask[] = {
655 PMCMASK(any, (0x1 << 13)),
659 static struct pmc_masks iap_prefetch_mask[] = {
660 PMCMASK(both, (0x3 << 12)),
661 PMCMASK(only, (0x1 << 12)),
666 static struct pmc_masks iap_cachestate_mask[] = {
667 PMCMASK(i, (1 << 8)),
668 PMCMASK(s, (1 << 9)),
669 PMCMASK(e, (1 << 10)),
670 PMCMASK(m, (1 << 11)),
674 static struct pmc_masks iap_snoopresponse_mask[] = {
675 PMCMASK(clean, (1 << 8)),
676 PMCMASK(hit, (1 << 9)),
677 PMCMASK(hitm, (1 << 11)),
681 static struct pmc_masks iap_snooptype_mask[] = {
682 PMCMASK(cmp2s, (1 << 8)),
683 PMCMASK(cmp2i, (1 << 9)),
687 static struct pmc_masks iap_transition_mask[] = {
689 PMCMASK(frequency, 0x10),
693 static struct pmc_masks iap_rsp_mask_i7_wm[] = {
694 PMCMASK(DMND_DATA_RD, (1 << 0)),
695 PMCMASK(DMND_RFO, (1 << 1)),
696 PMCMASK(DMND_IFETCH, (1 << 2)),
697 PMCMASK(WB, (1 << 3)),
698 PMCMASK(PF_DATA_RD, (1 << 4)),
699 PMCMASK(PF_RFO, (1 << 5)),
700 PMCMASK(PF_IFETCH, (1 << 6)),
701 PMCMASK(OTHER, (1 << 7)),
702 PMCMASK(UNCORE_HIT, (1 << 8)),
703 PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)),
704 PMCMASK(OTHER_CORE_HITM, (1 << 10)),
705 PMCMASK(REMOTE_CACHE_FWD, (1 << 12)),
706 PMCMASK(REMOTE_DRAM, (1 << 13)),
707 PMCMASK(LOCAL_DRAM, (1 << 14)),
708 PMCMASK(NON_DRAM, (1 << 15)),
712 static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = {
713 PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)),
714 PMCMASK(REQ_DMND_RFO, (1ULL << 1)),
715 PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)),
716 PMCMASK(REQ_WB, (1ULL << 3)),
717 PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)),
718 PMCMASK(REQ_PF_RFO, (1ULL << 5)),
719 PMCMASK(REQ_PF_IFETCH, (1ULL << 6)),
720 PMCMASK(REQ_PF_LLC_DATA_RD, (1ULL << 7)),
721 PMCMASK(REQ_PF_LLC_RFO, (1ULL << 8)),
722 PMCMASK(REQ_PF_LLC_IFETCH, (1ULL << 9)),
723 PMCMASK(REQ_BUS_LOCKS, (1ULL << 10)),
724 PMCMASK(REQ_STRM_ST, (1ULL << 11)),
725 PMCMASK(REQ_OTHER, (1ULL << 15)),
726 PMCMASK(RES_ANY, (1ULL << 16)),
727 PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)),
728 PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)),
729 PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)),
730 PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)),
731 PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)),
732 PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)),
733 PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)),
734 PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
735 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)),
736 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)),
737 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)),
738 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)),
739 PMCMASK(RES_NON_DRAM, (1ULL << 37)),
744 iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
745 struct pmc_op_pmcallocate *pmc_config)
748 uint64_t cachestate, evmask, rsp;
751 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
753 pmc_config->pm_md.pm_iap.pm_iap_config = 0;
755 cachestate = evmask = rsp = 0;
757 /* Parse additional modifiers if present */
758 while ((p = strsep(&ctrspec, ",")) != NULL) {
761 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) {
763 if (*++q == '\0') /* skip '=' */
765 count = strtol(q, &e, 0);
766 if (e == q || *e != '\0')
768 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
769 pmc_config->pm_md.pm_iap.pm_iap_config |=
771 } else if (KWMATCH(p, IAP_KW_EDGE)) {
772 pmc_config->pm_caps |= PMC_CAP_EDGE;
773 } else if (KWMATCH(p, IAP_KW_INV)) {
774 pmc_config->pm_caps |= PMC_CAP_INVERT;
775 } else if (KWMATCH(p, IAP_KW_OS)) {
776 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
777 } else if (KWMATCH(p, IAP_KW_USR)) {
778 pmc_config->pm_caps |= PMC_CAP_USER;
779 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) {
780 pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY;
781 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) {
782 n = pmc_parse_mask(iap_core_mask, p, &evmask);
785 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) {
786 n = pmc_parse_mask(iap_agent_mask, p, &evmask);
789 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) {
790 n = pmc_parse_mask(iap_prefetch_mask, p, &evmask);
793 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) {
794 n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate);
795 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE &&
796 KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) {
797 n = pmc_parse_mask(iap_transition_mask, p, &evmask);
800 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM ||
801 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 ||
802 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) {
803 if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) {
804 n = pmc_parse_mask(iap_snoopresponse_mask, p,
806 } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) {
807 n = pmc_parse_mask(iap_snooptype_mask, p,
811 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 ||
812 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) {
813 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
814 n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp);
817 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
818 cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON ||
819 cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE ||
820 cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON ) {
821 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
822 n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp);
828 if (n < 0) /* Parsing failed. */
832 pmc_config->pm_md.pm_iap.pm_iap_config |= evmask;
835 * If the event requires a 'cachestate' qualifier but was not
836 * specified by the user, use a sensible default.
839 case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */
840 case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */
841 case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */
842 case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */
843 case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */
844 case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */
845 case PMC_EV_IAP_EVENT_32H: /* Core */
846 case PMC_EV_IAP_EVENT_40H: /* Core */
847 case PMC_EV_IAP_EVENT_41H: /* Core */
848 case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */
850 cachestate = (0xF << 8);
852 case PMC_EV_IAP_EVENT_77H: /* Atom */
853 /* IAP_EVENT_77H only accepts a cachestate qualifier on the
856 if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0)
857 cachestate = (0xF << 8);
863 pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate;
864 pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp;
874 ucf_allocate_pmc(enum pmc_event pe, char *ctrspec,
875 struct pmc_op_pmcallocate *pmc_config)
880 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
881 pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0;
886 #define UCP_KW_CMASK "cmask"
887 #define UCP_KW_EDGE "edge"
888 #define UCP_KW_INV "inv"
891 ucp_allocate_pmc(enum pmc_event pe, char *ctrspec,
892 struct pmc_op_pmcallocate *pmc_config)
899 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
901 pmc_config->pm_md.pm_ucp.pm_ucp_config = 0;
903 /* Parse additional modifiers if present */
904 while ((p = strsep(&ctrspec, ",")) != NULL) {
907 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) {
909 if (*++q == '\0') /* skip '=' */
911 count = strtol(q, &e, 0);
912 if (e == q || *e != '\0')
914 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
915 pmc_config->pm_md.pm_ucp.pm_ucp_config |=
917 } else if (KWMATCH(p, UCP_KW_EDGE)) {
918 pmc_config->pm_caps |= PMC_CAP_EDGE;
919 } else if (KWMATCH(p, UCP_KW_INV)) {
920 pmc_config->pm_caps |= PMC_CAP_INVERT;
924 if (n < 0) /* Parsing failed. */
934 * These are very similar to AMD K7 PMCs, but support more kinds of
938 static struct pmc_event_alias k8_aliases[] = {
939 EV_ALIAS("branches", "k8-fr-retired-taken-branches"),
940 EV_ALIAS("branch-mispredicts",
941 "k8-fr-retired-taken-branches-mispredicted"),
942 EV_ALIAS("cycles", "tsc"),
943 EV_ALIAS("dc-misses", "k8-dc-miss"),
944 EV_ALIAS("ic-misses", "k8-ic-miss"),
945 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"),
946 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"),
947 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"),
951 #define __K8MASK(N,V) PMCMASK(N,(1 << (V)))
957 /* fp dispatched fpu ops */
958 static const struct pmc_masks k8_mask_fdfo[] = {
959 __K8MASK(add-pipe-excluding-junk-ops, 0),
960 __K8MASK(multiply-pipe-excluding-junk-ops, 1),
961 __K8MASK(store-pipe-excluding-junk-ops, 2),
962 __K8MASK(add-pipe-junk-ops, 3),
963 __K8MASK(multiply-pipe-junk-ops, 4),
964 __K8MASK(store-pipe-junk-ops, 5),
968 /* ls segment register loads */
969 static const struct pmc_masks k8_mask_lsrl[] = {
980 /* ls locked operation */
981 static const struct pmc_masks k8_mask_llo[] = {
982 __K8MASK(locked-instructions, 0),
983 __K8MASK(cycles-in-request, 1),
984 __K8MASK(cycles-to-complete, 2),
988 /* dc refill from {l2,system} and dc copyback */
989 static const struct pmc_masks k8_mask_dc[] = {
990 __K8MASK(invalid, 0),
992 __K8MASK(exclusive, 2),
994 __K8MASK(modified, 4),
998 /* dc one bit ecc error */
999 static const struct pmc_masks k8_mask_dobee[] = {
1000 __K8MASK(scrubber, 0),
1001 __K8MASK(piggyback, 1),
1005 /* dc dispatched prefetch instructions */
1006 static const struct pmc_masks k8_mask_ddpi[] = {
1013 /* dc dcache accesses by locks */
1014 static const struct pmc_masks k8_mask_dabl[] = {
1015 __K8MASK(accesses, 0),
1016 __K8MASK(misses, 1),
1020 /* bu internal l2 request */
1021 static const struct pmc_masks k8_mask_bilr[] = {
1022 __K8MASK(ic-fill, 0),
1023 __K8MASK(dc-fill, 1),
1024 __K8MASK(tlb-reload, 2),
1025 __K8MASK(tag-snoop, 3),
1026 __K8MASK(cancelled, 4),
1030 /* bu fill request l2 miss */
1031 static const struct pmc_masks k8_mask_bfrlm[] = {
1032 __K8MASK(ic-fill, 0),
1033 __K8MASK(dc-fill, 1),
1034 __K8MASK(tlb-reload, 2),
1038 /* bu fill into l2 */
1039 static const struct pmc_masks k8_mask_bfil[] = {
1040 __K8MASK(dirty-l2-victim, 0),
1041 __K8MASK(victim-from-l2, 1),
1045 /* fr retired fpu instructions */
1046 static const struct pmc_masks k8_mask_frfi[] = {
1048 __K8MASK(mmx-3dnow, 1),
1049 __K8MASK(packed-sse-sse2, 2),
1050 __K8MASK(scalar-sse-sse2, 3),
1054 /* fr retired fastpath double op instructions */
1055 static const struct pmc_masks k8_mask_frfdoi[] = {
1056 __K8MASK(low-op-pos-0, 0),
1057 __K8MASK(low-op-pos-1, 1),
1058 __K8MASK(low-op-pos-2, 2),
1062 /* fr fpu exceptions */
1063 static const struct pmc_masks k8_mask_ffe[] = {
1064 __K8MASK(x87-reclass-microfaults, 0),
1065 __K8MASK(sse-retype-microfaults, 1),
1066 __K8MASK(sse-reclass-microfaults, 2),
1067 __K8MASK(sse-and-x87-microtraps, 3),
1071 /* nb memory controller page access event */
1072 static const struct pmc_masks k8_mask_nmcpae[] = {
1073 __K8MASK(page-hit, 0),
1074 __K8MASK(page-miss, 1),
1075 __K8MASK(page-conflict, 2),
1079 /* nb memory controller turnaround */
1080 static const struct pmc_masks k8_mask_nmct[] = {
1081 __K8MASK(dimm-turnaround, 0),
1082 __K8MASK(read-to-write-turnaround, 1),
1083 __K8MASK(write-to-read-turnaround, 2),
1087 /* nb memory controller bypass saturation */
1088 static const struct pmc_masks k8_mask_nmcbs[] = {
1089 __K8MASK(memory-controller-hi-pri-bypass, 0),
1090 __K8MASK(memory-controller-lo-pri-bypass, 1),
1091 __K8MASK(dram-controller-interface-bypass, 2),
1092 __K8MASK(dram-controller-queue-bypass, 3),
1096 /* nb sized commands */
1097 static const struct pmc_masks k8_mask_nsc[] = {
1098 __K8MASK(nonpostwrszbyte, 0),
1099 __K8MASK(nonpostwrszdword, 1),
1100 __K8MASK(postwrszbyte, 2),
1101 __K8MASK(postwrszdword, 3),
1102 __K8MASK(rdszbyte, 4),
1103 __K8MASK(rdszdword, 5),
1104 __K8MASK(rdmodwr, 6),
1108 /* nb probe result */
1109 static const struct pmc_masks k8_mask_npr[] = {
1110 __K8MASK(probe-miss, 0),
1111 __K8MASK(probe-hit, 1),
1112 __K8MASK(probe-hit-dirty-no-memory-cancel, 2),
1113 __K8MASK(probe-hit-dirty-with-memory-cancel, 3),
1117 /* nb hypertransport bus bandwidth */
1118 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */
1119 __K8MASK(command, 0),
1121 __K8MASK(buffer-release, 2),
1128 #define K8_KW_COUNT "count"
1129 #define K8_KW_EDGE "edge"
1130 #define K8_KW_INV "inv"
1131 #define K8_KW_MASK "mask"
1132 #define K8_KW_OS "os"
1133 #define K8_KW_USR "usr"
1136 k8_allocate_pmc(enum pmc_event pe, char *ctrspec,
1137 struct pmc_op_pmcallocate *pmc_config)
1143 const struct pmc_masks *pm, *pmask;
1145 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1146 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
1151 #define __K8SETMASK(M) pmask = k8_mask_##M
1153 /* setup parsing tables */
1155 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1158 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD:
1161 case PMC_EV_K8_LS_LOCKED_OPERATION:
1164 case PMC_EV_K8_DC_REFILL_FROM_L2:
1165 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM:
1166 case PMC_EV_K8_DC_COPYBACK:
1169 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR:
1172 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS:
1175 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1178 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST:
1181 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS:
1184 case PMC_EV_K8_BU_FILL_INTO_L2:
1187 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1190 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1191 __K8SETMASK(frfdoi);
1193 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1196 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT:
1197 __K8SETMASK(nmcpae);
1199 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND:
1202 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION:
1205 case PMC_EV_K8_NB_SIZED_COMMANDS:
1208 case PMC_EV_K8_NB_PROBE_RESULT:
1211 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH:
1212 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH:
1213 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH:
1218 break; /* no options defined */
1221 while ((p = strsep(&ctrspec, ",")) != NULL) {
1222 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) {
1224 if (*++q == '\0') /* skip '=' */
1227 count = strtol(q, &e, 0);
1228 if (e == q || *e != '\0')
1231 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1232 pmc_config->pm_md.pm_amd.pm_amd_config |=
1233 AMD_PMC_TO_COUNTER(count);
1235 } else if (KWMATCH(p, K8_KW_EDGE)) {
1236 pmc_config->pm_caps |= PMC_CAP_EDGE;
1237 } else if (KWMATCH(p, K8_KW_INV)) {
1238 pmc_config->pm_caps |= PMC_CAP_INVERT;
1239 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) {
1240 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1242 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1243 } else if (KWMATCH(p, K8_KW_OS)) {
1244 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1245 } else if (KWMATCH(p, K8_KW_USR)) {
1246 pmc_config->pm_caps |= PMC_CAP_USER;
1251 /* other post processing */
1253 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1254 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED:
1255 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS:
1256 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1257 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1258 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1259 /* XXX only available in rev B and later */
1261 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1262 /* XXX only available in rev C and later */
1264 case PMC_EV_K8_LS_LOCKED_OPERATION:
1265 /* XXX CPU Rev A,B evmask is to be zero */
1266 if (evmask & (evmask - 1)) /* > 1 bit set */
1269 evmask = 0x01; /* Rev C and later: #instrs */
1270 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1274 if (evmask == 0 && pmask != NULL) {
1275 for (pm = pmask; pm->pm_name; pm++)
1276 evmask |= pm->pm_value;
1277 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1281 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
1282 pmc_config->pm_md.pm_amd.pm_amd_config =
1283 AMD_PMC_TO_UNITMASK(evmask);
1290 #if defined(__amd64__) || defined(__i386__)
1296 static struct pmc_event_alias p4_aliases[] = {
1297 EV_ALIAS("branches", "p4-branch-retired,mask=mmtp+mmtm"),
1298 EV_ALIAS("branch-mispredicts", "p4-mispred-branch-retired"),
1299 EV_ALIAS("cycles", "tsc"),
1300 EV_ALIAS("instructions",
1301 "p4-instr-retired,mask=nbogusntag+nbogustag"),
1302 EV_ALIAS("unhalted-cycles", "p4-global-power-events"),
1303 EV_ALIAS(NULL, NULL)
1306 #define P4_KW_ACTIVE "active"
1307 #define P4_KW_ACTIVE_ANY "any"
1308 #define P4_KW_ACTIVE_BOTH "both"
1309 #define P4_KW_ACTIVE_NONE "none"
1310 #define P4_KW_ACTIVE_SINGLE "single"
1311 #define P4_KW_BUSREQTYPE "busreqtype"
1312 #define P4_KW_CASCADE "cascade"
1313 #define P4_KW_EDGE "edge"
1314 #define P4_KW_INV "complement"
1315 #define P4_KW_OS "os"
1316 #define P4_KW_MASK "mask"
1317 #define P4_KW_PRECISE "precise"
1318 #define P4_KW_TAG "tag"
1319 #define P4_KW_THRESHOLD "threshold"
1320 #define P4_KW_USR "usr"
1322 #define __P4MASK(N,V) PMCMASK(N, (1 << (V)))
1324 static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */
1336 static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */
1337 __P4MASK(tcmiss, 0),
1341 static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */
1344 __P4MASK(hit-uc, 2),
1348 static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */
1349 __P4MASK(st-rb-full, 2),
1350 __P4MASK(64k-conf, 3),
1354 static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */
1360 static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */
1361 __P4MASK(split-ld, 1),
1365 static const struct pmc_masks p4_mask_spr[] = { /* store port replay */
1366 __P4MASK(split-st, 1),
1370 static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */
1371 __P4MASK(no-sta, 1),
1372 __P4MASK(no-std, 3),
1373 __P4MASK(partial-data, 4),
1374 __P4MASK(unalgn-addr, 5),
1378 static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */
1379 __P4MASK(dtmiss, 0),
1380 __P4MASK(itmiss, 1),
1384 static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */
1385 __P4MASK(rd-2ndl-hits, 0),
1386 __P4MASK(rd-2ndl-hite, 1),
1387 __P4MASK(rd-2ndl-hitm, 2),
1388 __P4MASK(rd-3rdl-hits, 3),
1389 __P4MASK(rd-3rdl-hite, 4),
1390 __P4MASK(rd-3rdl-hitm, 5),
1391 __P4MASK(rd-2ndl-miss, 8),
1392 __P4MASK(rd-3rdl-miss, 9),
1393 __P4MASK(wr-2ndl-miss, 10),
1397 static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */
1398 __P4MASK(all-read, 5),
1399 __P4MASK(all-write, 6),
1400 __P4MASK(mem-uc, 7),
1401 __P4MASK(mem-wc, 8),
1402 __P4MASK(mem-wt, 9),
1403 __P4MASK(mem-wp, 10),
1404 __P4MASK(mem-wb, 11),
1406 __P4MASK(other, 14),
1407 __P4MASK(prefetch, 15),
1411 static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */
1412 __P4MASK(all-read, 5),
1413 __P4MASK(all-write, 6),
1414 __P4MASK(mem-uc, 7),
1415 __P4MASK(mem-wc, 8),
1416 __P4MASK(mem-wt, 9),
1417 __P4MASK(mem-wp, 10),
1418 __P4MASK(mem-wb, 11),
1420 __P4MASK(other, 14),
1421 __P4MASK(prefetch, 15),
1425 static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */
1426 __P4MASK(drdy-drv, 0),
1427 __P4MASK(drdy-own, 1),
1428 __P4MASK(drdy-other, 2),
1429 __P4MASK(dbsy-drv, 3),
1430 __P4MASK(dbsy-own, 4),
1431 __P4MASK(dbsy-other, 5),
1435 static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */
1436 __P4MASK(req-type0, 0),
1437 __P4MASK(req-type1, 1),
1438 __P4MASK(req-len0, 2),
1439 __P4MASK(req-len1, 3),
1440 __P4MASK(req-io-type, 5),
1441 __P4MASK(req-lock-type, 6),
1442 __P4MASK(req-cache-type, 7),
1443 __P4MASK(req-split-type, 8),
1444 __P4MASK(req-dem-type, 9),
1445 __P4MASK(req-ord-type, 10),
1446 __P4MASK(mem-type0, 11),
1447 __P4MASK(mem-type1, 12),
1448 __P4MASK(mem-type2, 13),
1452 static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */
1457 static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */
1462 static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */
1467 static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */
1472 static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */
1477 static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */
1482 static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */
1487 static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */
1492 static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */
1498 static const struct pmc_masks p4_mask_gpe[] = { /* global power events */
1499 __P4MASK(running, 0),
1503 static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */
1508 static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */
1509 __P4MASK(from-tc-build, 0),
1510 __P4MASK(from-tc-deliver, 1),
1511 __P4MASK(from-rom, 2),
1515 static const struct pmc_masks p4_mask_rmbt[] = {
1516 /* retired mispred branch type */
1517 __P4MASK(conditional, 1),
1519 __P4MASK(return, 3),
1520 __P4MASK(indirect, 4),
1524 static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */
1525 __P4MASK(conditional, 1),
1527 __P4MASK(retired, 3),
1528 __P4MASK(indirect, 4),
1532 static const struct pmc_masks p4_mask_rs[] = { /* resource stall */
1533 __P4MASK(sbfull, 5),
1537 static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */
1538 __P4MASK(wcb-evicts, 0),
1539 __P4MASK(wcb-full-evict, 1),
1543 static const struct pmc_masks p4_mask_fee[] = { /* front end event */
1544 __P4MASK(nbogus, 0),
1549 static const struct pmc_masks p4_mask_ee[] = { /* execution event */
1550 __P4MASK(nbogus0, 0),
1551 __P4MASK(nbogus1, 1),
1552 __P4MASK(nbogus2, 2),
1553 __P4MASK(nbogus3, 3),
1554 __P4MASK(bogus0, 4),
1555 __P4MASK(bogus1, 5),
1556 __P4MASK(bogus2, 6),
1557 __P4MASK(bogus3, 7),
1561 static const struct pmc_masks p4_mask_re[] = { /* replay event */
1562 __P4MASK(nbogus, 0),
1567 static const struct pmc_masks p4_mask_insret[] = { /* instr retired */
1568 __P4MASK(nbogusntag, 0),
1569 __P4MASK(nbogustag, 1),
1570 __P4MASK(bogusntag, 2),
1571 __P4MASK(bogustag, 3),
1575 static const struct pmc_masks p4_mask_ur[] = { /* uops retired */
1576 __P4MASK(nbogus, 0),
1581 static const struct pmc_masks p4_mask_ut[] = { /* uop type */
1582 __P4MASK(tagloads, 1),
1583 __P4MASK(tagstores, 2),
1587 static const struct pmc_masks p4_mask_br[] = { /* branch retired */
1595 static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */
1596 __P4MASK(nbogus, 0),
1600 static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */
1609 static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */
1611 __P4MASK(moclear, 2),
1612 __P4MASK(smclear, 3),
1616 /* P4 event parser */
1618 p4_allocate_pmc(enum pmc_event pe, char *ctrspec,
1619 struct pmc_op_pmcallocate *pmc_config)
1623 int count, has_tag, has_busreqtype, n;
1624 uint32_t cccractivemask;
1626 const struct pmc_masks *pm, *pmask;
1628 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1629 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig =
1630 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0;
1634 cccractivemask = 0x3;
1635 has_tag = has_busreqtype = 0;
1637 #define __P4SETMASK(M) do { \
1638 pmask = p4_mask_##M; \
1642 case PMC_EV_P4_TC_DELIVER_MODE:
1645 case PMC_EV_P4_BPU_FETCH_REQUEST:
1648 case PMC_EV_P4_ITLB_REFERENCE:
1651 case PMC_EV_P4_MEMORY_CANCEL:
1652 __P4SETMASK(memcan);
1654 case PMC_EV_P4_MEMORY_COMPLETE:
1655 __P4SETMASK(memcomp);
1657 case PMC_EV_P4_LOAD_PORT_REPLAY:
1660 case PMC_EV_P4_STORE_PORT_REPLAY:
1663 case PMC_EV_P4_MOB_LOAD_REPLAY:
1666 case PMC_EV_P4_PAGE_WALK_TYPE:
1669 case PMC_EV_P4_BSQ_CACHE_REFERENCE:
1672 case PMC_EV_P4_IOQ_ALLOCATION:
1676 case PMC_EV_P4_IOQ_ACTIVE_ENTRIES:
1680 case PMC_EV_P4_FSB_DATA_ACTIVITY:
1683 case PMC_EV_P4_BSQ_ALLOCATION:
1686 case PMC_EV_P4_SSE_INPUT_ASSIST:
1689 case PMC_EV_P4_PACKED_SP_UOP:
1692 case PMC_EV_P4_PACKED_DP_UOP:
1695 case PMC_EV_P4_SCALAR_SP_UOP:
1698 case PMC_EV_P4_SCALAR_DP_UOP:
1701 case PMC_EV_P4_64BIT_MMX_UOP:
1704 case PMC_EV_P4_128BIT_MMX_UOP:
1705 __P4SETMASK(128bmu);
1707 case PMC_EV_P4_X87_FP_UOP:
1710 case PMC_EV_P4_X87_SIMD_MOVES_UOP:
1713 case PMC_EV_P4_GLOBAL_POWER_EVENTS:
1716 case PMC_EV_P4_TC_MS_XFER:
1719 case PMC_EV_P4_UOP_QUEUE_WRITES:
1722 case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE:
1725 case PMC_EV_P4_RETIRED_BRANCH_TYPE:
1728 case PMC_EV_P4_RESOURCE_STALL:
1731 case PMC_EV_P4_WC_BUFFER:
1734 case PMC_EV_P4_BSQ_ACTIVE_ENTRIES:
1735 case PMC_EV_P4_B2B_CYCLES:
1737 case PMC_EV_P4_SNOOP:
1738 case PMC_EV_P4_RESPONSE:
1740 case PMC_EV_P4_FRONT_END_EVENT:
1743 case PMC_EV_P4_EXECUTION_EVENT:
1746 case PMC_EV_P4_REPLAY_EVENT:
1749 case PMC_EV_P4_INSTR_RETIRED:
1750 __P4SETMASK(insret);
1752 case PMC_EV_P4_UOPS_RETIRED:
1755 case PMC_EV_P4_UOP_TYPE:
1758 case PMC_EV_P4_BRANCH_RETIRED:
1761 case PMC_EV_P4_MISPRED_BRANCH_RETIRED:
1764 case PMC_EV_P4_X87_ASSIST:
1767 case PMC_EV_P4_MACHINE_CLEAR:
1768 __P4SETMASK(machclr);
1774 /* process additional flags */
1775 while ((p = strsep(&ctrspec, ",")) != NULL) {
1776 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) {
1778 if (*++q == '\0') /* skip '=' */
1781 if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0)
1782 cccractivemask = 0x0;
1783 else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0)
1784 cccractivemask = 0x1;
1785 else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0)
1786 cccractivemask = 0x2;
1787 else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0)
1788 cccractivemask = 0x3;
1792 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) {
1793 if (has_busreqtype == 0)
1797 if (*++q == '\0') /* skip '=' */
1800 count = strtol(q, &e, 0);
1801 if (e == q || *e != '\0')
1803 evmask = (evmask & ~0x1F) | (count & 0x1F);
1804 } else if (KWMATCH(p, P4_KW_CASCADE))
1805 pmc_config->pm_caps |= PMC_CAP_CASCADE;
1806 else if (KWMATCH(p, P4_KW_EDGE))
1807 pmc_config->pm_caps |= PMC_CAP_EDGE;
1808 else if (KWMATCH(p, P4_KW_INV))
1809 pmc_config->pm_caps |= PMC_CAP_INVERT;
1810 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) {
1811 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1813 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1814 } else if (KWMATCH(p, P4_KW_OS))
1815 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1816 else if (KWMATCH(p, P4_KW_PRECISE))
1817 pmc_config->pm_caps |= PMC_CAP_PRECISE;
1818 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) {
1823 if (*++q == '\0') /* skip '=' */
1826 count = strtol(q, &e, 0);
1827 if (e == q || *e != '\0')
1830 pmc_config->pm_caps |= PMC_CAP_TAGGING;
1831 pmc_config->pm_md.pm_p4.pm_p4_escrconfig |=
1832 P4_ESCR_TO_TAG_VALUE(count);
1833 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) {
1835 if (*++q == '\0') /* skip '=' */
1838 count = strtol(q, &e, 0);
1839 if (e == q || *e != '\0')
1842 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1843 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &=
1844 ~P4_CCCR_THRESHOLD_MASK;
1845 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |=
1846 P4_CCCR_TO_THRESHOLD(count);
1847 } else if (KWMATCH(p, P4_KW_USR))
1848 pmc_config->pm_caps |= PMC_CAP_USER;
1853 /* other post processing */
1854 if (pe == PMC_EV_P4_IOQ_ALLOCATION ||
1855 pe == PMC_EV_P4_FSB_DATA_ACTIVITY ||
1856 pe == PMC_EV_P4_BSQ_ALLOCATION)
1857 pmc_config->pm_caps |= PMC_CAP_EDGE;
1859 /* fill in thread activity mask */
1860 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |=
1861 P4_CCCR_TO_ACTIVE_THREAD(cccractivemask);
1864 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1867 case PMC_EV_P4_FSB_DATA_ACTIVITY:
1868 if ((evmask & 0x06) == 0x06 ||
1869 (evmask & 0x18) == 0x18)
1870 return (-1); /* can't have own+other bits together */
1871 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */
1874 case PMC_EV_P4_MACHINE_CLEAR:
1875 /* only one bit is allowed to be set */
1876 if ((evmask & (evmask - 1)) != 0)
1879 evmask = 0x1; /* 'CLEAR' */
1880 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1884 if (evmask == 0 && pmask) {
1885 for (pm = pmask; pm->pm_name; pm++)
1886 evmask |= pm->pm_value;
1887 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1891 pmc_config->pm_md.pm_p4.pm_p4_escrconfig =
1892 P4_ESCR_TO_EVENT_MASK(evmask);
1899 #if defined(__i386__)
1902 * Pentium style PMCs
1905 static struct pmc_event_alias p5_aliases[] = {
1906 EV_ALIAS("branches", "p5-taken-branches"),
1907 EV_ALIAS("cycles", "tsc"),
1908 EV_ALIAS("dc-misses", "p5-data-read-miss-or-write-miss"),
1909 EV_ALIAS("ic-misses", "p5-code-cache-miss"),
1910 EV_ALIAS("instructions", "p5-instructions-executed"),
1911 EV_ALIAS("interrupts", "p5-hardware-interrupts"),
1912 EV_ALIAS("unhalted-cycles",
1913 "p5-number-of-cycles-not-in-halt-state"),
1914 EV_ALIAS(NULL, NULL)
1918 p5_allocate_pmc(enum pmc_event pe, char *ctrspec,
1919 struct pmc_op_pmcallocate *pmc_config)
1921 return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */
1925 * Pentium Pro style PMCs. These PMCs are found in Pentium II, Pentium III,
1926 * and Pentium M CPUs.
1929 static struct pmc_event_alias p6_aliases[] = {
1930 EV_ALIAS("branches", "p6-br-inst-retired"),
1931 EV_ALIAS("branch-mispredicts", "p6-br-miss-pred-retired"),
1932 EV_ALIAS("cycles", "tsc"),
1933 EV_ALIAS("dc-misses", "p6-dcu-lines-in"),
1934 EV_ALIAS("ic-misses", "p6-ifu-fetch-miss"),
1935 EV_ALIAS("instructions", "p6-inst-retired"),
1936 EV_ALIAS("interrupts", "p6-hw-int-rx"),
1937 EV_ALIAS("unhalted-cycles", "p6-cpu-clk-unhalted"),
1938 EV_ALIAS(NULL, NULL)
1941 #define P6_KW_CMASK "cmask"
1942 #define P6_KW_EDGE "edge"
1943 #define P6_KW_INV "inv"
1944 #define P6_KW_OS "os"
1945 #define P6_KW_UMASK "umask"
1946 #define P6_KW_USR "usr"
1948 static struct pmc_masks p6_mask_mesi[] = {
1956 static struct pmc_masks p6_mask_mesihw[] = {
1961 PMCMASK(nonhw, 0x00),
1963 PMCMASK(both, 0x30),
1967 static struct pmc_masks p6_mask_hw[] = {
1968 PMCMASK(nonhw, 0x00),
1970 PMCMASK(both, 0x30),
1974 static struct pmc_masks p6_mask_any[] = {
1975 PMCMASK(self, 0x00),
1980 static struct pmc_masks p6_mask_ekp[] = {
1988 static struct pmc_masks p6_mask_pps[] = {
1989 PMCMASK(packed-and-scalar, 0x00),
1990 PMCMASK(scalar, 0x01),
1994 static struct pmc_masks p6_mask_mite[] = {
1995 PMCMASK(packed-multiply, 0x01),
1996 PMCMASK(packed-shift, 0x02),
1997 PMCMASK(pack, 0x04),
1998 PMCMASK(unpack, 0x08),
1999 PMCMASK(packed-logical, 0x10),
2000 PMCMASK(packed-arithmetic, 0x20),
2004 static struct pmc_masks p6_mask_fmt[] = {
2005 PMCMASK(mmxtofp, 0x00),
2006 PMCMASK(fptommx, 0x01),
2010 static struct pmc_masks p6_mask_sr[] = {
2018 static struct pmc_masks p6_mask_eet[] = {
2020 PMCMASK(freq, 0x02),
2024 static struct pmc_masks p6_mask_efur[] = {
2026 PMCMASK(loadop, 0x01),
2027 PMCMASK(stdsta, 0x02),
2031 static struct pmc_masks p6_mask_essir[] = {
2032 PMCMASK(sse-packed-single, 0x00),
2033 PMCMASK(sse-packed-single-scalar-single, 0x01),
2034 PMCMASK(sse2-packed-double, 0x02),
2035 PMCMASK(sse2-scalar-double, 0x03),
2039 static struct pmc_masks p6_mask_esscir[] = {
2040 PMCMASK(sse-packed-single, 0x00),
2041 PMCMASK(sse-scalar-single, 0x01),
2042 PMCMASK(sse2-packed-double, 0x02),
2043 PMCMASK(sse2-scalar-double, 0x03),
2047 /* P6 event parser */
2049 p6_allocate_pmc(enum pmc_event pe, char *ctrspec,
2050 struct pmc_op_pmcallocate *pmc_config)
2055 const struct pmc_masks *pm, *pmask;
2057 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2058 pmc_config->pm_md.pm_ppro.pm_ppro_config = 0;
2062 #define P6MASKSET(M) pmask = p6_mask_ ## M
2065 case PMC_EV_P6_L2_IFETCH: P6MASKSET(mesi); break;
2066 case PMC_EV_P6_L2_LD: P6MASKSET(mesi); break;
2067 case PMC_EV_P6_L2_ST: P6MASKSET(mesi); break;
2068 case PMC_EV_P6_L2_RQSTS: P6MASKSET(mesi); break;
2069 case PMC_EV_P6_BUS_DRDY_CLOCKS:
2070 case PMC_EV_P6_BUS_LOCK_CLOCKS:
2071 case PMC_EV_P6_BUS_TRAN_BRD:
2072 case PMC_EV_P6_BUS_TRAN_RFO:
2073 case PMC_EV_P6_BUS_TRANS_WB:
2074 case PMC_EV_P6_BUS_TRAN_IFETCH:
2075 case PMC_EV_P6_BUS_TRAN_INVAL:
2076 case PMC_EV_P6_BUS_TRAN_PWR:
2077 case PMC_EV_P6_BUS_TRANS_P:
2078 case PMC_EV_P6_BUS_TRANS_IO:
2079 case PMC_EV_P6_BUS_TRAN_DEF:
2080 case PMC_EV_P6_BUS_TRAN_BURST:
2081 case PMC_EV_P6_BUS_TRAN_ANY:
2082 case PMC_EV_P6_BUS_TRAN_MEM:
2083 P6MASKSET(any); break;
2084 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED:
2085 case PMC_EV_P6_EMON_KNI_PREF_MISS:
2086 P6MASKSET(ekp); break;
2087 case PMC_EV_P6_EMON_KNI_INST_RETIRED:
2088 case PMC_EV_P6_EMON_KNI_COMP_INST_RET:
2089 P6MASKSET(pps); break;
2090 case PMC_EV_P6_MMX_INSTR_TYPE_EXEC:
2091 P6MASKSET(mite); break;
2092 case PMC_EV_P6_FP_MMX_TRANS:
2093 P6MASKSET(fmt); break;
2094 case PMC_EV_P6_SEG_RENAME_STALLS:
2095 case PMC_EV_P6_SEG_REG_RENAMES:
2096 P6MASKSET(sr); break;
2097 case PMC_EV_P6_EMON_EST_TRANS:
2098 P6MASKSET(eet); break;
2099 case PMC_EV_P6_EMON_FUSED_UOPS_RET:
2100 P6MASKSET(efur); break;
2101 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED:
2102 P6MASKSET(essir); break;
2103 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED:
2104 P6MASKSET(esscir); break;
2110 /* Pentium M PMCs have a few events with different semantics */
2111 if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) {
2112 if (pe == PMC_EV_P6_L2_LD ||
2113 pe == PMC_EV_P6_L2_LINES_IN ||
2114 pe == PMC_EV_P6_L2_LINES_OUT)
2116 else if (pe == PMC_EV_P6_L2_M_LINES_OUTM)
2120 /* Parse additional modifiers if present */
2121 while ((p = strsep(&ctrspec, ",")) != NULL) {
2122 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) {
2124 if (*++q == '\0') /* skip '=' */
2126 count = strtol(q, &e, 0);
2127 if (e == q || *e != '\0')
2129 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
2130 pmc_config->pm_md.pm_ppro.pm_ppro_config |=
2131 P6_EVSEL_TO_CMASK(count);
2132 } else if (KWMATCH(p, P6_KW_EDGE)) {
2133 pmc_config->pm_caps |= PMC_CAP_EDGE;
2134 } else if (KWMATCH(p, P6_KW_INV)) {
2135 pmc_config->pm_caps |= PMC_CAP_INVERT;
2136 } else if (KWMATCH(p, P6_KW_OS)) {
2137 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2138 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) {
2140 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
2142 if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS ||
2143 pe == PMC_EV_P6_BUS_LOCK_CLOCKS ||
2144 pe == PMC_EV_P6_BUS_TRAN_BRD ||
2145 pe == PMC_EV_P6_BUS_TRAN_RFO ||
2146 pe == PMC_EV_P6_BUS_TRAN_IFETCH ||
2147 pe == PMC_EV_P6_BUS_TRAN_INVAL ||
2148 pe == PMC_EV_P6_BUS_TRAN_PWR ||
2149 pe == PMC_EV_P6_BUS_TRAN_DEF ||
2150 pe == PMC_EV_P6_BUS_TRAN_BURST ||
2151 pe == PMC_EV_P6_BUS_TRAN_ANY ||
2152 pe == PMC_EV_P6_BUS_TRAN_MEM ||
2153 pe == PMC_EV_P6_BUS_TRANS_IO ||
2154 pe == PMC_EV_P6_BUS_TRANS_P ||
2155 pe == PMC_EV_P6_BUS_TRANS_WB ||
2156 pe == PMC_EV_P6_EMON_EST_TRANS ||
2157 pe == PMC_EV_P6_EMON_FUSED_UOPS_RET ||
2158 pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET ||
2159 pe == PMC_EV_P6_EMON_KNI_INST_RETIRED ||
2160 pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED ||
2161 pe == PMC_EV_P6_EMON_KNI_PREF_MISS ||
2162 pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED ||
2163 pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED ||
2164 pe == PMC_EV_P6_FP_MMX_TRANS)
2165 && (n > 1)) /* Only one mask keyword is allowed. */
2167 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
2168 } else if (KWMATCH(p, P6_KW_USR)) {
2169 pmc_config->pm_caps |= PMC_CAP_USER;
2174 /* post processing */
2178 * The following events default to an evmask of 0
2181 /* default => 'self' */
2182 case PMC_EV_P6_BUS_DRDY_CLOCKS:
2183 case PMC_EV_P6_BUS_LOCK_CLOCKS:
2184 case PMC_EV_P6_BUS_TRAN_BRD:
2185 case PMC_EV_P6_BUS_TRAN_RFO:
2186 case PMC_EV_P6_BUS_TRANS_WB:
2187 case PMC_EV_P6_BUS_TRAN_IFETCH:
2188 case PMC_EV_P6_BUS_TRAN_INVAL:
2189 case PMC_EV_P6_BUS_TRAN_PWR:
2190 case PMC_EV_P6_BUS_TRANS_P:
2191 case PMC_EV_P6_BUS_TRANS_IO:
2192 case PMC_EV_P6_BUS_TRAN_DEF:
2193 case PMC_EV_P6_BUS_TRAN_BURST:
2194 case PMC_EV_P6_BUS_TRAN_ANY:
2195 case PMC_EV_P6_BUS_TRAN_MEM:
2197 /* default => 'nta' */
2198 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED:
2199 case PMC_EV_P6_EMON_KNI_PREF_MISS:
2201 /* default => 'packed and scalar' */
2202 case PMC_EV_P6_EMON_KNI_INST_RETIRED:
2203 case PMC_EV_P6_EMON_KNI_COMP_INST_RET:
2205 /* default => 'mmx to fp transitions' */
2206 case PMC_EV_P6_FP_MMX_TRANS:
2208 /* default => 'SSE Packed Single' */
2209 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED:
2210 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED:
2212 /* default => 'all fused micro-ops' */
2213 case PMC_EV_P6_EMON_FUSED_UOPS_RET:
2215 /* default => 'all transitions' */
2216 case PMC_EV_P6_EMON_EST_TRANS:
2219 case PMC_EV_P6_MMX_UOPS_EXEC:
2220 evmask = 0x0F; /* only value allowed */
2225 * For all other events, set the default event mask
2226 * to a logical OR of all the allowed event mask bits.
2228 if (evmask == 0 && pmask) {
2229 for (pm = pmask; pm->pm_name; pm++)
2230 evmask |= pm->pm_value;
2231 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
2237 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
2238 pmc_config->pm_md.pm_ppro.pm_ppro_config |=
2239 P6_EVSEL_TO_UMASK(evmask);
2246 #if defined(__i386__) || defined(__amd64__)
2248 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec,
2249 struct pmc_op_pmcallocate *pmc_config)
2251 if (pe != PMC_EV_TSC_TSC)
2254 /* TSC events must be unqualified. */
2255 if (ctrspec && *ctrspec != '\0')
2258 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
2259 pmc_config->pm_caps |= PMC_CAP_READ;
2265 static struct pmc_event_alias generic_aliases[] = {
2266 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"),
2267 EV_ALIAS(NULL, NULL)
2271 soft_allocate_pmc(enum pmc_event pe, char *ctrspec,
2272 struct pmc_op_pmcallocate *pmc_config)
2277 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST)
2280 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2284 #if defined(__XSCALE__)
2286 static struct pmc_event_alias xscale_aliases[] = {
2287 EV_ALIAS("branches", "BRANCH_RETIRED"),
2288 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"),
2289 EV_ALIAS("dc-misses", "DC_MISS"),
2290 EV_ALIAS("ic-misses", "IC_MISS"),
2291 EV_ALIAS("instructions", "INSTR_RETIRED"),
2292 EV_ALIAS(NULL, NULL)
2295 xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2296 struct pmc_op_pmcallocate *pmc_config __unused)
2307 #if defined(__mips__)
2309 static struct pmc_event_alias mips24k_aliases[] = {
2310 EV_ALIAS("instructions", "INSTR_EXECUTED"),
2311 EV_ALIAS("branches", "BRANCH_COMPLETED"),
2312 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"),
2313 EV_ALIAS(NULL, NULL)
2316 static struct pmc_event_alias octeon_aliases[] = {
2317 EV_ALIAS("instructions", "RET"),
2318 EV_ALIAS("branches", "BR"),
2319 EV_ALIAS("branch-mispredicts", "BRMIS"),
2320 EV_ALIAS(NULL, NULL)
2323 #define MIPS_KW_OS "os"
2324 #define MIPS_KW_USR "usr"
2325 #define MIPS_KW_ANYTHREAD "anythread"
2328 mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2329 struct pmc_op_pmcallocate *pmc_config __unused)
2335 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2337 while ((p = strsep(&ctrspec, ",")) != NULL) {
2338 if (KWMATCH(p, MIPS_KW_OS))
2339 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2340 else if (KWMATCH(p, MIPS_KW_USR))
2341 pmc_config->pm_caps |= PMC_CAP_USER;
2342 else if (KWMATCH(p, MIPS_KW_ANYTHREAD))
2343 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
2351 #endif /* __mips__ */
2353 #if defined(__powerpc__)
2355 static struct pmc_event_alias ppc7450_aliases[] = {
2356 EV_ALIAS("instructions", "INSTR_COMPLETED"),
2357 EV_ALIAS("branches", "BRANCHES_COMPLETED"),
2358 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"),
2359 EV_ALIAS(NULL, NULL)
2362 #define PPC7450_KW_OS "os"
2363 #define PPC7450_KW_USR "usr"
2364 #define PPC7450_KW_ANYTHREAD "anythread"
2367 ppc7450_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2368 struct pmc_op_pmcallocate *pmc_config __unused)
2374 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2376 while ((p = strsep(&ctrspec, ",")) != NULL) {
2377 if (KWMATCH(p, PPC7450_KW_OS))
2378 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2379 else if (KWMATCH(p, PPC7450_KW_USR))
2380 pmc_config->pm_caps |= PMC_CAP_USER;
2381 else if (KWMATCH(p, PPC7450_KW_ANYTHREAD))
2382 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
2389 #endif /* __powerpc__ */
2393 * Match an event name `name' with its canonical form.
2395 * Matches are case insensitive and spaces, periods, underscores and
2396 * hyphen characters are considered to match each other.
2398 * Returns 1 for a match, 0 otherwise.
2402 pmc_match_event_name(const char *name, const char *canonicalname)
2405 const unsigned char *c, *n;
2407 c = (const unsigned char *) canonicalname;
2408 n = (const unsigned char *) name;
2410 for (; (nc = *n) && (cc = *c); n++, c++) {
2412 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') &&
2413 (cc == ' ' || cc == '_' || cc == '-' || cc == '.'))
2416 if (toupper(nc) == toupper(cc))
2423 if (*n == '\0' && *c == '\0')
2430 * Match an event name against all the event named supported by a
2433 * Returns an event descriptor pointer on match or NULL otherwise.
2435 static const struct pmc_event_descr *
2436 pmc_match_event_class(const char *name,
2437 const struct pmc_class_descr *pcd)
2440 const struct pmc_event_descr *ev;
2442 ev = pcd->pm_evc_event_table;
2443 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++)
2444 if (pmc_match_event_name(name, ev->pm_ev_name))
2451 pmc_mdep_is_compatible_class(enum pmc_class pc)
2455 for (n = 0; n < pmc_mdep_class_list_size; n++)
2456 if (pmc_mdep_class_list[n] == pc)
2466 pmc_allocate(const char *ctrspec, enum pmc_mode mode,
2467 uint32_t flags, int cpu, pmc_id_t *pmcid)
2471 char *r, *spec_copy;
2472 const char *ctrname;
2473 const struct pmc_event_descr *ev;
2474 const struct pmc_event_alias *alias;
2475 struct pmc_op_pmcallocate pmc_config;
2476 const struct pmc_class_descr *pcd;
2481 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS &&
2482 mode != PMC_MODE_SC && mode != PMC_MODE_TC) {
2487 /* replace an event alias with the canonical event specifier */
2488 if (pmc_mdep_event_aliases)
2489 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++)
2490 if (!strcasecmp(ctrspec, alias->pm_alias)) {
2491 spec_copy = strdup(alias->pm_spec);
2495 if (spec_copy == NULL)
2496 spec_copy = strdup(ctrspec);
2499 ctrname = strsep(&r, ",");
2502 * If a explicit class prefix was given by the user, restrict the
2503 * search for the event to the specified PMC class.
2506 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) {
2507 pcd = pmc_class_table[n];
2508 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) &&
2509 strncasecmp(ctrname, pcd->pm_evc_name,
2510 pcd->pm_evc_name_size) == 0) {
2511 if ((ev = pmc_match_event_class(ctrname +
2512 pcd->pm_evc_name_size, pcd)) == NULL) {
2521 * Otherwise, search for this event in all compatible PMC
2524 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) {
2525 pcd = pmc_class_table[n];
2526 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class))
2527 ev = pmc_match_event_class(ctrname, pcd);
2535 bzero(&pmc_config, sizeof(pmc_config));
2536 pmc_config.pm_ev = ev->pm_ev_code;
2537 pmc_config.pm_class = pcd->pm_evc_class;
2538 pmc_config.pm_cpu = cpu;
2539 pmc_config.pm_mode = mode;
2540 pmc_config.pm_flags = flags;
2542 if (PMC_IS_SAMPLING_MODE(mode))
2543 pmc_config.pm_caps |= PMC_CAP_INTERRUPT;
2545 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) {
2550 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0)
2553 *pmcid = pmc_config.pm_pmcid;
2565 pmc_attach(pmc_id_t pmc, pid_t pid)
2567 struct pmc_op_pmcattach pmc_attach_args;
2569 pmc_attach_args.pm_pmc = pmc;
2570 pmc_attach_args.pm_pid = pid;
2572 return (PMC_CALL(PMCATTACH, &pmc_attach_args));
2576 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps)
2581 cl = PMC_ID_TO_CLASS(pmcid);
2582 for (i = 0; i < cpu_info.pm_nclass; i++)
2583 if (cpu_info.pm_classes[i].pm_class == cl) {
2584 *caps = cpu_info.pm_classes[i].pm_caps;
2592 pmc_configure_logfile(int fd)
2594 struct pmc_op_configurelog cla;
2597 if (PMC_CALL(CONFIGURELOG, &cla) < 0)
2603 pmc_cpuinfo(const struct pmc_cpuinfo **pci)
2605 if (pmc_syscall == -1) {
2615 pmc_detach(pmc_id_t pmc, pid_t pid)
2617 struct pmc_op_pmcattach pmc_detach_args;
2619 pmc_detach_args.pm_pmc = pmc;
2620 pmc_detach_args.pm_pid = pid;
2621 return (PMC_CALL(PMCDETACH, &pmc_detach_args));
2625 pmc_disable(int cpu, int pmc)
2627 struct pmc_op_pmcadmin ssa;
2631 ssa.pm_state = PMC_STATE_DISABLED;
2632 return (PMC_CALL(PMCADMIN, &ssa));
2636 pmc_enable(int cpu, int pmc)
2638 struct pmc_op_pmcadmin ssa;
2642 ssa.pm_state = PMC_STATE_FREE;
2643 return (PMC_CALL(PMCADMIN, &ssa));
2647 * Return a list of events known to a given PMC class. 'cl' is the
2648 * PMC class identifier, 'eventnames' is the returned list of 'const
2649 * char *' pointers pointing to the names of the events. 'nevents' is
2650 * the number of event name pointers returned.
2652 * The space for 'eventnames' is allocated using malloc(3). The caller
2653 * is responsible for freeing this space when done.
2656 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
2661 const struct pmc_event_descr *ev;
2666 ev = iaf_event_table;
2667 count = PMC_EVENT_TABLE_SIZE(iaf);
2671 * Return the most appropriate set of event name
2672 * spellings for the current CPU.
2674 switch (cpu_info.pm_cputype) {
2676 case PMC_CPU_INTEL_ATOM:
2677 ev = atom_event_table;
2678 count = PMC_EVENT_TABLE_SIZE(atom);
2680 case PMC_CPU_INTEL_CORE:
2681 ev = core_event_table;
2682 count = PMC_EVENT_TABLE_SIZE(core);
2684 case PMC_CPU_INTEL_CORE2:
2685 case PMC_CPU_INTEL_CORE2EXTREME:
2686 ev = core2_event_table;
2687 count = PMC_EVENT_TABLE_SIZE(core2);
2689 case PMC_CPU_INTEL_COREI7:
2690 ev = corei7_event_table;
2691 count = PMC_EVENT_TABLE_SIZE(corei7);
2693 case PMC_CPU_INTEL_IVYBRIDGE:
2694 ev = ivybridge_event_table;
2695 count = PMC_EVENT_TABLE_SIZE(ivybridge);
2697 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
2698 ev = ivybridge_xeon_event_table;
2699 count = PMC_EVENT_TABLE_SIZE(ivybridge_xeon);
2701 case PMC_CPU_INTEL_SANDYBRIDGE:
2702 ev = sandybridge_event_table;
2703 count = PMC_EVENT_TABLE_SIZE(sandybridge);
2705 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
2706 ev = sandybridge_xeon_event_table;
2707 count = PMC_EVENT_TABLE_SIZE(sandybridge_xeon);
2709 case PMC_CPU_INTEL_WESTMERE:
2710 ev = westmere_event_table;
2711 count = PMC_EVENT_TABLE_SIZE(westmere);
2716 ev = ucf_event_table;
2717 count = PMC_EVENT_TABLE_SIZE(ucf);
2721 * Return the most appropriate set of event name
2722 * spellings for the current CPU.
2724 switch (cpu_info.pm_cputype) {
2726 case PMC_CPU_INTEL_COREI7:
2727 ev = corei7uc_event_table;
2728 count = PMC_EVENT_TABLE_SIZE(corei7uc);
2730 case PMC_CPU_INTEL_SANDYBRIDGE:
2731 ev = sandybridgeuc_event_table;
2732 count = PMC_EVENT_TABLE_SIZE(sandybridgeuc);
2734 case PMC_CPU_INTEL_WESTMERE:
2735 ev = westmereuc_event_table;
2736 count = PMC_EVENT_TABLE_SIZE(westmereuc);
2741 ev = tsc_event_table;
2742 count = PMC_EVENT_TABLE_SIZE(tsc);
2745 ev = k7_event_table;
2746 count = PMC_EVENT_TABLE_SIZE(k7);
2749 ev = k8_event_table;
2750 count = PMC_EVENT_TABLE_SIZE(k8);
2753 ev = p4_event_table;
2754 count = PMC_EVENT_TABLE_SIZE(p4);
2757 ev = p5_event_table;
2758 count = PMC_EVENT_TABLE_SIZE(p5);
2761 ev = p6_event_table;
2762 count = PMC_EVENT_TABLE_SIZE(p6);
2764 case PMC_CLASS_XSCALE:
2765 ev = xscale_event_table;
2766 count = PMC_EVENT_TABLE_SIZE(xscale);
2768 case PMC_CLASS_MIPS24K:
2769 ev = mips24k_event_table;
2770 count = PMC_EVENT_TABLE_SIZE(mips24k);
2772 case PMC_CLASS_OCTEON:
2773 ev = octeon_event_table;
2774 count = PMC_EVENT_TABLE_SIZE(octeon);
2776 case PMC_CLASS_PPC7450:
2777 ev = ppc7450_event_table;
2778 count = PMC_EVENT_TABLE_SIZE(ppc7450);
2780 case PMC_CLASS_SOFT:
2781 ev = soft_event_table;
2782 count = soft_event_info.pm_nevent;
2789 if ((names = malloc(count * sizeof(const char *))) == NULL)
2792 *eventnames = names;
2795 for (;count--; ev++, names++)
2796 *names = ev->pm_ev_name;
2802 pmc_flush_logfile(void)
2804 return (PMC_CALL(FLUSHLOG,0));
2808 pmc_close_logfile(void)
2810 return (PMC_CALL(CLOSELOG,0));
2814 pmc_get_driver_stats(struct pmc_driverstats *ds)
2816 struct pmc_op_getdriverstats gms;
2818 if (PMC_CALL(GETDRIVERSTATS, &gms) < 0)
2821 /* copy out fields in the current userland<->library interface */
2822 ds->pm_intr_ignored = gms.pm_intr_ignored;
2823 ds->pm_intr_processed = gms.pm_intr_processed;
2824 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull;
2825 ds->pm_syscalls = gms.pm_syscalls;
2826 ds->pm_syscall_errors = gms.pm_syscall_errors;
2827 ds->pm_buffer_requests = gms.pm_buffer_requests;
2828 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed;
2829 ds->pm_log_sweeps = gms.pm_log_sweeps;
2834 pmc_get_msr(pmc_id_t pmc, uint32_t *msr)
2836 struct pmc_op_getmsr gm;
2839 if (PMC_CALL(PMCGETMSR, &gm) < 0)
2848 int error, pmc_mod_id;
2850 uint32_t abi_version;
2851 struct module_stat pmc_modstat;
2852 struct pmc_op_getcpuinfo op_cpu_info;
2853 #if defined(__amd64__) || defined(__i386__)
2854 int cpu_has_iaf_counters;
2858 if (pmc_syscall != -1) /* already inited */
2861 /* retrieve the system call number from the KLD */
2862 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0)
2865 pmc_modstat.version = sizeof(struct module_stat);
2866 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0)
2869 pmc_syscall = pmc_modstat.data.intval;
2871 /* check the kernel module's ABI against our compiled-in version */
2872 abi_version = PMC_VERSION;
2873 if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0)
2874 return (pmc_syscall = -1);
2876 /* ignore patch & minor numbers for the comparision */
2877 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) {
2878 errno = EPROGMISMATCH;
2879 return (pmc_syscall = -1);
2882 if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0)
2883 return (pmc_syscall = -1);
2885 cpu_info.pm_cputype = op_cpu_info.pm_cputype;
2886 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu;
2887 cpu_info.pm_npmc = op_cpu_info.pm_npmc;
2888 cpu_info.pm_nclass = op_cpu_info.pm_nclass;
2889 for (n = 0; n < cpu_info.pm_nclass; n++)
2890 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n];
2892 pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE *
2893 sizeof(struct pmc_class_descr *));
2895 if (pmc_class_table == NULL)
2898 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++)
2899 pmc_class_table[n] = NULL;
2902 * Get soft events list.
2904 soft_event_info.pm_class = PMC_CLASS_SOFT;
2905 if (PMC_CALL(GETDYNEVENTINFO, &soft_event_info) < 0)
2906 return (pmc_syscall = -1);
2908 /* Map soft events to static list. */
2909 for (n = 0; n < soft_event_info.pm_nevent; n++) {
2910 soft_event_table[n].pm_ev_name =
2911 soft_event_info.pm_events[n].pm_ev_name;
2912 soft_event_table[n].pm_ev_code =
2913 soft_event_info.pm_events[n].pm_ev_code;
2915 soft_class_table_descr.pm_evc_event_table_size = \
2916 soft_event_info.pm_nevent;
2917 soft_class_table_descr.pm_evc_event_table = \
2921 * Fill in the class table.
2925 /* Fill soft events information. */
2926 pmc_class_table[n++] = &soft_class_table_descr;
2927 #if defined(__amd64__) || defined(__i386__)
2928 if (cpu_info.pm_cputype != PMC_CPU_GENERIC)
2929 pmc_class_table[n++] = &tsc_class_table_descr;
2932 * Check if this CPU has fixed function counters.
2934 cpu_has_iaf_counters = 0;
2935 for (t = 0; t < cpu_info.pm_nclass; t++)
2936 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF &&
2937 cpu_info.pm_classes[t].pm_num > 0)
2938 cpu_has_iaf_counters = 1;
2941 #define PMC_MDEP_INIT(C) do { \
2942 pmc_mdep_event_aliases = C##_aliases; \
2943 pmc_mdep_class_list = C##_pmc_classes; \
2944 pmc_mdep_class_list_size = \
2945 PMC_TABLE_SIZE(C##_pmc_classes); \
2948 #define PMC_MDEP_INIT_INTEL_V2(C) do { \
2950 pmc_class_table[n++] = &iaf_class_table_descr; \
2951 if (!cpu_has_iaf_counters) \
2952 pmc_mdep_event_aliases = \
2953 C##_aliases_without_iaf; \
2954 pmc_class_table[n] = &C##_class_table_descr; \
2957 /* Configure the event name parser. */
2958 switch (cpu_info.pm_cputype) {
2959 #if defined(__i386__)
2960 case PMC_CPU_AMD_K7:
2962 pmc_class_table[n] = &k7_class_table_descr;
2964 case PMC_CPU_INTEL_P5:
2966 pmc_class_table[n] = &p5_class_table_descr;
2968 case PMC_CPU_INTEL_P6: /* P6 ... Pentium M CPUs have */
2969 case PMC_CPU_INTEL_PII: /* similar PMCs. */
2970 case PMC_CPU_INTEL_PIII:
2971 case PMC_CPU_INTEL_PM:
2973 pmc_class_table[n] = &p6_class_table_descr;
2976 #if defined(__amd64__) || defined(__i386__)
2977 case PMC_CPU_AMD_K8:
2979 pmc_class_table[n] = &k8_class_table_descr;
2981 case PMC_CPU_INTEL_ATOM:
2982 PMC_MDEP_INIT_INTEL_V2(atom);
2984 case PMC_CPU_INTEL_CORE:
2985 PMC_MDEP_INIT(core);
2986 pmc_class_table[n] = &core_class_table_descr;
2988 case PMC_CPU_INTEL_CORE2:
2989 case PMC_CPU_INTEL_CORE2EXTREME:
2990 PMC_MDEP_INIT_INTEL_V2(core2);
2992 case PMC_CPU_INTEL_COREI7:
2993 pmc_class_table[n++] = &ucf_class_table_descr;
2994 pmc_class_table[n++] = &corei7uc_class_table_descr;
2995 PMC_MDEP_INIT_INTEL_V2(corei7);
2997 case PMC_CPU_INTEL_IVYBRIDGE:
2998 PMC_MDEP_INIT_INTEL_V2(ivybridge);
3000 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
3001 PMC_MDEP_INIT_INTEL_V2(ivybridge_xeon);
3003 case PMC_CPU_INTEL_SANDYBRIDGE:
3004 pmc_class_table[n++] = &ucf_class_table_descr;
3005 pmc_class_table[n++] = &sandybridgeuc_class_table_descr;
3006 PMC_MDEP_INIT_INTEL_V2(sandybridge);
3008 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
3009 PMC_MDEP_INIT_INTEL_V2(sandybridge_xeon);
3011 case PMC_CPU_INTEL_WESTMERE:
3012 pmc_class_table[n++] = &ucf_class_table_descr;
3013 pmc_class_table[n++] = &westmereuc_class_table_descr;
3014 PMC_MDEP_INIT_INTEL_V2(westmere);
3016 case PMC_CPU_INTEL_PIV:
3018 pmc_class_table[n] = &p4_class_table_descr;
3021 case PMC_CPU_GENERIC:
3022 PMC_MDEP_INIT(generic);
3024 #if defined(__XSCALE__)
3025 case PMC_CPU_INTEL_XSCALE:
3026 PMC_MDEP_INIT(xscale);
3027 pmc_class_table[n] = &xscale_class_table_descr;
3030 #if defined(__mips__)
3031 case PMC_CPU_MIPS_24K:
3032 PMC_MDEP_INIT(mips24k);
3033 pmc_class_table[n] = &mips24k_class_table_descr;
3035 case PMC_CPU_MIPS_OCTEON:
3036 PMC_MDEP_INIT(octeon);
3037 pmc_class_table[n] = &octeon_class_table_descr;
3039 #endif /* __mips__ */
3040 #if defined(__powerpc__)
3041 case PMC_CPU_PPC_7450:
3042 PMC_MDEP_INIT(ppc7450);
3043 pmc_class_table[n] = &ppc7450_class_table_descr;
3048 * Some kind of CPU this version of the library knows nothing
3049 * about. This shouldn't happen since the abi version check
3050 * should have caught this.
3053 return (pmc_syscall = -1);
3060 pmc_name_of_capability(enum pmc_caps cap)
3065 * 'cap' should have a single bit set and should be in
3068 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST ||
3069 cap > PMC_CAP_LAST) {
3075 return (pmc_capability_names[i - 1]);
3079 pmc_name_of_class(enum pmc_class pc)
3081 if ((int) pc >= PMC_CLASS_FIRST &&
3082 pc <= PMC_CLASS_LAST)
3083 return (pmc_class_names[pc]);
3090 pmc_name_of_cputype(enum pmc_cputype cp)
3094 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++)
3095 if (cp == pmc_cputype_names[n].pm_cputype)
3096 return (pmc_cputype_names[n].pm_name);
3103 pmc_name_of_disposition(enum pmc_disp pd)
3105 if ((int) pd >= PMC_DISP_FIRST &&
3106 pd <= PMC_DISP_LAST)
3107 return (pmc_disposition_names[pd]);
3114 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
3116 const struct pmc_event_descr *ev, *evfence;
3118 ev = evfence = NULL;
3119 if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) {
3120 ev = iaf_event_table;
3121 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf);
3122 } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) {
3124 case PMC_CPU_INTEL_ATOM:
3125 ev = atom_event_table;
3126 evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom);
3128 case PMC_CPU_INTEL_CORE:
3129 ev = core_event_table;
3130 evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core);
3132 case PMC_CPU_INTEL_CORE2:
3133 case PMC_CPU_INTEL_CORE2EXTREME:
3134 ev = core2_event_table;
3135 evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2);
3137 case PMC_CPU_INTEL_COREI7:
3138 ev = corei7_event_table;
3139 evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7);
3141 case PMC_CPU_INTEL_IVYBRIDGE:
3142 ev = ivybridge_event_table;
3143 evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge);
3145 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
3146 ev = ivybridge_xeon_event_table;
3147 evfence = ivybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(ivybridge_xeon);
3149 case PMC_CPU_INTEL_SANDYBRIDGE:
3150 ev = sandybridge_event_table;
3151 evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge);
3153 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
3154 ev = sandybridge_xeon_event_table;
3155 evfence = sandybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(sandybridge_xeon);
3157 case PMC_CPU_INTEL_WESTMERE:
3158 ev = westmere_event_table;
3159 evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere);
3161 default: /* Unknown CPU type. */
3164 } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) {
3165 ev = ucf_event_table;
3166 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf);
3167 } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) {
3169 case PMC_CPU_INTEL_COREI7:
3170 ev = corei7uc_event_table;
3171 evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc);
3173 case PMC_CPU_INTEL_SANDYBRIDGE:
3174 ev = sandybridgeuc_event_table;
3175 evfence = sandybridgeuc_event_table + PMC_EVENT_TABLE_SIZE(sandybridgeuc);
3177 case PMC_CPU_INTEL_WESTMERE:
3178 ev = westmereuc_event_table;
3179 evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc);
3181 default: /* Unknown CPU type. */
3184 } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) {
3185 ev = k7_event_table;
3186 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7);
3187 } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
3188 ev = k8_event_table;
3189 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
3190 } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) {
3191 ev = p4_event_table;
3192 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4);
3193 } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) {
3194 ev = p5_event_table;
3195 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5);
3196 } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) {
3197 ev = p6_event_table;
3198 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6);
3199 } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) {
3200 ev = xscale_event_table;
3201 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale);
3202 } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) {
3203 ev = mips24k_event_table;
3204 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k);
3205 } else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) {
3206 ev = octeon_event_table;
3207 evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon);
3208 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) {
3209 ev = ppc7450_event_table;
3210 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450);
3211 } else if (pe == PMC_EV_TSC_TSC) {
3212 ev = tsc_event_table;
3213 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc);
3214 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) {
3215 ev = soft_event_table;
3216 evfence = soft_event_table + soft_event_info.pm_nevent;
3219 for (; ev != evfence; ev++)
3220 if (pe == ev->pm_ev_code)
3221 return (ev->pm_ev_name);
3227 pmc_name_of_event(enum pmc_event pe)
3231 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL)
3239 pmc_name_of_mode(enum pmc_mode pm)
3241 if ((int) pm >= PMC_MODE_FIRST &&
3242 pm <= PMC_MODE_LAST)
3243 return (pmc_mode_names[pm]);
3250 pmc_name_of_state(enum pmc_state ps)
3252 if ((int) ps >= PMC_STATE_FIRST &&
3253 ps <= PMC_STATE_LAST)
3254 return (pmc_state_names[ps]);
3263 if (pmc_syscall == -1) {
3268 return (cpu_info.pm_ncpu);
3274 if (pmc_syscall == -1) {
3279 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) {
3284 return (cpu_info.pm_npmc);
3288 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci)
3291 struct pmc_op_getpmcinfo *pmci;
3293 if ((npmc = pmc_npmc(cpu)) < 0)
3296 nbytes = sizeof(struct pmc_op_getpmcinfo) +
3297 npmc * sizeof(struct pmc_info);
3299 if ((pmci = calloc(1, nbytes)) == NULL)
3304 if (PMC_CALL(GETPMCINFO, pmci) < 0) {
3309 /* kernel<->library, library<->userland interfaces are identical */
3310 *ppmci = (struct pmc_pmcinfo *) pmci;
3315 pmc_read(pmc_id_t pmc, pmc_value_t *value)
3317 struct pmc_op_pmcrw pmc_read_op;
3319 pmc_read_op.pm_pmcid = pmc;
3320 pmc_read_op.pm_flags = PMC_F_OLDVALUE;
3321 pmc_read_op.pm_value = -1;
3323 if (PMC_CALL(PMCRW, &pmc_read_op) < 0)
3326 *value = pmc_read_op.pm_value;
3331 pmc_release(pmc_id_t pmc)
3333 struct pmc_op_simple pmc_release_args;
3335 pmc_release_args.pm_pmcid = pmc;
3336 return (PMC_CALL(PMCRELEASE, &pmc_release_args));
3340 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep)
3342 struct pmc_op_pmcrw pmc_rw_op;
3344 pmc_rw_op.pm_pmcid = pmc;
3345 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE;
3346 pmc_rw_op.pm_value = newvalue;
3348 if (PMC_CALL(PMCRW, &pmc_rw_op) < 0)
3351 *oldvaluep = pmc_rw_op.pm_value;
3356 pmc_set(pmc_id_t pmc, pmc_value_t value)
3358 struct pmc_op_pmcsetcount sc;
3361 sc.pm_count = value;
3363 if (PMC_CALL(PMCSETCOUNT, &sc) < 0)
3369 pmc_start(pmc_id_t pmc)
3371 struct pmc_op_simple pmc_start_args;
3373 pmc_start_args.pm_pmcid = pmc;
3374 return (PMC_CALL(PMCSTART, &pmc_start_args));
3378 pmc_stop(pmc_id_t pmc)
3380 struct pmc_op_simple pmc_stop_args;
3382 pmc_stop_args.pm_pmcid = pmc;
3383 return (PMC_CALL(PMCSTOP, &pmc_stop_args));
3387 pmc_width(pmc_id_t pmcid, uint32_t *width)
3392 cl = PMC_ID_TO_CLASS(pmcid);
3393 for (i = 0; i < cpu_info.pm_nclass; i++)
3394 if (cpu_info.pm_classes[i].pm_class == cl) {
3395 *width = cpu_info.pm_classes[i].pm_width;
3403 pmc_write(pmc_id_t pmc, pmc_value_t value)
3405 struct pmc_op_pmcrw pmc_write_op;
3407 pmc_write_op.pm_pmcid = pmc;
3408 pmc_write_op.pm_flags = PMC_F_NEWVALUE;
3409 pmc_write_op.pm_value = value;
3410 return (PMC_CALL(PMCRW, &pmc_write_op));
3414 pmc_writelog(uint32_t userdata)
3416 struct pmc_op_writelog wl;
3418 wl.pm_userdata = userdata;
3419 return (PMC_CALL(WRITELOG, &wl));