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31 .Nd library for accessing hardware performance monitoring counters
39 provides a programming interface that allows applications to use
40 hardware performance counters to gather performance data about
41 specific processes or for the system as a whole.
42 The library is implemented using the lower-level facilities offered by
47 Performance monitoring counters (PMCs) are represented by the library
48 using a software abstraction.
51 PMCs can have one two scopes:
55 These PMCs measure events in a whole-system manner, i.e., independent
56 of the currently executing thread.
57 System scope PMCs are allocated on specific CPUs and do not
59 Non-privileged process are allowed to allocate system scope PMCs if the
62 .Va security.bsd.unprivileged_syspmcs
66 These PMCs only measure hardware events when the processes they are
67 attached to are executing on a CPU.
68 In an SMP system, process scope PMCs migrate between CPUs along with
69 their target processes.
72 Orthogonal to PMC scope, PMCs may be allocated in one of two
76 Counting PMCs measure events according to their scope
78 The application needs to explicitly read these counters
79 to retrieve their value.
81 Sampling PMCs cause the CPU to be periodically interrupted
82 and information about its state of execution to be collected.
83 Sampling PMCs are used to profile specific processes and kernel
84 threads or to profile the system as a whole.
87 The scope and operational mode for a software PMC are specified at
89 An application is allowed to allocate multiple PMCs subject
90 to availability of hardware resources.
92 The library uses human-readable strings to name the event being
94 The syntax used for specifying a hardware event along with additional
95 event specific qualifiers (if any) is described in detail in section
96 .Sx "EVENT SPECIFIERS"
99 PMCs are associated with the process that allocated them and
100 will be automatically reclaimed by the system when the process exits.
101 Additionally, process-scope PMCs have to be attached to one or more
102 target processes before they can perform measurements.
103 A process-scope PMC may be attached to those target processes
104 that its owner process would otherwise be permitted to debug.
105 An owner process may attach PMCs to itself allowing
106 it to measure its own behavior.
107 Additionally, on some machine architectures, such self-attached PMCs
108 may be read cheaply using specialized instructions supported by the
111 Certain kinds of PMCs require that a log file be configured before
116 System scope sampling PMCs.
118 Process scope sampling PMCs.
120 Process scope counting PMCs that have been configured to report PMC
121 readings on process context switches or process exits.
123 Upto one log file may be configured per owner process.
124 Events logged to a log file may be subsequently analyzed using the
128 The CPUs known to the PMC library are named by the
129 .Vt "enum pmc_cputype"
131 Supported CPUs include:
132 .Bl -tag -width PMC_CPU_INTEL_PIII -compact
147 .It PMC_CPU_INTEL_PII
148 .Tn "Intel Pentium II"
150 .It PMC_CPU_INTEL_PIII
151 .Tn "Intel Pentium III"
154 .Tn "Intel Pentium M"
156 .It PMC_CPU_INTEL_PIV
157 .Tn "Intel Pentium 4"
161 PMC supported by this library are named by the
164 Supported PMC kinds include:
165 .Bl -tag -width PMC_CLASS_TSC -compact
167 The timestamp counter on i386 and amd64 architecture CPUs.
169 Programmable hardware counters present in
173 Programmable hardware counters present in
177 Programmable hardware counters present in
182 Programmable hardware counters present in
192 Programmable hardware counters present in
193 .Tn "Intel Pentium 4"
198 Capabilities of performance monitoring hardware are denoted using
202 Supported capabilities include:
203 .Bl -tag -width "PMC_CAP_INTERRUPT" -compact
205 The ability to count negated to asserted transitions of the hardware
206 conditions being probed for.
207 .It PMC_CAP_INTERRUPT
208 The ability to interrupt the CPU.
210 The ability to invert the sense of the hardware conditions being
213 PMC hardware allows the CPU to read performance counters.
214 .It PMC_CAP_QUALIFIER
215 The hardware allows monitored to be further qualified in some
216 system dependent way.
218 The ability to restrict counting of hardware events to when the CPU is
219 running privileged code.
220 .It PMC_CAP_THRESHOLD
221 The ability to ignore simultaneous hardware events below a
222 programmable threshold.
224 The ability to restrict counting of hardware events to those when the
225 CPU is running unprivileged code.
227 PMC hardware allows CPUs write to counters.
229 .Ss Functional Grouping
230 This section contains a brief overview of the available functionality
232 Each function listed here is described further in its own manual page.
233 .Bl -tag -width indent
236 .It Fn pmc_disable , Fn pmc_enable
237 Administratively disable (enable) specific performance monitoring
239 Counters that are disabled will not be available to applications to
242 .It "Convenience Functions"
244 .It Fn pmc_event_names_of_class
245 Returns a list of event names supported by a given PMC type.
246 .It Fn pmc_name_of_capability
249 flag to a human-readable string.
250 .It Fn pmc_name_of_class
253 constant to a human-readable string.
254 .It Fn pmc_name_of_cputype
255 Return a human-readable name for a CPU type.
256 .It Fn pmc_name_of_disposition
257 Return a human-readable string describing a PMC's disposition.
258 .It Fn pmc_name_of_event
259 Convert a numeric event code to a human-readable string.
260 .It Fn pmc_name_of_mode
263 constant to a human-readable name.
264 .It Fn pmc_name_of_state
265 Return a human-readable string describing a PMC's current state.
267 .It "Library Initialization"
270 Initialize the library.
271 This function must be called before any other library function.
273 .It "Log File Handling"
275 .It Fn pmc_configure_logfile
276 Configure a log file for
278 to write logged events to.
279 .It Fn pmc_flush_logfile
280 Flush all pending log data in
284 Append arbitrary user data to the current log file.
288 .It Fn pmc_allocate , Fn pmc_release
289 Allocate (free) a PMC.
290 .It Fn pmc_attach , Fn pmc_detach
291 Attach (detach) a process scope PMC to a target.
292 .It Fn pmc_read , Fn pmc_write , Fn pmc_rw
293 Read (write) a value from (to) a PMC.
294 .It Fn pmc_start , Fn pmc_stop
295 Start (stop) a software PMC.
297 Set the reload value for a sampling PMC.
301 .It Fn pmc_capabilities
302 Retrieve the capabilities for a given PMC.
304 Retrieve information about the CPUs and PMC hardware present in the
306 .It Fn pmc_get_driver_stats
307 Retrieve statistics maintained by
310 Determine the number of CPUs in the system.
312 Return the number of hardware PMCs present in a given CPU.
314 Return information about the state of a given CPU's PMCs.
316 Determine the width of a hardware counter in bits.
318 .It "x86 Architecture Specific API"
321 Returns the processor model specific register number
324 Applications may then use the x86
326 instruction to directly read the contents of the PMC.
329 .Ss Signal Handling Requirements
330 Applications using PMCs are required to handle the following signals:
331 .Bl -tag -width ".Dv SIGBUS"
335 module is unloaded using
337 processes that have PMCs allocated to them will be sent a
343 driver will send a PMC owning process a
348 If any process-mode PMC allocated by it loses all its
351 If the driver encounters an error when writing log data to a
353 This error may be retrieved by a subsequent call to
354 .Fn pmc_flush_logfile .
357 .Ss Typical Program Flow
360 An application would first invoke function
362 to allow the library to initialize itself.
364 Signal handling would then be set up.
366 Next the application would allocate the PMCs it desires using function
369 Initial values for PMCs may be set using function
372 If a log file is necessary for the PMCs to work, it would
373 be configured using function
374 .Fn pmc_configure_logfile .
376 Process scope PMCs would then be attached to their target processes
380 The PMCs would then be started using function
383 Once started, the values of counting PMCs may be read using function
385 For PMCs that write events to the log file, this logged data would be
386 read and parsed using the
390 PMCs are stopped using function
392 and process scope PMCs are detached from their targets using
396 Before the process exits, its may release its PMCs using function
398 Any configured log file may be closed using function
399 .Fn pmc_configure_logfile .
402 Event specifiers are strings comprising of an event name, followed by
403 optional parameters modifying the semantics of the hardware event
405 Event names are PMC architecture dependent, but the PMC library defines
406 machine independent aliases for commonly used events.
407 .Ss Event Name Aliases
408 Event name aliases are CPU architecture independent names for commonly
410 The following aliases are known to this version of the
413 .Bl -tag -width indent
415 Measure the number of branches retired.
416 .It Li branch-mispredicts
417 Measure the number of retired branches that were mispredicted.
419 Measure processor cycles.
420 This event is implemented using the processor's Time Stamp Counter
423 Measure the number of data cache misses.
425 Measure the number of instruction cache misses.
427 Measure the number of instructions retired.
429 Measure the number of interrupts seen.
430 .It Li unhalted-cycles
431 Measure the number of cycles the processor is not in a halted
434 .Ss Time Stamp Counter (TSC)
435 The timestamp counter is a monotonically non-decreasing counter that
436 counts processor cycles.
438 In the i386 architecture, this counter may
439 be selected by requesting an event with event specifier
443 event does not support any further qualifiers.
444 It can only be allocated in system-wide counting mode,
445 and is a read-only counter.
446 Multiple processes are allowed to allocate the TSC.
447 Once allocated, it may be read using the
449 function, or by using the RDTSC instruction.
451 These PMCs are present in the
453 series of CPUs and are documented in:
455 .%B "AMD Athlon Processor x86 Code Optimization Guide"
456 .%N "Publication No. 22007"
458 .%Q "Advanced Micro Devices, Inc."
461 Event specifiers for AMD K7 PMCs can have the following optional
463 .Bl -tag -width indent
464 .It Li count= Ns Ar value
465 Configure the counter to increment only if the number of configured
466 events measured in a cycle is greater than or equal to
469 Configure the counter to only count negated-to-asserted transitions
470 of the conditions expressed by the other qualifiers.
471 In other words, the counter will increment only once whenever a given
472 condition becomes true, irrespective of the number of clocks during
473 which the condition remains true.
475 Invert the sense of comparision when the
477 qualifier is present, making the counter to increment when the
478 number of events per cycle is less than the value specified by
483 Configure the PMC to count events happening at privilege level 0.
484 .It Li unitmask= Ns Ar mask
485 This qualifier is used to further qualify a select few events,
486 .Dq Li k7-dc-refills-from-l2 ,
487 .Dq Li k7-dc-refills-from-system
489 .Dq Li k7-dc-writebacks .
492 is a string of the following characters optionally separated by
496 .Bl -tag -width indent -compact
498 Count operations for lines in the
502 Count operations for lines in the
506 Count operations for lines in the
510 Count operations for lines in the
514 Count operations for lines in the
521 qualifier is specified, the default is to count events for caches
522 lines in any of the above states.
524 Configure the PMC to count events occurring at privilege levels 1, 2
532 qualifiers were specified, the default is to enable both.
534 The event specifiers supported on AMD K7 PMCs are:
535 .Bl -tag -width indent
536 .It Li k7-dc-accesses
537 Count data cache accesses.
539 Count data cache misses.
540 .It Li k7-dc-refills-from-l2 Op Li ,unitmask= Ns Ar mask
541 Count data cache refills from L2 cache.
542 This event may be further qualified using the
545 .It Li k7-dc-refills-from-system Op Li ,unitmask= Ns Ar mask
546 Count data cache refills from system memory.
547 This event may be further qualified using the
550 .It Li k7-dc-writebacks Op Li ,unitmask= Ns Ar mask
551 Count data cache writebacks.
552 This event may be further qualified using the
555 .It Li k7-l1-dtlb-miss-and-l2-dtlb-hits
556 Count L1 DTLB misses and L2 DTLB hits.
557 .It Li k7-l1-and-l2-dtlb-misses
558 Count L1 and L2 DTLB misses.
559 .It Li k7-misaligned-references
560 Count misaligned data references.
562 Count instruction cache fetches.
564 Count instruction cache misses.
565 .It Li k7-l1-itlb-misses
566 Count L1 ITLB misses that are L2 ITLB hits.
567 .It Li k7-l1-l2-itlb-misses
568 Count L1 (and L2) ITLB misses.
569 .It Li k7-retired-instructions
570 Count all retired instructions.
571 .It Li k7-retired-ops
573 .It Li k7-retired-branches
574 Count all retired branches (conditional, unconditional, exceptions
576 .It Li k7-retired-branches-mispredicted
577 Count all misprediced retired branches.
578 .It Li k7-retired-taken-branches
579 Count retired taken branches.
580 .It Li k7-retired-taken-branches-mispredicted
581 Count mispredicted taken branches that were retired.
582 .It Li k7-retired-far-control-transfers
583 Count retired far control transfers.
584 .It Li k7-retired-resync-branches
585 Count retired resync branches (non control transfer branches).
586 .It Li k7-interrupts-masked-cycles
587 Count the number of cycles when the processor's
590 .It Li k7-interrupts-masked-while-pending-cycles
591 Count the number of cycles interrupts were masked while pending due
595 .It Li k7-hardware-interrupts
596 Count the number of taken hardware interrupts.
599 These PMCs are present in the
604 They are documented in:
606 .%B "BIOS and Kernel Developer's Guide for the AMD Athlon(tm) 64 and AMD Opteron Processors"
607 .%N "Publication No. 26094"
609 .%Q "Advanced Micro Devices, Inc."
612 Event specifiers for AMD K8 PMCs can have the following optional
614 .Bl -tag -width indent
615 .It Li count= Ns Ar value
616 Configure the counter to increment only if the number of configured
617 events measured in a cycle is greater than or equal to
620 Configure the counter to only count negated-to-asserted transitions
621 of the conditions expressed by the other fields.
622 In other words, the counter will increment only once whenever a given
623 condition becomes true, irrespective of the number of clocks during
624 which the condition remains true.
626 Invert the sense of comparision when the
628 qualifier is present, making the counter to increment when the
629 number of events per cycle is less than the value specified by
633 .It Li mask= Ns Ar qualifier
634 Many event specifiers for AMD K8 PMCs need to be additionally
635 qualified using a mask qualifier.
636 These additional qualifiers are event-specific and are documented
637 along with their associated event specifiers below.
639 Configure the PMC to count events happening at privilege level 0.
641 Configure the PMC to count events occurring at privilege levels 1, 2
649 qualifiers were specified, the default is to enable both.
651 The event specifiers supported on AMD K8 PMCs are:
652 .Bl -tag -width indent
653 .It Li k8-bu-cpu-clk-unhalted
654 Count the number of clock cycles when the CPU is not in the HLT or
656 .It Li k8-bu-fill-request-l2-miss Op Li ,mask= Ns Ar qualifier
657 Count fill requests that missed in the L2 cache.
658 This event may be further qualified using
662 separated set of the following keywords:
664 .Bl -tag -width indent -compact
666 Count data cache fill requests.
668 Count instruction cache fill requests.
673 The default is to count all types of requests.
674 .It Li k8-bu-internal-l2-request Op Li ,mask= Ns Ar qualifier
675 Count internally generated requests to the L2 cache.
676 This event may be further qualified using
680 separated set of the following keywords:
682 .Bl -tag -width indent -compact
684 Count cancelled requests.
686 Count data cache fill requests.
688 Count instruction cache fill requests.
690 Count tag snoop requests.
695 The default is to count all types of requests.
697 Count data cache accesses including microcode scratchpad accesses.
698 .It Li k8-dc-copyback Op Li ,mask= Ns Ar qualifier
699 Count data cache copyback operations.
700 This event may be further qualified using
704 separated set of the following keywords:
706 .Bl -tag -width indent -compact
708 Count operations for lines in the
712 Count operations for lines in the
716 Count operations for lines in the
720 Count operations for lines in the
724 Count operations for lines in the
729 The default is to count operations for lines in all the
731 .It Li k8-dc-dcache-accesses-by-locks Op Li ,mask= Ns Ar qualifier
732 Count data cache accesses by lock instructions.
733 This event is only available on processors of revision C or later
735 This event may be further qualified using
739 separated set of the following keywords:
741 .Bl -tag -width indent -compact
743 Count data cache accesses by lock instructions.
745 Count data cache misses by lock instructions.
748 The default is to count all accesses.
749 .It Li k8-dc-dispatched-prefetch-instructions Op Li ,mask= Ns Ar qualifier
750 Count the number of dispatched prefetch instructions.
751 This event may be further qualified using
755 separated set of the following keywords:
757 .Bl -tag -width indent -compact
759 Count load operations.
761 Count non-temporal operations.
763 Count store operations.
766 The default is to count all operations.
767 .It Li k8-dc-l1-dtlb-miss-and-l2-dtlb-hit
768 Count L1 DTLB misses that are L2 DTLB hits.
769 .It Li k8-dc-l1-dtlb-miss-and-l2-dtlb-miss
770 Count L1 DTLB misses that are also misses in the L2 DTLB.
771 .It Li k8-dc-microarchitectural-early-cancel-of-an-access
772 Count microarchitectural early cancels of data cache accesses.
773 .It Li k8-dc-microarchitectural-late-cancel-of-an-access
774 Count microarchitectural late cancels of data cache accesses.
775 .It Li k8-dc-misaligned-data-reference
776 Count misaligned data references.
778 Count data cache misses.
779 .It Li k8-dc-one-bit-ecc-error Op Li ,mask= Ns Ar qualifier
780 Count one bit ECC errors found by the scrubber.
781 This event may be further qualified using
785 separated set of the following keywords:
787 .Bl -tag -width indent -compact
789 Count scrubber detected errors.
791 Count piggyback scrubber errors.
794 The default is to count both kinds of errors.
795 .It Li k8-dc-refill-from-l2 Op Li ,mask= Ns Ar qualifier
796 Count data cache refills from L2 cache.
797 This event may be further qualified using
801 separated set of the following keywords:
803 .Bl -tag -width indent -compact
805 Count operations for lines in the
809 Count operations for lines in the
813 Count operations for lines in the
817 Count operations for lines in the
821 Count operations for lines in the
826 The default is to count operations for lines in all the
828 .It Li k8-dc-refill-from-system Op Li ,mask= Ns Ar qualifier
829 Count data cache refills from system memory.
830 This event may be further qualified using
834 separated set of the following keywords:
836 .Bl -tag -width indent -compact
838 Count operations for lines in the
842 Count operations for lines in the
846 Count operations for lines in the
850 Count operations for lines in the
854 Count operations for lines in the
859 The default is to count operations for lines in all the
861 .It Li k8-fp-dispatched-fpu-ops Op Li ,mask= Ns Ar qualifier
862 Count the number of dispatched FPU ops.
863 This event is supported in revision B and later CPUs.
864 This event may be further qualified using
868 separated set of the following keywords:
870 .Bl -tag -width indent -compact
871 .It Li add-pipe-excluding-junk-ops
872 Count add pipe ops excluding junk ops.
873 .It Li add-pipe-junk-ops
874 Count junk ops in the add pipe.
875 .It Li multiply-pipe-excluding-junk-ops
876 Count multiply pipe ops excluding junk ops.
877 .It Li multiply-pipe-junk-ops
878 Count junk ops in the multiply pipe.
879 .It Li store-pipe-excluding-junk-ops
880 Count store pipe ops excluding junk ops
881 .It Li store-pipe-junk-ops
882 Count junk ops in the store pipe.
885 The default is to count all types of ops.
886 .It Li k8-fp-cycles-with-no-fpu-ops-retired
887 Count cycles when no FPU ops were retired.
888 This event is supported in revision B and later CPUs.
889 .It Li k8-fp-dispatched-fpu-fast-flag-ops
890 Count dispatched FPU ops that use the fast flag interface.
891 This event is supported in revision B and later CPUs.
892 .It Li k8-fr-decoder-empty
893 Count cycles when there was nothing to dispatch (i.e., the decoder
895 .It Li k8-fr-dispatch-stalls
896 Count all dispatch stalls.
897 .It Li k8-fr-dispatch-stall-for-segment-load
898 Count dispatch stalls for segment loads.
899 .It Li k8-fr-dispatch-stall-for-serialization
900 Count dispatch stalls for serialization.
901 .It Li k8-fr-dispatch-stall-from-branch-abort-to-retire
902 Count dispatch stalls from branch abort to retiral.
903 .It Li k8-fr-dispatch-stall-when-fpu-is-full
904 Count dispatch stalls when the FPU is full.
905 .It Li k8-fr-dispatch-stall-when-ls-is-full
906 Count dispatch stalls when the load/store unit is full.
907 .It Li k8-fr-dispatch-stall-when-reorder-buffer-is-full
908 Count dispatch stalls when the reorder buffer is full.
909 .It Li k8-fr-dispatch-stall-when-reservation-stations-are-full
910 Count dispatch stalls when reservation stations are full.
911 .It Li k8-fr-dispatch-stall-when-waiting-for-all-to-be-quiet
912 Count dispatch stalls when waiting for all to be quiet.
913 .\" XXX What does "waiting for all to be quiet" mean?
914 .It Li k8-fr-dispatch-stall-when-waiting-far-xfer-or-resync-branch-pending
915 Count dispatch stalls when a far control transfer or a resync branch
917 .It Li k8-fr-fpu-exceptions Op Li ,mask= Ns Ar qualifier
918 Count FPU exceptions.
919 This event is supported in revision B and later CPUs.
920 This event may be further qualified using
924 separated set of the following keywords:
926 .Bl -tag -width indent -compact
927 .It Li sse-and-x87-microtraps
928 Count SSE and x87 microtraps.
929 .It Li sse-reclass-microfaults
930 Count SSE reclass microfaults
931 .It Li sse-retype-microfaults
932 Count SSE retype microfaults
933 .It Li x87-reclass-microfaults
934 Count x87 reclass microfaults.
937 The default is to count all types of exceptions.
938 .It Li k8-fr-interrupts-masked-cycles
939 Count cycles when interrupts were masked (by CPU RFLAGS field IF was zero).
940 .It Li k8-fr-interrupts-masked-while-pending-cycles
941 Count cycles while interrupts were masked while pending (i.e., cycles
942 when INTR was asserted while CPU RFLAGS field IF was zero).
943 .It Li k8-fr-number-of-breakpoints-for-dr0
944 Count the number of breakpoints for DR0.
945 .It Li k8-fr-number-of-breakpoints-for-dr1
946 Count the number of breakpoints for DR1.
947 .It Li k8-fr-number-of-breakpoints-for-dr2
948 Count the number of breakpoints for DR2.
949 .It Li k8-fr-number-of-breakpoints-for-dr3
950 Count the number of breakpoints for DR3.
951 .It Li k8-fr-retired-branches
952 Count retired branches including exceptions and interrupts.
953 .It Li k8-fr-retired-branches-mispredicted
954 Count mispredicted retired branches.
955 .It Li k8-fr-retired-far-control-transfers
956 Count retired far control transfers (which are always mispredicted).
957 .It Li k8-fr-retired-fastpath-double-op-instructions Op Li ,mask= Ns Ar qualifier
958 Count retired fastpath double op instructions.
959 This event is supported in revision B and later CPUs.
960 This event may be further qualified using
964 separated set of the following keywords:
966 .Bl -tag -width indent -compact
968 Count instructions with the low op in position 0.
970 Count instructions with the low op in position 1.
972 Count instructions with the low op in position 2.
975 The default is to count all types of instructions.
976 .It Li k8-fr-retired-fpu-instructions Op Li ,mask= Ns Ar qualifier
977 Count retired FPU instructions.
978 This event is supported in revision B and later CPUs.
979 This event may be further qualified using
983 separated set of the following keywords:
985 .Bl -tag -width indent -compact
987 Count MMX and 3DNow!\& instructions.
988 .It Li packed-sse-sse2
989 Count packed SSE and SSE2 instructions.
990 .It Li scalar-sse-sse2
991 Count scalar SSE and SSE2 instructions
993 Count x87 instructions.
996 The default is to count all types of instructions.
997 .It Li k8-fr-retired-near-returns
998 Count retired near returns.
999 .It Li k8-fr-retired-near-returns-mispredicted
1000 Count mispredicted near returns.
1001 .It Li k8-fr-retired-resyncs
1002 Count retired resyncs (non-control transfer branches).
1003 .It Li k8-fr-retired-taken-hardware-interrupts
1004 Count retired taken hardware interrupts.
1005 .It Li k8-fr-retired-taken-branches
1006 Count retired taken branches.
1007 .It Li k8-fr-retired-taken-branches-mispredicted
1008 Count retired taken branches that were mispredicted.
1009 .It Li k8-fr-retired-taken-branches-mispredicted-by-addr-miscompare
1010 Count retired taken branches that were mispredicted only due to an
1012 .It Li k8-fr-retired-uops
1014 .It Li k8-fr-retired-x86-instructions
1015 Count retired x86 instructions including exceptions and interrupts.
1017 Count instruction cache fetches.
1018 .It Li k8-ic-instruction-fetch-stall
1019 Count cycles in stalls due to instruction fetch.
1020 .It Li k8-ic-l1-itlb-miss-and-l2-itlb-hit
1021 Count L1 ITLB misses that are L2 ITLB hits.
1022 .It Li k8-ic-l1-itlb-miss-and-l2-itlb-miss
1023 Count ITLB misses that miss in both L1 and L2 ITLBs.
1024 .It Li k8-ic-microarchitectural-resync-by-snoop
1025 Count microarchitectural resyncs caused by snoops.
1027 Count instruction cache misses.
1028 .It Li k8-ic-refill-from-l2
1029 Count instruction cache refills from L2 cache.
1030 .It Li k8-ic-refill-from-system
1031 Count instruction cache refills from system memory.
1032 .It Li k8-ic-return-stack-hits
1033 Count hits to the return stack.
1034 .It Li k8-ic-return-stack-overflow
1035 Count overflows of the return stack.
1036 .It Li k8-ls-buffer2-full
1037 Count load/store buffer2 full events.
1038 .It Li k8-ls-locked-operation Op Li ,mask= Ns Ar qualifier
1039 Count locked operations.
1040 For revision C and later CPUs, the following qualifiers are supported:
1042 .Bl -tag -width indent -compact
1043 .It Li cycles-in-request
1044 Count the number of cycles in the lock request/grant stage.
1045 .It Li cycles-to-complete
1046 Count the number of cycles a lock takes to complete once it is
1047 non-speculative and is the older load/store operation.
1048 .It Li locked-instructions
1049 Count the number of lock instructions executed.
1052 The default is to count the number of lock instructions executed.
1053 .It Li k8-ls-microarchitectural-late-cancel
1054 Count microarchitectural late cancels of operations in the load/store
1056 .It Li k8-ls-microarchitectural-resync-by-self-modifying-code
1057 Count microarchitectural resyncs caused by self-modifying code.
1058 .It Li k8-ls-microarchitectural-resync-by-snoop
1059 Count microarchitectural resyncs caused by snoops.
1060 .It Li k8-ls-retired-cflush-instructions
1061 Count retired CFLUSH instructions.
1062 .It Li k8-ls-retired-cpuid-instructions
1063 Count retired CPUID instructions.
1064 .It Li k8-ls-segment-register-load Op Li ,mask= Ns Ar qualifier
1065 Count segment register loads.
1066 This event may be further qualified using
1070 separated set of the following keywords:
1071 .Bl -tag -width indent -compact
1073 Count CS register loads.
1075 Count DS register loads.
1077 Count ES register loads.
1079 Count FS register loads.
1081 Count GS register loads.
1083 .\" Count HS register loads.
1084 .\" XXX "HS" register?
1086 Count SS register loads.
1089 The default is to count all types of loads.
1090 .It Li k8-nb-memory-controller-bypass-saturation Op Li ,mask= Ns Ar qualifier
1091 Count memory controller bypass counter saturation events.
1092 This event may be further qualified using
1096 separated set of the following keywords:
1098 .Bl -tag -width indent -compact
1099 .It Li dram-controller-interface-bypass
1100 Count DRAM controller interface bypass.
1101 .It Li dram-controller-queue-bypass
1102 Count DRAM controller queue bypass.
1103 .It Li memory-controller-hi-pri-bypass
1104 Count memory controller high priority bypasses.
1105 .It Li memory-controller-lo-pri-bypass
1106 Count memory controller low priority bypasses.
1109 .It Li k8-nb-memory-controller-dram-slots-missed
1110 Count memory controller DRAM command slots missed (in MemClks).
1111 .It Li k8-nb-memory-controller-page-access-event Op Li ,mask= Ns Ar qualifier
1112 Count memory controller page access events.
1113 This event may be further qualified using
1117 separated set of the following keywords:
1119 .Bl -tag -width indent -compact
1120 .It Li page-conflict
1121 Count page conflicts.
1128 The default is to count all types of events.
1129 .It Li k8-nb-memory-controller-page-table-overflow
1130 Count memory control page table overflow events.
1131 .It Li k8-nb-probe-result Op Li ,mask= Ns Ar qualifier
1133 This event may be further qualified using
1137 separated set of the following keywords:
1139 .Bl -tag -width indent -compact
1141 Count all probe hits.
1142 .It Li probe-hit-dirty-no-memory-cancel
1143 Count probe hits without memory cancels.
1144 .It Li probe-hit-dirty-with-memory-cancel
1145 Count probe hits with memory cancels.
1149 .It Li k8-nb-sized-commands Op Li ,mask= Ns Ar qualifier
1150 Count sized commands issued.
1151 This event may be further qualified using
1155 separated set of the following keywords:
1157 .Bl -tag -width indent -compact
1158 .It Li nonpostwrszbyte
1159 .It Li nonpostwrszdword
1161 .It Li postwrszdword
1167 The default is to count all types of commands.
1168 .It Li k8-nb-memory-controller-turnaround Op Li ,mask= Ns Ar qualifier
1169 Count memory control turnaround events.
1170 This event may be further qualified using
1174 separated set of the following keywords:
1176 .Bl -tag -width indent -compact
1177 .\" XXX doc is unclear whether these are cycle counts or event counts
1178 .It Li dimm-turnaround
1179 Count DIMM turnarounds.
1180 .It Li read-to-write-turnaround
1181 Count read to write turnarounds.
1182 .It Li write-to-read-turnaround
1183 Count write to read turnarounds.
1186 The default is to count all types of events.
1187 .It Li k8-nb-ht-bus0-bandwidth Op Li ,mask= Ns Ar qualifier
1188 .It Li k8-nb-ht-bus1-bandwidth Op Li ,mask= Ns Ar qualifier
1189 .It Li k8-nb-ht-bus2-bandwidth Op Li ,mask= Ns Ar qualifier
1190 Count events on the HyperTransport(tm) buses.
1191 These events may be further qualified using
1195 separated set of the following keywords:
1197 .Bl -tag -width indent -compact
1198 .It Li buffer-release
1199 Count buffer release messages sent.
1201 Count command messages sent.
1203 Count data messages sent.
1205 Count nop messages sent.
1208 The default is to count all types of messages.
1210 .Ss Intel Pentium PMCS
1211 Intel Pentium PMCs are present in Intel
1217 These CPUs have two counters.
1218 Some events may only be used on specific counters and some events
1219 are defined only on processors supporting the MMX instruction set.
1221 These PMCs are documented in
1223 .%B "Intel 64 and IA-32 Intel(R) Architectures Software Developer's Manual"
1224 .%T "Volume 3B: System Programming Guide, Part 2"
1225 .%N "Order Number 253669-024US"
1227 .%Q "Intel Corporation"
1230 Event specifiers for Intel Pentium PMCs can have the following common
1232 .Bl -tag -width indent
1234 Count duration (in clocks) of events.
1235 The default is to count events.
1237 Measure events at privilege levels 0, 1 and 2.
1239 Assert the external processor pin associated with a counter on counter
1242 Measure events at privilege level 3.
1245 Note that these PMCs do not have the ability to interrupt the CPU.
1247 The event specifiers supported by Intel Pentium PMCs are:
1248 .Bl -tag -width indent
1249 .It Li p5-any-segment-register-loaded
1250 The number of writes to any segment register, including the LDTR,
1252 Far control transfers and task switches that involve privilege
1253 level changes will count this event twice.
1254 .It Li p5-bank-conflicts
1255 The number of actual bank conflicts.
1257 The number of taken and not taken branches including branches, jumps, calls,
1258 software interrupts and interrupt returns.
1259 .It Li p5-breakpoint-match-on-dr0-register
1260 The number of matches on the DR0 breakpoint register.
1261 .It Li p5-breakpoint-match-on-dr1-register
1262 The number of matches on the DR1 breakpoint register.
1263 .It Li p5-breakpoint-match-on-dr2-register
1264 The number of matches on the DR2 breakpoint register.
1265 .It Li p5-breakpoint-match-on-dr3-register
1266 The number of matches on the DR3 breakpoint register.
1267 .It Li p5-btb-false-entries
1269 The number of false entries in the BTB.
1270 This event is only allocated on counter 0.
1272 The number of branches executed that hit in the branch table buffer.
1273 .It Li p5-btb-miss-prediction-on-not-taken-branch
1275 The number of times the BTB predicted a not-taken branch as taken.
1276 This event is only allocated on counter 1.
1277 .It Li p5-bus-cycle-duration
1278 The number of cycles while a bus cycle was in progress.
1279 .It Li p5-bus-ownership-latency
1281 The time from bus ownership being requested to ownership being granted.
1282 This event is only allocated on counter 0.
1283 .It Li p5-bus-ownership-transfers
1285 The number of bus ownership transfers.
1286 This event is only allocated on counter 1.
1287 .It Li p5-bus-utilization-due-to-processor-activity
1289 The number of clocks the bus is busy due to the processor's own
1291 This event is only allocated on counter 0.
1292 .It Li p5-cache-line-sharing
1294 The number of shared data lines in L1 cache.
1295 This event is only allocated on counter 1.
1296 .It Li p5-cache-m-state-line-sharing
1298 The number of hits to an M- state line due to a memory access by
1300 This event is only allocated on counter 0.
1301 .It Li p5-code-cache-miss
1302 The number of instruction reads that miss the internal code cache.
1303 Both cacheable and uncacheable misses are counted.
1305 The number of instruction reads to both cacheable and uncacheable regions.
1306 .It Li p5-code-tlb-miss
1307 The number of instruction reads that miss the instruction TLB.
1308 Both cacheable and uncacheable unreads are counted.
1309 .It Li p5-d1-starvation-and-fifo-is-empty
1311 The number of times the D1 stage cannot issue any instructions because
1313 This event is only allocated on counter 0.
1314 .It Li p5-d1-starvation-and-only-one-instruction-in-fifo
1316 The number of times the D1 stage could issue only one instruction
1317 because the FIFO had one instruction ready.
1318 This event is only allocated on counter 1.
1319 .It Li p5-data-cache-lines-written-back
1320 The number of data cache lines that are written back, including
1321 those caused by internal and external snoops.
1322 .It Li p5-data-cache-tlb-miss-stall-duration
1324 The number of clocks the pipeline is stalled due to a data cache
1326 This event is only allocated on counter 1.
1328 The number of memory data reads, counting internal data cache hits and
1330 I/O and data memory accesses due to TLB miss processing are
1332 Split cycle reads are counted individually.
1333 .It Li p5-data-read-miss
1334 The number of memory read accesses that miss the data cache, counting
1335 both cacheable and uncacheable accesses.
1336 Data accesses that are part of TLB miss processing are not included.
1337 I/O accesses are not included.
1338 .It Li p5-data-read-miss-or-write-miss
1339 The number of data reads and writes that miss the internal data cache,
1340 counting uncacheable accesses.
1341 Data accesses due to TLB miss processing are not counted.
1342 .It Li p5-data-read-or-write
1343 The number of data reads and writes including internal data cache hits
1345 Data reads due to TLB miss processing are not counted.
1346 .It Li p5-data-tlb-miss
1347 The number of misses to the data cache translation lookaside buffer.
1348 .It Li p5-data-write
1349 The number of memory data writes, counting internal data cache hits
1351 I/O is not included and split cycle writes are counted individually.
1352 .It Li p5-data-write-miss
1353 The number of memory write accesses that miss the data cache, counting
1354 both cacheable and uncacheable accesses.
1355 I/O accesses are not counted.
1356 .It Li p5-emms-instructions-executed
1358 The number of EMMS instructions executed.
1359 This event is only allocated on counter 0.
1360 .It Li p5-external-data-cache-snoop-hits
1361 The number of external snoops to the data cache that hit a valid line,
1362 or the data line fill buffer, or one of the write back buffers.
1363 .It Li p5-external-snoops
1364 The number of external snoop requests accepted, including snoops that
1365 hit in the code cache, the data cache and that hit in neither.
1366 .It Li p5-floating-point-stalls-duration
1368 The number of cycles the pipeline is stalled due to a floating point
1370 This event is only allocated on counter 0.
1372 The number of floating point adds, subtracts, multiples, divides and
1374 Transcendental instructions trigger this event multiple times.
1375 Instructions generating divide-by-zero, negative square root, special
1376 operand and stack exceptions are not counted.
1377 Integer multiply instructions that use the x87 FPU are counted.
1378 .It Li p5-full-write-buffer-stall-duration-while-executing-mmx-instructions
1380 The number of clocks the pipeline has stalled due to full write
1381 buffers when executing MMX instructions.
1382 This event is only allocated on counter 0.
1383 .It Li p5-hardware-interrupts
1384 The number of taken INTR and NMI interrupts.
1385 .It Li p5-instructions-executed
1386 The number of instructions executed.
1387 Repeat prefixed instructions are counted only once.
1388 The HLT instruction is counted only once, irrespective of the number
1389 of cycles spent in the halted state.
1390 All hardware and software exceptions are counted as instructions, and
1391 fault handler invocations are also counted as instructions.
1392 .It Li p5-instructions-executed-v-pipe
1393 The number of instructions that executed in the V pipe.
1394 .It Li p5-io-read-or-write-cycle
1395 The number of bus cycles directed to I/O space.
1396 .It Li p5-locked-bus-cycle
1397 The number of locked bus cycles that occur on account of the lock
1398 prefixes, LOCK instructions, page table updates and descriptor table
1400 .It Li p5-memory-accesses-in-both-pipes
1401 The number of data memory reads or writes that are paired in both pipes.
1402 .It Li p5-misaligned-data-memory-on-mmx-instructions
1404 The number of misaligned data memory references when executing MMX
1406 This event is only allocated on counter 0.
1407 .It Li p5-misaligned-data-memory-or-io-references
1408 The number of memory or I/O reads or writes that are not aligned on
1410 2- and 4-byte accesses are counted as misaligned if they cross a 4
1412 .It Li p5-mispredicted-or-unpredicted-returns
1414 The number of returns predicted incorrectly or not at all, only
1415 counting RET instructions.
1416 This event is only allocated on counter 0.
1417 .It Li p5-mmx-instruction-data-read-misses
1419 The number of MMX instruction data read misses.
1420 This event is only allocated on counter 1.
1421 .It Li p5-mmx-instruction-data-reads
1423 The number of MMX instruction data reads.
1424 This event is only allocated on counter 0.
1425 .It Li p5-mmx-instruction-data-write-misses
1427 The number of data write misses caused by MMX instructions.
1428 This event is only allocated on counter 1.
1429 .It Li p5-mmx-instruction-data-writes
1431 The number of data writes caused by MMX instructions.
1432 This event is only allocated on counter 0.
1433 .It Li p5-mmx-instructions-executed-u-pipe
1435 The number of MMX instructions executed in the U pipe.
1436 This event is only allocated on counter 0.
1437 .It Li p5-mmx-instructions-executed-v-pipe
1438 The number of MMX instructions executed in the V pipe.
1439 This event is only allocated on counter 1.
1440 .It Li p5-mmx-multiply-unit-interlock
1442 The number of clocks the pipeline is stalled because the destination
1443 of a prior MMX multiply is not ready.
1444 This event is only allocated on counter 0.
1445 .It Li p5-movd-movq-store-stall-due-to-previous-mmx-operation
1447 The number of clocks a MOVD/MOVQ instruction stalled in the D2 stage
1448 of the pipeline due to a previous MMX instruction.
1449 This event is only allocated on counter 1.
1450 .It Li p5-noncacheable-memory-reads
1451 The number of bus cycles for non-cacheable instruction or data reads,
1452 including cycles caused by TLB misses.
1453 .It Li p5-number-of-cycles-not-in-halt-state
1455 The number of cycles the processor is not idle due to the HLT
1457 This event is only allocated on counter 0.
1458 .It Li p5-pipeline-agi-stalls
1459 The number of address generation interlock stalls.
1460 An AGI that occurs in both the U and V pipelines in the same clock
1461 signals the event twice.
1462 .It Li p5-pipeline-flushes
1463 The number of pipeline flushes that occur.
1464 Pipeline flushes are caused by branch mispredicts, exceptions,
1465 interrupts, some segment register loads, and BTB misses.
1466 Prefetch queue flushes due to serializing instructions are not
1468 .It Li p5-pipeline-flushes-due-to-wrong-branch-predictions
1470 The number of pipeline flushes due to wrong branch predictions
1471 resolved in either the E- or WB- stage of the pipeline.
1472 This event is only allocated on counter 0.
1473 .It Li p5-pipeline-flushes-due-to-wrong-branch-predictions-resolved-in-wb-stage
1475 The number of pipeline flushes due to wrong branch predictions
1476 resolved in the stage of the pipeline.
1477 This event is only allocated on counter 1.
1478 .It Li p5-pipeline-stall-for-mmx-instruction-data-memory-reads
1480 The number of clocks during pipeline stalls caused by waiting MMX data
1482 This event is only allocated on counter 0.
1483 .It Li p5-predicted-returns
1485 The number of predicted returns, whether correct or incorrect.
1486 This counter only counts RET instructions.
1487 This event is only allocated on counter 1.
1490 The number of RET instructions executed.
1491 This event is only allocated on counter 0.
1492 .It Li p5-saturating-mmx-instructions-executed
1494 The number of saturating MMX instructions executed.
1495 This event is only allocated on counter 0.
1496 .It Li p5-saturations-performed
1498 The number of saturating MMX instructions executed when at least one
1499 of its results were actually saturated.
1500 This event is only allocated on counter 1.
1501 .It Li p5-stall-on-mmx-instruction-write-to-e-o-m-state-line
1503 The number of clocks during stalls on MMX instructions writing to
1504 E- or M- state cache lines.
1505 This event is only allocated on counter 1.
1506 .It Li p5-stall-on-write-to-an-e-or-m-state-line
1507 The number of stalls on a write to an exclusive or modified data cache
1509 .It Li p5-taken-branch-or-btb-hit
1510 The number of events that may cause a hit in the BTB, namely either
1511 taken branches or BTB hits.
1512 .It Li p5-taken-branches
1514 The number of taken branches.
1515 This event is only allocated on counter 1.
1516 .It Li p5-transitions-between-mmx-and-fp-instructions
1518 The number of transitions between MMX and floating-point instructions
1520 This event is only allocated on counter 1.
1521 .It Li p5-waiting-for-data-memory-read-stall-duration
1522 The number of clocks the pipeline was stalled waiting for data
1524 Data TLB misses processing is included in this count.
1525 .It Li p5-write-buffer-full-stall-duration
1526 The number of clocks while the pipeline was stalled due to write
1528 .It Li p5-write-hit-to-m-or-e-state-lines
1529 The number of writes that hit exclusive or modified lines in the data
1531 .It Li p5-writes-to-noncacheable-memory
1533 The number of writes to non-cacheable memory, including write cycles
1534 caused by TLB misses and I/O writes.
1535 This event is only allocated on counter 1.
1538 Intel P6 PMCs are present in Intel
1547 These CPUs have two counters.
1548 Some events may only be used on specific counters and some events are
1549 defined only on specific processor models.
1551 These PMCs are documented in
1553 .%B "IA-32 Intel(R) Architecture Software Developer's Manual"
1554 .%T "Volume 3: System Programming Guide"
1555 .%N "Order Number 245472-012"
1557 .%Q "Intel Corporation"
1560 Some of these events are affected by processor errata described in
1562 .%B "Intel(R) Pentium(R) III Processor Specification Update"
1563 .%N "Document Number: 244453-054"
1565 .%Q "Intel Corporation"
1568 Event specifiers for Intel P6 PMCs can have the following common
1570 .Bl -tag -width indent
1571 .It Li cmask= Ns Ar value
1572 Configure the PMC to increment only if the number of configured
1573 events measured in a cycle is greater than or equal to
1576 Configure the PMC to count the number of deasserted to asserted
1577 transitions of the conditions expressed by the other qualifiers.
1578 If specified, the counter will increment only once whenever a
1579 condition becomes true, irrespective of the number of clocks during
1580 which the condition remains true.
1582 Invert the sense of comparision when the
1584 qualifier is present, making the counter increment when the number of
1585 events per cycle is less than the value specified by the
1589 Configure the PMC to count events happening at processor privilege
1591 .It Li umask= Ns Ar value
1592 This qualifier is used to further qualify the event selected (see
1595 Configure the PMC to count events occurring at privilege levels 1, 2
1603 qualifiers are specified, the default is to enable both.
1605 The event specifiers supported by Intel P6 PMCs are:
1606 .Bl -tag -width indent
1608 Count the number of times a static branch prediction was made by the
1609 branch decoder because the BTB did not have a prediction.
1610 .It Li p6-br-bac-missp-exec
1612 Count the number of branch instructions executed that where
1613 mispredicted at the Front End (BAC).
1615 Count the number of bogus branches.
1616 .It Li p6-br-call-exec
1618 Count the number of call instructions executed.
1619 .It Li p6-br-call-missp-exec
1621 Count the number of call instructions executed that were mispredicted.
1622 .It Li p6-br-cnd-exec
1624 Count the number of conditional branch instructions executed.
1625 .It Li p6-br-cnd-missp-exec
1627 Count the number of conditional branch instructions executed that were
1629 .It Li p6-br-ind-call-exec
1631 Count the number of indirect call instructions executed.
1632 .It Li p6-br-ind-exec
1634 Count the number of indirect branch instructions executed.
1635 .It Li p6-br-ind-missp-exec
1637 Count the number of indirect branch instructions executed that were
1639 .It Li p6-br-inst-decoded
1640 Count the number of branch instructions decoded.
1641 .It Li p6-br-inst-exec
1643 Count the number of branch instructions executed but necessarily retired.
1644 .It Li p6-br-inst-retired
1645 Count the number of branch instructions retired.
1646 .It Li p6-br-miss-pred-retired
1647 Count the number of mispredicted branch instructions retired.
1648 .It Li p6-br-miss-pred-taken-ret
1649 Count the number of taken mispredicted branches retired.
1650 .It Li p6-br-missp-exec
1652 Count the number of branch instructions executed that were
1653 mispredicted at execution.
1654 .It Li p6-br-ret-bac-missp-exec
1656 Count the number of return instructions executed that were
1657 mispredicted at the Front End (BAC).
1658 .It Li p6-br-ret-exec
1660 Count the number of return instructions executed.
1661 .It Li p6-br-ret-missp-exec
1663 Count the number of return instructions executed that were
1664 mispredicted at execution.
1665 .It Li p6-br-taken-retired
1666 Count the number of taken branches retired.
1667 .It Li p6-btb-misses
1668 Count the number of branches for which the BTB did not produce a
1670 .It Li p6-bus-bnr-drv
1671 Count the number of bus clock cycles during which this processor is
1672 driving the BNR# pin.
1673 .It Li p6-bus-data-rcv
1674 Count the number of bus clock cycles during which this processor is
1676 .It Li p6-bus-drdy-clocks Op Li ,umask= Ns Ar qualifier
1677 Count the number of clocks during which DRDY# is asserted.
1678 An additional qualifier may be specified, and comprises one of the
1681 .Bl -tag -width indent -compact
1683 Count transactions generated by any agent on the bus.
1685 Count transactions generated by this processor.
1688 The default is to count operations generated by this processor.
1689 .It Li p6-bus-hit-drv
1690 Count the number of bus clock cycles during which this processor is
1691 driving the HIT# pin.
1692 .It Li p6-bus-hitm-drv
1693 Count the number of bus clock cycles during which this processor is
1694 driving the HITM# pin.
1695 .It Li p6-bus-lock-clocks Op Li ,umask= Ns Ar qualifier
1696 Count the number of clocks during with LOCK# is asserted on the
1697 external system bus.
1698 An additional qualifier may be specified and comprises one of the following
1701 .Bl -tag -width indent -compact
1703 Count transactions generated by any agent on the bus.
1705 Count transactions generated by this processor.
1708 The default is to count operations generated by this processor.
1709 .It Li p6-bus-req-outstanding
1710 Count the number of bus requests outstanding in any given cycle.
1711 .It Li p6-bus-snoop-stall
1712 Count the number of clock cycles during which the bus is snoop stalled.
1713 .It Li p6-bus-tran-any Op Li ,umask= Ns Ar qualifier
1714 Count the number of completed bus transactions of any kind.
1715 An additional qualifier may be specified and comprises one of the following
1718 .Bl -tag -width indent -compact
1720 Count transactions generated by any agent on the bus.
1722 Count transactions generated by this processor.
1725 The default is to count operations generated by this processor.
1726 .It Li p6-bus-tran-brd Op Li ,umask= Ns Ar qualifier
1727 Count the number of burst read transactions.
1728 An additional qualifier may be specified and comprises one of the following
1731 .Bl -tag -width indent -compact
1733 Count transactions generated by any agent on the bus.
1735 Count transactions generated by this processor.
1738 The default is to count operations generated by this processor.
1739 .It Li p6-bus-tran-burst Op Li ,umask= Ns Ar qualifier
1740 Count the number of completed burst transactions.
1741 An additional qualifier may be specified and comprises one of the following
1744 .Bl -tag -width indent -compact
1746 Count transactions generated by any agent on the bus.
1748 Count transactions generated by this processor.
1751 The default is to count operations generated by this processor.
1752 .It Li p6-bus-tran-def Op Li ,umask= Ns Ar qualifier
1753 Count the number of completed deferred transactions.
1754 An additional qualifier may be specified and comprises one of the following
1757 .Bl -tag -width indent -compact
1759 Count transactions generated by any agent on the bus.
1761 Count transactions generated by this processor.
1764 The default is to count operations generated by this processor.
1765 .It Li p6-bus-tran-ifetch Op Li ,umask= Ns Ar qualifier
1766 Count the number of completed instruction fetch transactions.
1767 An additional qualifier may be specified and comprises one of the following
1770 .Bl -tag -width indent -compact
1772 Count transactions generated by any agent on the bus.
1774 Count transactions generated by this processor.
1777 The default is to count operations generated by this processor.
1778 .It Li p6-bus-tran-inval Op Li ,umask= Ns Ar qualifier
1779 Count the number of completed invalidate transactions.
1780 An additional qualifier may be specified and comprises one of the following
1783 .Bl -tag -width indent -compact
1785 Count transactions generated by any agent on the bus.
1787 Count transactions generated by this processor.
1790 The default is to count operations generated by this processor.
1791 .It Li p6-bus-tran-mem Op Li ,umask= Ns Ar qualifier
1792 Count the number of completed memory transactions.
1793 An additional qualifier may be specified and comprises one of the following
1796 .Bl -tag -width indent -compact
1798 Count transactions generated by any agent on the bus.
1800 Count transactions generated by this processor.
1803 The default is to count operations generated by this processor.
1804 .It Li p6-bus-tran-pwr Op Li ,umask= Ns Ar qualifier
1805 Count the number of completed partial write transactions.
1806 An additional qualifier may be specified and comprises one of the following
1809 .Bl -tag -width indent -compact
1811 Count transactions generated by any agent on the bus.
1813 Count transactions generated by this processor.
1816 The default is to count operations generated by this processor.
1817 .It Li p6-bus-tran-rfo Op Li ,umask= Ns Ar qualifier
1818 Count the number of completed read-for-ownership transactions.
1819 An additional qualifier may be specified and comprises one of the following
1822 .Bl -tag -width indent -compact
1824 Count transactions generated by any agent on the bus.
1826 Count transactions generated by this processor.
1829 The default is to count operations generated by this processor.
1830 .It Li p6-bus-trans-io Op Li ,umask= Ns Ar qualifier
1831 Count the number of completed I/O transactions.
1832 An additional qualifier may be specified and comprises one of the following
1835 .Bl -tag -width indent -compact
1837 Count transactions generated by any agent on the bus.
1839 Count transactions generated by this processor.
1842 The default is to count operations generated by this processor.
1843 .It Li p6-bus-trans-p Op Li ,umask= Ns Ar qualifier
1844 Count the number of completed partial transactions.
1845 An additional qualifier may be specified and comprises one of the following
1848 .Bl -tag -width indent -compact
1850 Count transactions generated by any agent on the bus.
1852 Count transactions generated by this processor.
1855 The default is to count operations generated by this processor.
1856 .It Li p6-bus-trans-wb Op Li ,umask= Ns Ar qualifier
1857 Count the number of completed write-back transactions.
1858 An additional qualifier may be specified and comprises one of the following
1861 .Bl -tag -width indent -compact
1863 Count transactions generated by any agent on the bus.
1865 Count transactions generated by this processor.
1868 The default is to count operations generated by this processor.
1869 .It Li p6-cpu-clk-unhalted
1870 Count the number of cycles during with the processor was not halted.
1873 Count the number of cycles during with the processor was not halted
1874 and not in a thermal trip.
1875 .It Li p6-cycles-div-busy
1876 Count the number of cycles during which the divider is busy and cannot
1878 This event is only allocated on counter 0.
1879 .It Li p6-cycles-in-pending-and-masked
1880 Count the number of processor cycles for which interrupts were
1881 disabled and interrupts were pending.
1882 .It Li p6-cycles-int-masked
1883 Count the number of processor cycles for which interrupts were
1885 .It Li p6-data-mem-refs
1886 Count all loads and all stores using any memory type, including
1888 Each part of a split store is counted separately.
1889 .It Li p6-dcu-lines-in
1890 Count the total lines allocated in the data cache unit.
1891 .It Li p6-dcu-m-lines-in
1892 Count the number of M state lines allocated in the data cache unit.
1893 .It Li p6-dcu-m-lines-out
1894 Count the number of M state lines evicted from the data cache unit.
1895 .It Li p6-dcu-miss-outstanding
1896 Count the weighted number of cycles while a data cache unit miss is
1897 outstanding, incremented by the number of outstanding cache misses at
1900 Count the number of integer and floating-point divides including
1901 speculative divides.
1902 This event is only allocated on counter 1.
1903 .It Li p6-emon-esp-uops
1905 Count the total number of micro-ops.
1906 .It Li p6-emon-est-trans Op Li ,umask= Ns Ar qualifier
1909 .Tn "Enhanced Intel SpeedStep"
1911 An additional qualifier may be specified, and can be one of the
1914 .Bl -tag -width indent -compact
1916 Count all transitions.
1918 Count only frequency transitions.
1921 The default is to count all transitions.
1922 .It Li p6-emon-fused-uops-ret Op Li ,umask= Ns Ar qualifier
1924 Count the number of retired fused micro-ops.
1925 An additional qualifier may be specified, and may be one of the
1928 .Bl -tag -width indent -compact
1930 Count all fused micro-ops.
1932 Count only load and op micro-ops.
1934 Count only STD/STA micro-ops.
1937 The default is to count all fused micro-ops.
1938 .It Li p6-emon-kni-comp-inst-ret
1939 .Pq Tn "Pentium III"
1940 Count the number of SSE computational instructions retired.
1941 An additional qualifier may be specified, and comprises one of the
1944 .Bl -tag -width indent -compact
1945 .It Li packed-and-scalar
1946 Count packed and scalar operations.
1948 Count scalar operations only.
1951 The default is to count packed and scalar operations.
1952 .It Li p6-emon-kni-inst-retired Op Li ,umask= Ns Ar qualifier
1953 .Pq Tn "Pentium III"
1954 Count the number of SSE instructions retired.
1955 An additional qualifier may be specified, and comprises one of the
1958 .Bl -tag -width indent -compact
1959 .It Li packed-and-scalar
1960 Count packed and scalar operations.
1962 Count scalar operations only.
1965 The default is to count packed and scalar operations.
1966 .It Li p6-emon-kni-pref-dispatched Op Li ,umask= Ns Ar qualifier
1967 .Pq Tn "Pentium III"
1968 Count the number of SSE prefetch or weakly ordered instructions
1969 dispatched (including speculative prefetches).
1970 An additional qualifier may be specified, and comprises one of the
1973 .Bl -tag -width indent -compact
1975 Count non-temporal prefetches.
1977 Count prefetches to L1.
1979 Count prefetches to L2.
1981 Count weakly ordered stores.
1984 The default is to count non-temporal prefetches.
1985 .It Li p6-emon-kni-pref-miss Op Li ,umask= Ns Ar qualifier
1986 .Pq Tn "Pentium III"
1987 Count the number of prefetch or weakly ordered instructions that miss
1989 An additional qualifier may be specified, and comprises one of the
1992 .Bl -tag -width indent -compact
1994 Count non-temporal prefetches.
1996 Count prefetches to L1.
1998 Count prefetches to L2.
2000 Count weakly ordered stores.
2003 The default is to count non-temporal prefetches.
2004 .It Li p6-emon-pref-rqsts-dn
2006 Count the number of downward prefetches issued.
2007 .It Li p6-emon-pref-rqsts-up
2009 Count the number of upward prefetches issued.
2010 .It Li p6-emon-simd-instr-retired
2012 Count the number of retired
2015 .It Li p6-emon-sse-sse2-comp-inst-retired Op Li ,umask= Ns Ar qualifier
2017 Count the number of computational SSE instructions retired.
2018 An additional qualifier may be specified and can be one of the
2021 .Bl -tag -width indent -compact
2022 .It Li sse-packed-single
2023 Count SSE packed-single instructions.
2024 .It Li sse-scalar-single
2025 Count SSE scalar-single instructions.
2026 .It Li sse2-packed-double
2027 Count SSE2 packed-double instructions.
2028 .It Li sse2-scalar-double
2029 Count SSE2 scalar-double instructions.
2032 The default is to count SSE packed-single instructions.
2033 .It Li p6-emon-sse-sse2-inst-retired Op Li ,umask= Ns Ar qualifer
2036 Count the number of SSE instructions retired.
2037 An additional qualifier can be specified, and can be one of the
2040 .Bl -tag -width indent -compact
2041 .It Li sse-packed-single
2042 Count SSE packed-single instructions.
2043 .It Li sse-packed-single-scalar-single
2044 Count SSE packed-single and scalar-single instructions.
2045 .It Li sse2-packed-double
2046 Count SSE2 packed-double instructions.
2047 .It Li sse2-scalar-double
2048 Count SSE2 scalar-double instructions.
2051 The default is to count SSE packed-single instructions.
2052 .It Li p6-emon-synch-uops
2054 Count the number of sync micro-ops.
2055 .It Li p6-emon-thermal-trip
2057 Count the duration or occurrences of thermal trips.
2060 qualifier to count occurrences of thermal trips.
2061 .It Li p6-emon-unfusion
2063 Count the number of unfusion events in the reorder buffer.
2065 Count the number of computational floating point operations retired.
2066 This event is only allocated on counter 0.
2068 Count the number of floating point exceptions handled by microcode.
2069 This event is only allocated on counter 1.
2070 .It Li p6-fp-comps-ops-exe
2071 Count the number of computation floating point operations executed.
2072 This event is only allocated on counter 0.
2073 .It Li p6-fp-mmx-trans Op Li ,umask= Ns Ar qualifier
2074 .Pq Tn "Pentium II" , Tn "Pentium III"
2075 Count the number of transitions between MMX and floating-point
2077 An additional qualifier may be specified, and comprises one of the
2080 .Bl -tag -width indent -compact
2082 Count transitions from MMX instructions to floating-point instructions.
2084 Count transitions from floating-point instructions to MMX instructions.
2087 The default is to count MMX to floating-point transitions.
2089 Count the number of hardware interrupts received.
2091 Count the number of instruction fetches, both cacheable and non-cacheable.
2092 .It Li p6-ifu-fetch-miss
2093 Count the number of instruction fetch misses (i.e., those that produce
2095 .It Li p6-ifu-mem-stall
2096 Count the number of cycles instruction fetch is stalled for any reason.
2098 Count the number of cycles the instruction length decoder is stalled.
2099 .It Li p6-inst-decoded
2100 Count the number of instructions decoded.
2101 .It Li p6-inst-retired
2102 Count the number of instructions retired.
2104 Count the number of instruction TLB misses.
2106 Count the number of L2 address strobes.
2107 .It Li p6-l2-dbus-busy
2108 Count the number of cycles during which the L2 cache data bus was busy.
2109 .It Li p6-l2-dbus-busy-rd
2110 Count the number of cycles during which the L2 cache data bus was busy
2111 transferring read data from L2 to the processor.
2112 .It Li p6-l2-ifetch Op Li ,umask= Ns Ar qualifier
2113 Count the number of L2 instruction fetches.
2114 An additional qualifier may be specified and comprises a list of the following
2115 keywords separated by
2119 .Bl -tag -width indent -compact
2121 Count operations affecting E (exclusive) state lines.
2123 Count operations affecting I (invalid) state lines.
2125 Count operations affecting M (modified) state lines.
2127 Count operations affecting S (shared) state lines.
2130 The default is to count operations affecting all (MESI) state lines.
2131 .It Li p6-l2-ld Op Li ,umask= Ns Ar qualifier
2132 Count the number of L2 data loads.
2133 An additional qualifier may be specified and comprises a list of the following
2134 keywords separated by
2138 .Bl -tag -width indent -compact
2141 Count both hardware-prefetched lines and non-hardware-prefetched lines.
2143 Count operations affecting E (exclusive) state lines.
2146 Count hardware-prefetched lines only.
2148 Count operations affecting I (invalid) state lines.
2150 Count operations affecting M (modified) state lines.
2153 Exclude hardware-prefetched lines.
2155 Count operations affecting S (shared) state lines.
2158 The default on processors other than
2160 processors is to count operations affecting all (MESI) state lines.
2163 processors is to count both hardware-prefetched and
2164 non-hardware-prefetch operations on all (MESI) state lines.
2166 This event is affected by processor errata E53.
2167 .It Li p6-l2-lines-in Op Li ,umask= Ns Ar qualifier
2168 Count the number of L2 lines allocated.
2169 An additional qualifier may be specified and comprises a list of the following
2170 keywords separated by
2174 .Bl -tag -width indent -compact
2177 Count both hardware-prefetched lines and non-hardware-prefetched lines.
2179 Count operations affecting E (exclusive) state lines.
2182 Count hardware-prefetched lines only.
2184 Count operations affecting I (invalid) state lines.
2186 Count operations affecting M (modified) state lines.
2189 Exclude hardware-prefetched lines.
2191 Count operations affecting S (shared) state lines.
2194 The default on processors other than
2196 processors is to count operations affecting all (MESI) state lines.
2199 processors is to count both hardware-prefetched and
2200 non-hardware-prefetch operations on all (MESI) state lines.
2202 This event is affected by processor errata E45.
2203 .It Li p6-l2-lines-out Op Li ,umask= Ns Ar qualifier
2204 Count the number of L2 lines evicted.
2205 An additional qualifier may be specified and comprises a list of the following
2206 keywords separated by
2210 .Bl -tag -width indent -compact
2213 Count both hardware-prefetched lines and non-hardware-prefetched lines.
2215 Count operations affecting E (exclusive) state lines.
2218 Count hardware-prefetched lines only.
2220 Count operations affecting I (invalid) state lines.
2222 Count operations affecting M (modified) state lines.
2224 .Pq Tn "Pentium M" only
2225 Exclude hardware-prefetched lines.
2227 Count operations affecting S (shared) state lines.
2230 The default on processors other than
2232 processors is to count operations affecting all (MESI) state lines.
2235 processors is to count both hardware-prefetched and
2236 non-hardware-prefetch operations on all (MESI) state lines.
2238 This event is affected by processor errata E45.
2239 .It Li p6-l2-m-lines-inm
2240 Count the number of modified lines allocated in L2 cache.
2241 .It Li p6-l2-m-lines-outm Op Li ,umask= Ns Ar qualifier
2242 Count the number of L2 M-state lines evicted.
2245 On these processors an additional qualifier may be specified and
2246 comprises a list of the following keywords separated by
2250 .Bl -tag -width indent -compact
2252 Count both hardware-prefetched lines and non-hardware-prefetched lines.
2254 Count hardware-prefetched lines only.
2256 Exclude hardware-prefetched lines.
2259 The default is to count both hardware-prefetched and
2260 non-hardware-prefetch operations.
2262 This event is affected by processor errata E53.
2263 .It Li p6-l2-rqsts Op Li ,umask= Ns Ar qualifier
2264 Count the total number of L2 requests.
2265 An additional qualifier may be specified and comprises a list of the following
2266 keywords separated by
2270 .Bl -tag -width indent -compact
2272 Count operations affecting E (exclusive) state lines.
2274 Count operations affecting I (invalid) state lines.
2276 Count operations affecting M (modified) state lines.
2278 Count operations affecting S (shared) state lines.
2281 The default is to count operations affecting all (MESI) state lines.
2283 Count the number of L2 data stores.
2284 An additional qualifier may be specified and comprises a list of the following
2285 keywords separated by
2289 .Bl -tag -width indent -compact
2291 Count operations affecting E (exclusive) state lines.
2293 Count operations affecting I (invalid) state lines.
2295 Count operations affecting M (modified) state lines.
2297 Count operations affecting S (shared) state lines.
2300 The default is to count operations affecting all (MESI) state lines.
2302 Count the number of load operations delayed due to store buffer blocks.
2303 .It Li p6-misalign-mem-ref
2304 Count the number of misaligned data memory references (crossing a 64
2306 .It Li p6-mmx-assist
2307 .Pq Tn "Pentium II" , Tn "Pentium III"
2308 Count the number of MMX assists executed.
2309 .It Li p6-mmx-instr-exec
2310 .Pq Tn Celeron , Tn "Pentium II"
2311 Count the number of MMX instructions executed, except MOVQ and MOVD
2312 stores from register to memory.
2313 .It Li p6-mmx-instr-ret
2315 Count the number of MMX instructions retired.
2316 .It Li p6-mmx-instr-type-exec Op Li ,umask= Ns Ar qualifier
2317 .Pq Tn "Pentium II" , Tn "Pentium III"
2318 Count the number of MMX instructions executed.
2319 An additional qualifier may be specified and comprises a list of
2320 the following keywords separated by
2324 .Bl -tag -width indent -compact
2326 Count MMX pack operation instructions.
2327 .It Li packed-arithmetic
2328 Count MMX packed arithmetic instructions.
2329 .It Li packed-logical
2330 Count MMX packed logical instructions.
2331 .It Li packed-multiply
2332 Count MMX packed multiply instructions.
2334 Count MMX packed shift instructions.
2336 Count MMX unpack operation instructions.
2339 The default is to count all operations.
2340 .It Li p6-mmx-sat-instr-exec
2341 .Pq Tn "Pentium II" , Tn "Pentium III"
2342 Count the number of MMX saturating instructions executed.
2343 .It Li p6-mmx-uops-exec
2344 .Pq Tn "Pentium II" , Tn "Pentium III"
2345 Count the number of MMX micro-ops executed.
2347 Count the number of integer and floating-point multiplies, including
2348 speculative multiplies.
2349 This event is only allocated on counter 1.
2350 .It Li p6-partial-rat-stalls
2351 Count the number of cycles or events for partial stalls.
2352 .It Li p6-resource-stalls
2353 Count the number of cycles there was a resource related stall of any kind.
2354 .It Li p6-ret-seg-renames
2355 .Pq Tn "Pentium II" , Tn "Pentium III"
2356 Count the number of segment register rename events retired.
2358 Count the number of cycles the store buffer is draining.
2359 .It Li p6-seg-reg-renames Op Li ,umask= Ns Ar qualifier
2360 .Pq Tn "Pentium II" , Tn "Pentium III"
2361 Count the number of segment register renames.
2362 An additional qualifier may be specified, and comprises a list of the
2363 following keywords separated by
2367 .Bl -tag -width indent -compact
2369 Count renames for segment register DS.
2371 Count renames for segment register ES.
2373 Count renames for segment register FS.
2375 Count renames for segment register GS.
2378 The default is to count operations affecting all segment registers.
2379 .It Li p6-seg-rename-stalls
2380 .Pq Tn "Pentium II" , Tn "Pentium III"
2381 Count the number of segment register renaming stalls.
2382 An additional qualifier may be specified, and comprises a list of the
2383 following keywords separated by
2387 .Bl -tag -width indent -compact
2389 Count stalls for segment register DS.
2391 Count stalls for segment register ES.
2393 Count stalls for segment register FS.
2395 Count stalls for segment register GS.
2398 The default is to count operations affecting all the segment registers.
2399 .It Li p6-segment-reg-loads
2400 Count the number of segment register loads.
2401 .It Li p6-uops-retired
2402 Count the number of micro-ops retired.
2405 Intel P4 PMCs are present in Intel
2410 These PMCs are documented in
2412 .%B "IA-32 Intel(R) Architecture Software Developer's Manual"
2413 .%T "Volume 3: System Programming Guide"
2414 .%N "Order Number 245472-012"
2416 .%Q "Intel Corporation"
2418 Further information about using these PMCs may be found in
2420 .%B "IA-32 Intel(R) Architecture Optimization Guide"
2422 .%N "Order Number 248966-009"
2423 .%Q "Intel Corporation"
2425 Some of these events are affected by processor errata described in
2427 .%B "Intel(R) Pentium(R) 4 Processor Specification Update"
2428 .%N "Document Number: 249199-059"
2430 .%Q "Intel Corporation"
2433 Event specifiers for Intel P4 PMCs can have the following common
2435 .Bl -tag -width indent
2436 .It Li active= Ns Ar choice
2437 (On P4 HTT CPUs) Filter event counting based on which logical
2438 processors are active.
2439 The allowed values of
2443 .Bl -tag -width indent -compact
2445 Count when either logical processor is active.
2447 Count when both logical processors are active.
2449 Count only when neither logical processor is active.
2451 Count only when one logical processor is active.
2457 Configure the PMC to cascade onto its partner.
2459 .Sx "Cascading P4 PMCs"
2460 below for more information.
2462 Configure the counter to count false to true transitions of the threshold
2464 This qualifier only takes effect if a threshold qualifier has also been
2467 Configure the counter to increment only when the event count seen is
2468 less than the threshold qualifier value specified.
2469 .It Li mask= Ns Ar qualifier
2470 Many event specifiers for Intel P4 PMCs need to be additionally
2471 qualified using a mask qualifier.
2472 The allowed syntax for these qualifiers is event specific and is
2473 described along with the events.
2475 Configure the PMC to count when the CPL of the processor is 0.
2477 Select precise event based sampling.
2478 Precise sampling is supported by the hardware for a limited set of
2480 .It Li tag= Ns Ar value
2481 Configure the PMC to tag the internal uop selected by the other
2482 fields in this event specifier with value
2484 This feature is used when cascading PMCs.
2485 .It Li threshold= Ns Ar value
2486 Configure the PMC to increment only when the event counts seen are
2487 greater than the specified threshold value
2490 Configure the PMC to count when the CPL of the processor is 1, 2 or 3.
2497 qualifiers are specified, the default is to enable both.
2499 On Intel Pentium 4 processors with HTT, events are
2500 divided into two classes:
2502 .Bl -tag -width indent -compact
2504 are those where hardware can differentiate between events
2505 generated on one logical processor from those generated on the
2508 are those where hardware cannot differentiate between events
2509 generated by multiple logical processors in a package.
2512 Only TS events are allowed for use with process-mode PMCs on
2515 The event specifiers supported by Intel P4 PMCs are:
2517 .Bl -tag -width indent
2518 .It Li p4-128bit-mmx-uop Op Li ,mask= Ns Ar flags
2520 Count integer SIMD SSE2 instructions that operate on 128 bit SIMD
2524 can take the following value (which is also the default):
2526 .Bl -tag -width indent -compact
2528 Count all uops operating on 128 bit SIMD integer operands in memory or
2532 If an instruction contains more than one 128 bit MMX uop, then each
2533 uop will be counted.
2534 .It Li p4-64bit-mmx-uop Op Li ,mask= Ns Ar flags
2536 Count MMX instructions that operate on 64 bit SIMD operands.
2539 can take the following value (which is also the default):
2541 .Bl -tag -width indent -compact
2543 Count all uops operating on 64 bit SIMD integer operands in memory or
2547 If an instruction contains more than one 64 bit MMX uop, then each
2548 uop will be counted.
2549 .It Li p4-b2b-cycles
2551 Count back-to-back bus cycles.
2552 Further documentation for this event is unavailable.
2555 Count bus-not-ready conditions.
2556 Further documentation for this event is unavailable.
2557 .It Li p4-bpu-fetch-request Op Li ,mask= Ns Ar qualifier
2559 Count instruction fetch requests qualified by additional
2562 At this point only one flag is supported:
2564 .Bl -tag -width indent -compact
2566 Count trace cache lookup misses.
2569 The default qualifier is also
2570 .Dq Li mask=tcmiss .
2571 .It Li p4-branch-retired Op Li ,mask= Ns Ar flags
2573 Counts retired branches.
2576 is a list of the following
2580 .Bl -tag -width indent -compact
2582 Count branches not-taken and predicted.
2584 Count branches not-taken and mis-predicted.
2586 Count branches taken and predicted.
2588 Count branches taken and mis-predicted.
2591 The default qualifier counts all four kinds of branches.
2592 .It Li p4-bsq-active-entries Op Li ,mask= Ns Ar qualifier
2594 Count the number of entries (clipped at 15) currently active in the
2600 separated set of the following flags:
2602 .Bl -tag -width indent -compact
2603 .It Li req-type0 , Li req-type1
2604 Forms a 2-bit number used to select the request type encoding:
2606 .Bl -tag -width indent -compact
2608 reads excluding read invalidate
2612 writes other than writebacks
2619 is the MSB for this two bit number.
2620 .It Li req-len0 , Li req-len1
2621 Forms a two-bit number that specifies the request length encoding:
2623 .Bl -tag -width indent -compact
2634 is the MSB for this two bit number.
2636 Count requests that are input or output requests.
2637 .It Li req-lock-type
2638 Count requests that lock the bus.
2639 .It Li req-lock-cache
2640 Count requests that lock the cache.
2641 .It Li req-split-type
2642 Count requests that is a bus 8-byte chunk that is split across an
2645 Count requests that are demand (not prefetches) if set.
2646 Count requests that are prefetches if not set.
2648 Count requests that are ordered.
2649 .It Li mem-type0 , Li mem-type1 , Li mem-type2
2650 Forms a 3-bit number that specifies a memory type encoding:
2652 .Bl -tag -width indent -compact
2667 is the MSB of this 3-bit number.
2670 The default qualifier has all the above bits set.
2672 Edge triggering using the
2674 qualifier should not be used with this event when counting cycles.
2675 .It Li p4-bsq-allocation Op Li ,mask= Ns Ar qualifier
2677 Count allocations in the bus sequence unit according to the flags
2682 separated set of the following flags:
2684 .Bl -tag -width indent -compact
2685 .It Li req-type0 , Li req-type1
2686 Forms a 2-bit number used to select the request type encoding:
2688 .Bl -tag -width indent -compact
2690 reads excluding read invalidate
2694 writes other than writebacks
2701 is the MSB for this two bit number.
2702 .It Li req-len0 , Li req-len1
2703 Forms a two-bit number that specifies the request length encoding:
2705 .Bl -tag -width indent -compact
2716 is the MSB for this two bit number.
2718 Count requests that are input or output requests.
2719 .It Li req-lock-type
2720 Count requests that lock the bus.
2721 .It Li req-lock-cache
2722 Count requests that lock the cache.
2723 .It Li req-split-type
2724 Count requests that is a bus 8-byte chunk that is split across an
2727 Count requests that are demand (not prefetches) if set.
2728 Count requests that are prefetches if not set.
2730 Count requests that are ordered.
2731 .It Li mem-type0 , Li mem-type1 , Li mem-type2
2732 Forms a 3-bit number that specifies a memory type encoding:
2734 .Bl -tag -width indent -compact
2749 is the MSB of this 3-bit number.
2752 The default qualifier has all the above bits set.
2754 This event is usually used along with the
2756 qualifier to avoid multiple counting.
2757 .It Li p4-bsq-cache-reference Op Li ,mask= Ns Ar qualifier
2759 Count cache references as seen by the bus unit (2nd or 3rd level
2765 separated list of the following keywords:
2767 .Bl -tag -width indent -compact
2769 Count 2nd level cache hits in the shared state.
2771 Count 2nd level cache hits in the exclusive state.
2773 Count 2nd level cache hits in the modified state.
2775 Count 3rd level cache hits in the shared state.
2777 Count 3rd level cache hits in the exclusive state.
2779 Count 3rd level cache hits in the modified state.
2781 Count 2nd level cache misses.
2783 Count 3rd level cache misses.
2785 Count write-back lookups from the data access cache that miss the 2nd
2789 The default is to count all the above events.
2790 .It Li p4-execution-event Op Li ,mask= Ns Ar flags
2792 Count the retirement of tagged uops selected through the execution
2796 can contain the following strings separated by
2800 .Bl -tag -width indent -compact
2801 .It Li nbogus0 , Li nbogus1 , Li nbogus2 , Li nbogus3
2802 The marked uops are not bogus.
2803 .It Li bogus0 , Li bogus1 , Li bogus2 , Li bogus3
2804 The marked uops are bogus.
2807 This event requires additional (upstream) events to be allocated to
2808 perform the desired uop tagging.
2809 The default is to set all the above flags.
2810 This event can be used for precise event based sampling.
2811 .It Li p4-front-end-event Op Li ,mask= Ns Ar flags
2813 Count the retirement of tagged uops selected through the front-end
2817 can contain the following strings separated by
2821 .Bl -tag -width indent -compact
2823 The marked uops are not bogus.
2825 The marked uops are bogus.
2828 This event requires additional (upstream) events to be allocated to
2829 perform the desired uop tagging.
2830 The default is to select both kinds of events.
2831 This event can be used for precise event based sampling.
2832 .It Li p4-fsb-data-activity Op Li ,mask= Ns Ar flags
2834 Count each DBSY or DRDY event selected by qualifier
2840 separated set of the following flags:
2842 .Bl -tag -width indent -compact
2844 Count when this processor is driving data onto the bus.
2846 Count when this processor is reading data from the bus.
2848 Count when data is on the bus but not being sampled by this processor.
2850 Count when this processor reserves the bus for use in the next cycle
2851 in order to drive data.
2853 Count when some agent reserves the bus for use in the next bus cycle
2854 to drive data that this processor will sample.
2856 Count when some agent reserves the bus for use in the next bus cycle
2857 to drive data that this processor will not sample.
2864 are mutually exclusive.
2869 are mutually exclusive.
2870 The default value for
2873 .Dq Li drdy-drv+drdy-own+dbsy-drv+dbsy-own .
2874 .It Li p4-global-power-events Op Li ,mask= Ns Ar flags
2876 Count cycles during which the processor is not stopped.
2879 can take the following value (which is also the default):
2881 .Bl -tag -width indent -compact
2883 Count cycles when the processor is active.
2886 .It Li p4-instr-retired Op Li ,mask= Ns Ar flags
2888 Count instructions retired during a clock cycle.
2891 comprises of the following strings separated by
2895 .Bl -tag -width indent -compact
2897 Count non-bogus instructions that are not tagged.
2899 Count non-bogus instructions that are tagged.
2901 Count bogus instructions that are not tagged.
2903 Count bogus instructions that are tagged.
2906 The default qualifier counts all the above kinds of instructions.
2907 .It Li p4-ioq-active-entries Xo
2908 .Op Li ,mask= Ns Ar qualifier
2909 .Op Li ,busreqtype= Ns Ar req-type
2912 Count the number of entries (clipped at 15) in the IOQ that are
2914 The event masks are specified by qualifier
2923 separated set of the following flags:
2925 .Bl -tag -width indent -compact
2929 Count write entries.
2931 Count entries accessing uncacheable memory.
2933 Count entries accessing write-combining memory.
2935 Count entries accessing write-through memory.
2937 Count entries accessing write-protected memory
2939 Count entries accessing write-back memory.
2941 Count store requests driven by the processor (i.e., not by other
2942 processors or by DMA).
2944 Count store requests driven by other processors or by DMA.
2946 Include hardware and software prefetch requests in the count.
2949 The default value for
2951 is to enable all the above flags.
2955 qualifier is a 5-bit number can be additionally used to select a
2956 specific bus request type.
2961 qualifier should not be used when counting cycles with this event.
2962 The exact behaviour of this event depends on the processor revision.
2963 .It Li p4-ioq-allocation Xo
2964 .Op Li ,mask= Ns Ar qualifier
2965 .Op Li ,busreqtype= Ns Ar req-type
2968 Count various types of transactions on the bus matching the flags set
2978 separated set of the following flags:
2980 .Bl -tag -width indent -compact
2984 Count write entries.
2986 Count entries accessing uncacheable memory.
2988 Count entries accessing write-combining memory.
2990 Count entries accessing write-through memory.
2992 Count entries accessing write-protected memory
2994 Count entries accessing write-back memory.
2996 Count store requests driven by the processor (i.e., not by other
2997 processors or by DMA).
2999 Count store requests driven by other processors or by DMA.
3001 Include hardware and software prefetch requests in the count.
3004 The default value for
3006 is to enable all the above flags.
3010 qualifier is a 5-bit number can be additionally used to select a
3011 specific bus request type.
3016 qualifier is normally used with this event to prevent multiple
3018 The exact behaviour of this event depends on the processor revision.
3019 .It Li p4-itlb-reference Op mask= Ns Ar qualifier
3021 Count translations using the intruction translation look-aside
3025 argument is a list of the following strings separated by
3029 .Bl -tag -width indent -compact
3035 Count uncacheable ITLB hits.
3040 is specified the default is to count all the three kinds of ITLB
3042 .It Li p4-load-port-replay Op Li ,mask= Ns Ar qualifier
3044 Count replayed events at the load port.
3047 can take on one value:
3049 .Bl -tag -width indent -compact
3054 The default value for
3058 .It Li p4-mispred-branch-retired Op Li ,mask= Ns Ar flags
3060 Count mispredicted IA-32 branch instructions.
3063 can take the following value (which is also the default):
3065 .Bl -tag -width indent -compact
3067 Count non-bogus retired branch instructions.
3069 .It Li p4-machine-clear Op Li ,mask= Ns Ar flags
3071 Count the number of pipeline clears seen by the processor.
3074 is a list of the following strings separated by
3078 .Bl -tag -width indent -compact
3080 Count for a portion of the many cycles when the machine is being
3081 cleared for any reason.
3083 Count machine clears due to memory ordering issues.
3085 Count machine clears due to self-modifying code.
3090 to get a count of occurrences of machine clears.
3091 The default qualifier is
3093 .It Li p4-memory-cancel Op Li ,mask= Ns Ar event-list
3095 Count the cancelling of various kinds of requests in the data cache
3096 address control unit of the CPU.
3099 is a list of the following strings separated by
3103 .Bl -tag -width indent -compact
3105 Requests cancelled because no store request buffer was available.
3107 Requests that conflict due to 64K aliasing.
3112 is not specified, then the default is to count both kinds of events.
3113 .It Li p4-memory-complete Op Li ,mask= Ns Ar event-list
3115 Count the completion of load split, store split, uncacheable split and
3116 uncacheable load operations selected by qualifier
3122 separated list of the following flags:
3124 .Bl -tag -width indent -compact
3126 Count load splits completed, excluding loads from uncacheable or
3127 write-combining areas.
3129 Count any split stores completed.
3132 The default is to count both kinds of operations.
3133 .It Li p4-mob-load-replay Op Li ,mask= Ns Ar qualifier
3135 Count load replays triggered by the memory order buffer.
3140 separated list of the following flags:
3142 .Bl -tag -width indent -compact
3144 Count replays because of unknown store addresses.
3146 Count replays because of unknown store data.
3148 Count replays because of partially overlapped data accesses between
3149 load and store operations.
3151 Count replays because of mismatches in the lower 4 bits of load and
3155 The default qualifier is
3156 .Ar no-sta+no-std+partial-data+unalgn-addr .
3157 .It Li p4-packed-dp-uop Op Li ,mask= Ns Ar flags
3159 Count packed double-precision uops.
3162 can take the following value (which is also the default):
3164 .Bl -tag -width indent -compact
3166 Count all uops operating on packed double-precision operands.
3168 .It Li p4-packed-sp-uop Op Li ,mask= Ns Ar flags
3170 Count packed single-precision uops.
3173 can take the following value (which is also the default):
3175 .Bl -tag -width indent -compact
3177 Count all uops operating on packed single-precision operands.
3179 .It Li p4-page-walk-type Op Li ,mask= Ns Ar qualifier
3181 Count page walks performed by the page miss handler.
3186 separated list of the following keywords:
3188 .Bl -tag -width indent -compact
3190 Count page walks for data TLB misses.
3192 Count page walks for instruction TLB misses.
3195 The default value for
3198 .Dq Li dtmiss+itmiss .
3199 .It Li p4-replay-event Op Li ,mask= Ns Ar flags
3201 Count the retirement of tagged uops selected through the replay
3207 separated set of the following strings:
3209 .Bl -tag -width indent -compact
3211 The marked uops are not bogus.
3213 The marked uops are bogus.
3216 This event requires additional (upstream) events to be allocated to
3217 perform the desired uop tagging.
3218 The default qualifier counts both kinds of uops.
3219 This event can be used for precise event based sampling.
3220 .It Li p4-resource-stall Op Li ,mask= Ns Ar flags
3222 Count the occurrence or latency of stalls in the allocator.
3225 can take the following value (which is also the default):
3227 .Bl -tag -width indent -compact
3229 A stall due to the lack of store buffers.
3233 Count different types of responses.
3234 Further documentation on this event is not available.
3235 .It Li p4-retired-branch-type Op Li ,mask= Ns Ar flags
3237 Count branches retired.
3242 separated list of strings:
3244 .Bl -tag -width indent -compact
3246 Count conditional jumps.
3248 Count direct and indirect call branches.
3250 Count return branches.
3252 Count returns, indirect calls or indirect jumps.
3255 The default qualifier counts all the above branch types.
3256 .It Li p4-retired-mispred-branch-type Op Li ,mask= Ns Ar flags
3258 Count mispredicted branches retired.
3263 separated list of strings:
3265 .Bl -tag -width indent -compact
3267 Count conditional jumps.
3269 Count indirect call branches.
3271 Count return branches.
3273 Count returns, indirect calls or indirect jumps.
3276 The default qualifier counts all the above branch types.
3277 .It Li p4-scalar-dp-uop Op Li ,mask= Ns Ar flags
3279 Count the number of scalar double-precision uops.
3282 can take the following value (which is also the default):
3284 .Bl -tag -width indent -compact
3286 Count the number of scalar double-precision uops.
3288 .It Li p4-scalar-sp-uop Op Li ,mask= Ns Ar flags
3290 Count the number of scalar single-precision uops.
3293 can take the following value (which is also the default):
3295 .Bl -tag -width indent -compact
3297 Count all uops operating on scalar single-precision operands.
3301 Count snoop traffic.
3302 Further documentation on this event is not available.
3303 .It Li p4-sse-input-assist Op Li ,mask= Ns Ar flags
3305 Count the number of times an assist is required to handle problems
3306 with the operands for SSE and SSE2 operations.
3309 can take the following value (which is also the default):
3311 .Bl -tag -width indent -compact
3313 Count assists for all SSE and SSE2 uops.
3315 .It Li p4-store-port-replay Op Li ,mask= Ns Ar qualifier
3317 Count events replayed at the store port.
3320 can take on one value:
3322 .Bl -tag -width indent -compact
3327 The default value for
3331 .It Li p4-tc-deliver-mode Op Li ,mask= Ns Ar qualifier
3333 Count the duration in cycles of operating modes of the trace cache and
3335 The desired operating mode is selected by
3337 which is a list of the following strings separated by
3341 .Bl -tag -width indent -compact
3343 Both logical processors are in deliver mode.
3345 Logical processor 0 is in deliver mode while logical processor 1 is in
3348 Logical processor 0 is in deliver mode while logical processor 1 is
3349 halted, or in machine clear, or transitioning to a long microcode
3352 Logical processor 0 is in build mode while logical processor 1 is in
3355 Both logical processors are in build mode.
3357 Logical processor 0 is in build mode while logical processor 1 is
3358 halted, or in machine clear or transitioning to a long microcode
3361 Logical processor 0 is halted, or in machine clear or transitioning to
3362 a long microcode flow while logical processor 1 is in deliver mode.
3364 Logical processor 0 is halted, or in machine clear or transitioning to
3365 a long microcode flow while logical processor 1 is in build mode.
3368 If there is only one logical processor in the processor package then
3369 the qualifier for logical processor 1 is ignored.
3370 If no qualifier is specified, the default qualifier is
3371 .Dq Li DD+DB+DI+BD+BB+BI+ID+IB .
3372 .It Li p4-tc-ms-xfer Op Li ,mask= Ns Ar flags
3374 Count the number of times uop delivery changed from the trace cache to
3378 can take the following value (which is also the default):
3380 .Bl -tag -width indent -compact
3382 Count TC to MS transfers.
3384 .It Li p4-uop-queue-writes Op Li ,mask= Ns Ar flags
3386 Count the number of valid uops written to the uop queue.
3389 is a list of the following strings, separated by
3393 .Bl -tag -width indent -compact
3394 .It Li from-tc-build
3395 Count uops being written from the trace cache in build mode.
3396 .It Li from-tc-deliver
3397 Count uops being written from the trace cache in deliver mode.
3399 Count uops being written from microcode ROM.
3402 The default qualifier counts all the above kinds of uops.
3403 .It Li p4-uop-type Op Li ,mask= Ns Ar flags
3405 This event is used in conjunction with the front-end at-retirement
3406 mechanism to tag load and store uops.
3409 comprises the following strings separated by
3413 .Bl -tag -width indent -compact
3415 Mark uops that are load operations.
3417 Mark uops that are store operations.
3420 The default qualifier counts both kinds of uops.
3421 .It Li p4-uops-retired Op Li ,mask= Ns Ar flags
3423 Count uops retired during a clock cycle.
3426 comprises the following strings separated by
3430 .Bl -tag -width indent -compact
3432 Count marked uops that are not bogus.
3434 Count marked uops that are bogus.
3437 The default qualifier counts both kinds of uops.
3438 .It Li p4-wc-buffer Op Li ,mask= Ns Ar flags
3440 Count write-combining buffer operations.
3443 contains the following strings separated by
3447 .Bl -tag -width indent -compact
3449 WC buffer evictions due to any cause.
3450 .It Li wcb-full-evict
3451 WC buffer evictions due to no WC buffer being available.
3454 The default qualifer counts both kinds of evictions.
3455 .It Li p4-x87-assist Op Li ,mask= Ns Ar flags
3457 Count the retirement of x87 instructions that required special
3461 contains the following strings separated by
3465 .Bl -tag -width indent -compact
3467 Count instructions that saw an FP stack underflow.
3469 Count instructions that saw an FP stack overflow.
3471 Count instructions that saw an x87 output overflow.
3473 Count instructions that saw an x87 output underflow.
3475 Count instructions that needed an x87 input assist.
3478 The default qualifier counts all the above types of instruction
3480 .It Li p4-x87-fp-uop Op Li ,mask= Ns Ar flags
3482 Count x87 floating-point uops.
3485 can take the following value (which is also the default):
3487 .Bl -tag -width indent -compact
3489 Count all x87 floating-point uops.
3492 If an instruction contains more than one x87 floating-point uops, then
3493 all x87 floating-point uops will be counted.
3494 This event does not count x87 floating-point data movement operations.
3495 .It Li p4-x87-simd-moves-uop Op Li ,mask= Ns Ar flags
3497 Count each x87 FPU, MMX, SSE, or SSE2 uops that load data or store
3498 data or perform register-to-register moves.
3499 This event does not count integer move uops.
3502 may contain the following keywords separated by
3506 .Bl -tag -width indent -compact
3508 Count all x87 and SIMD store and move uops.
3510 Count all x87 and SIMD load uops.
3513 The default is to count all uops.
3515 This event may be affected by processor errata N43.
3517 .Ss "Cascading P4 PMCs"
3518 PMC cascading support is currently poorly implemented.
3519 While individual event counters may be allocated with a
3521 qualifier, the current API does not offer the ability
3522 to name and allocate all the resources needed for a
3523 cascaded event counter pair in a single operation.
3524 .Ss "Precise Event Based Sampling"
3525 Support for precise event based sampling is currently
3528 The interface between the
3532 driver is intended to be private to the implementation and may
3534 In order to ease forward compatibility with future versions of the
3536 driver, applications are urged to dynamically link with the
3552 library first appeared in
3557 library was written by
3559 .Aq jkoshy@FreeBSD.org .