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31 .Nd measurement events for
33 .Tn Core i7 and Xeon 5500
42 CPUs contain PMCs conforming to version 2 of the
44 performance measurement architecture.
45 These CPUs may contain up to three classes of PMCs:
46 .Bl -tag -width "Li PMC_CLASS_IAP"
48 Fixed-function counters that count only one hardware event per counter.
50 Programmable counters that may be configured to count one of a defined
51 set of hardware events.
54 The number of PMCs available in each class and their widths need to be
55 determined at run time by calling
58 Intel Core i7 and Xeon 5500 PMCs are documented in
60 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
61 .%T "Volume 3B: System Programming Guide, Part 2"
62 .%N "Order Number: 253669-033US"
64 .%Q "Intel Corporation"
66 .Ss COREI7 AND XEON 5500 FIXED FUNCTION PMCS
67 These PMCs and their supported events are documented in
69 Not all CPUs in this family implement fixed-function counters.
70 .Ss COREI7 AND XEON 5500 PROGRAMMABLE PMCS
71 The programmable PMCs support the following capabilities:
72 .Bl -column "PMC_CAP_INTERRUPT" "Support"
73 .It Em Capability Ta Em Support
74 .It PMC_CAP_CASCADE Ta \&No
75 .It PMC_CAP_EDGE Ta Yes
76 .It PMC_CAP_INTERRUPT Ta Yes
77 .It PMC_CAP_INVERT Ta Yes
78 .It PMC_CAP_READ Ta Yes
79 .It PMC_CAP_PRECISE Ta \&No
80 .It PMC_CAP_SYSTEM Ta Yes
81 .It PMC_CAP_TAGGING Ta \&No
82 .It PMC_CAP_THRESHOLD Ta Yes
83 .It PMC_CAP_USER Ta Yes
84 .It PMC_CAP_WRITE Ta Yes
87 Event specifiers for these PMCs support the following common
89 .Bl -tag -width indent
90 .It Li rsp= Ns Ar value
91 Configure the Off-core Response bits.
92 .Bl -tag -width indent
94 Counts the number of demand and DCU prefetch data reads of full
95 and partial cachelines as well as demand data page table entry
96 cacheline reads. Does not count L2 data read prefetches or
99 Counts the number of demand and DCU prefetch reads for ownership
100 (RFO) requests generated by a write to data cacheline. Does not
103 Counts the number of demand and DCU prefetch instruction cacheline
104 reads. Does not count L2 code read prefetches.
106 Counts the number of writeback (modified to exclusive) transactions.
108 Counts the number of data cacheline reads generated by L2 prefetchers.
110 Counts the number of RFO requests generated by L2 prefetchers.
112 Counts the number of code reads generated by L2 prefetchers.
114 Counts one of the following transaction types, including L3 invalidate,
115 I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences,
116 lock, unlock, split lock.
118 L3 Hit: local or remote home requests that hit L3 cache in the uncore
119 with no coherency actions required (snooping).
120 .It Li OTHER_CORE_HIT_SNP
121 L3 Hit: local or remote home requests that hit L3 cache in the uncore
122 and was serviced by another core with a cross core snoop where no modified
123 copies were found (clean).
124 .It Li OTHER_CORE_HITM
125 L3 Hit: local or remote home requests that hit L3 cache in the uncore
126 and was serviced by another core with a cross core snoop where modified
127 copies were found (HITM).
128 .It Li REMOTE_CACHE_FWD
129 L3 Miss: local homed requests that missed the L3 cache and was serviced
130 by forwarded data following a cross package snoop where no modified
131 copies found. (Remote home requests are not counted)
133 L3 Miss: remote home requests that missed the L3 cache and were serviced
136 L3 Miss: local home requests that missed the L3 cache and were serviced
139 Non-DRAM requests that were serviced by IOH.
141 .It Li cmask= Ns Ar value
142 Configure the PMC to increment only if the number of configured
143 events measured in a cycle is greater than or equal to
146 Configure the PMC to count the number of de-asserted to asserted
147 transitions of the conditions expressed by the other qualifiers.
148 If specified, the counter will increment only once whenever a
149 condition becomes true, irrespective of the number of clocks during
150 which the condition remains true.
152 Invert the sense of comparison when the
154 qualifier is present, making the counter increment when the number of
155 events per cycle is less than the value specified by the
159 Configure the PMC to count events happening at processor privilege
162 Configure the PMC to count events occurring at privilege levels 1, 2
170 qualifiers are specified, the default is to enable both.
171 .Ss Event Specifiers (Programmable PMCs)
172 Core i7 and Xeon 5500 programmable PMCs support the following events:
173 .Bl -tag -width indent
175 .Pq Event 04H , Umask 07H
176 Counts the number of store buffer drains.
177 .It Li STORE_BLOCKS.AT_RET
178 .Pq Event 06H , Umask 04H
179 Counts number of loads delayed with at-Retirement block code. The following
180 loads need to be executed at retirement and wait for all senior stores on
181 the same thread to be drained: load splitting across 4K boundary (page
182 split), load accessing uncacheable (UC or USWC) memory, load lock, and load
183 with page table in UC or USWC memory region.
184 .It Li STORE_BLOCKS.L1D_BLOCK
185 .Pq Event 06H , Umask 08H
186 Cacheable loads delayed with L1D block code
187 .It Li PARTIAL_ADDRESS_ALIAS
188 .Pq Event 07H , Umask 01H
189 Counts false dependency due to partial address aliasing
190 .It Li DTLB_LOAD_MISSES.ANY
191 .Pq Event 08H , Umask 01H
192 Counts all load misses that cause a page walk
193 .It Li DTLB_LOAD_MISSES.WALK_COMPLETED
194 .Pq Event 08H , Umask 02H
195 Counts number of completed page walks due to load miss in the STLB.
196 .It Li DTLB_LOAD_MISSES.STLB_HIT
197 .Pq Event 08H , Umask 10H
198 Number of cache load STLB hits
199 .It Li DTLB_LOAD_MISSES.PDE_MISS
200 .Pq Event 08H , Umask 20H
201 Number of DTLB cache load misses where the low part of the linear to
202 physical address translation was missed.
203 .It Li DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED
204 .Pq Event 08H , Umask 80H
205 Counts number of completed large page walks due to load miss in the STLB.
206 .It Li MEM_INST_RETIRED.LOADS
207 .Pq Event 0BH , Umask 01H
208 Counts the number of instructions with an architecturally-visible store
209 retired on the architected path.
210 In conjunction with ld_lat facility
211 .It Li MEM_INST_RETIRED.STORES
212 .Pq Event 0BH , Umask 02H
213 Counts the number of instructions with an architecturally-visible store
214 retired on the architected path.
215 In conjunction with ld_lat facility
216 .It Li MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD
217 .Pq Event 0BH , Umask 10H
218 Counts the number of instructions exceeding the latency specified with
220 In conjunction with ld_lat facility
221 .It Li MEM_STORE_RETIRED.DTLB_MISS
222 .Pq Event 0CH , Umask 01H
223 The event counts the number of retired stores that missed the DTLB. The DTLB
224 miss is not counted if the store operation causes a fault. Does not counter
225 prefetches. Counts both primary and secondary misses to the TLB
226 .It Li UOPS_ISSUED.ANY
227 .Pq Event 0EH , Umask 01H
228 Counts the number of Uops issued by the Register Allocation Table to the
229 Reservation Station, i.e. the UOPs issued from the front end to the back
231 .It Li UOPS_ISSUED.STALLED_CYCLES
232 .Pq Event 0EH , Umask 01H
233 Counts the number of cycles no Uops issued by the Register Allocation Table
234 to the Reservation Station, i.e. the UOPs issued from the front end to the
236 set invert=1, cmask = 1
237 .It Li UOPS_ISSUED.FUSED
238 .Pq Event 0EH , Umask 02H
239 Counts the number of fused Uops that were issued from the Register
240 Allocation Table to the Reservation Station.
241 .It Li MEM_UNCORE_RETIRED.L3_DATA_MISS_UNKNOWN
242 .Pq Event 0FH , Umask 01H
243 Counts number of memory load instructions retired where the memory reference
244 missed L3 and data source is unknown.
245 Available only for CPUID signature 06_2EH
246 .It Li MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM
247 .Pq Event 0FH , Umask 02H
248 Counts number of memory load instructions retired where the memory reference
249 hit modified data in a sibling core residing on the same socket.
250 .It Li MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT
251 .Pq Event 0FH , Umask 08H
252 Counts number of memory load instructions retired where the memory reference
253 missed the L1, L2 and L3 caches and HIT in a remote socket's cache. Only
254 counts locally homed lines.
255 .It Li MEM_UNCORE_RETIRED.REMOTE_DRAM
256 .Pq Event 0FH , Umask 10H
257 Counts number of memory load instructions retired where the memory reference
258 missed the L1, L2 and L3 caches and was remotely homed. This includes both
259 DRAM access and HITM in a remote socket's cache for remotely homed lines.
260 .It Li MEM_UNCORE_RETIRED.LOCAL_DRAM
261 .Pq Event 0FH , Umask 20H
262 Counts number of memory load instructions retired where the memory reference
263 missed the L1, L2 and L3 caches and required a local socket memory
264 reference. This includes locally homed cachelines that were in a modified
265 state in another socket.
266 .It Li MEM_UNCORE_RETIRED.UNCACHEABLE
267 .Pq Event 0FH , Umask 80H
268 Counts number of memory load instructions retired where the memory reference
269 missed the L1, L2 and L3 caches and to perform I/O.
270 Available only for CPUID signature 06_2EH
271 .It Li FP_COMP_OPS_EXE.X87
272 .Pq Event 10H , Umask 01H
273 Counts the number of FP Computational Uops Executed. The number of FADD,
274 FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer
275 DIVs, and IDIVs. This event does not distinguish an FADD used in the middle
276 of a transcendental flow from a separate FADD instruction.
277 .It Li FP_COMP_OPS_EXE.MMX
278 .Pq Event 10H , Umask 02H
279 Counts number of MMX Uops executed.
280 .It Li FP_COMP_OPS_EXE.SSE_FP
281 .Pq Event 10H , Umask 04H
282 Counts number of SSE and SSE2 FP uops executed.
283 .It Li FP_COMP_OPS_EXE.SSE2_INTEGER
284 .Pq Event 10H , Umask 08H
285 Counts number of SSE2 integer uops executed.
286 .It Li FP_COMP_OPS_EXE.SSE_FP_PACKED
287 .Pq Event 10H , Umask 10H
288 Counts number of SSE FP packed uops executed.
289 .It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR
290 .Pq Event 10H , Umask 20H
291 Counts number of SSE FP scalar uops executed.
292 .It Li FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION
293 .Pq Event 10H , Umask 40H
294 Counts number of SSE* FP single precision uops executed.
295 .It Li FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION
296 .Pq Event 10H , Umask 80H
297 Counts number of SSE* FP double precision uops executed.
298 .It Li SIMD_INT_128.PACKED_MPY
299 .Pq Event 12H , Umask 01H
300 Counts number of 128 bit SIMD integer multiply operations.
301 .It Li SIMD_INT_128.PACKED_SHIFT
302 .Pq Event 12H , Umask 02H
303 Counts number of 128 bit SIMD integer shift operations.
304 .It Li SIMD_INT_128.PACK
305 .Pq Event 12H , Umask 04H
306 Counts number of 128 bit SIMD integer pack operations.
307 .It Li SIMD_INT_128.UNPACK
308 .Pq Event 12H , Umask 08H
309 Counts number of 128 bit SIMD integer unpack operations.
310 .It Li SIMD_INT_128.PACKED_LOGICAL
311 .Pq Event 12H , Umask 10H
312 Counts number of 128 bit SIMD integer logical operations.
313 .It Li SIMD_INT_128.PACKED_ARITH
314 .Pq Event 12H , Umask 20H
315 Counts number of 128 bit SIMD integer arithmetic operations.
316 .It Li SIMD_INT_128.SHUFFLE_MOVE
317 .Pq Event 12H , Umask 40H
318 Counts number of 128 bit SIMD integer shuffle and move operations.
319 .It Li LOAD_DISPATCH.RS
320 .Pq Event 13H , Umask 01H
321 Counts number of loads dispatched from the Reservation Station that bypass
322 the Memory Order Buffer.
323 .It Li LOAD_DISPATCH.RS_DELAYED
324 .Pq Event 13H , Umask 02H
325 Counts the number of delayed RS dispatches at the stage latch. If an RS
326 dispatch can not bypass to LB, it has another chance to dispatch from the
327 one-cycle delayed staging latch before it is written into the LB.
328 .It Li LOAD_DISPATCH.MOB
329 .Pq Event 13H , Umask 04H
330 Counts the number of loads dispatched from the Reservation Station to the
332 .It Li LOAD_DISPATCH.ANY
333 .Pq Event 13H , Umask 07H
334 Counts all loads dispatched from the Reservation Station.
335 .It Li ARITH.CYCLES_DIV_BUSY
336 .Pq Event 14H , Umask 01H
337 Counts the number of cycles the divider is busy executing divide or square
338 root operations. The divide can be integer, X87 or Streaming SIMD Extensions
339 (SSE). The square root operation can be either X87 or SSE.
340 Set 'edge =1, invert=1, cmask=1' to count the number of divides.
341 Count may be incorrect When SMT is on.
343 .Pq Event 14H , Umask 02H
344 Counts the number of multiply operations executed. This includes integer as
345 well as floating point multiply operations but excludes DPPS mul and MPSAD.
346 Count may be incorrect When SMT is on
347 .It Li INST_QUEUE_WRITES
348 .Pq Event 17H , Umask 01H
349 Counts the number of instructions written into the instruction queue every
351 .It Li INST_DECODED.DEC0
352 .Pq Event 18H , Umask 01H
353 Counts number of instructions that require decoder 0 to be decoded. Usually,
354 this means that the instruction maps to more than 1 uop
355 .It Li TWO_UOP_INSTS_DECODED
356 .Pq Event 19H , Umask 01H
357 An instruction that generates two uops was decoded
358 .It Li INST_QUEUE_WRITE_CYCLES
359 .Pq Event 1EH , Umask 01H
360 This event counts the number of cycles during which instructions are written
361 to the instruction queue. Dividing this counter by the number of
362 instructions written to the instruction queue (INST_QUEUE_WRITES) yields the
363 average number of instructions decoded each cycle. If this number is less
364 than four and the pipe stalls, this indicates that the decoder is failing to
365 decode enough instructions per cycle to sustain the 4-wide pipeline.
366 If SSE* instructions that are 6 bytes or longer arrive one after another,
367 then front end throughput may limit execution speed. In such case,
369 .Pq Event 20H , Umask 01H
370 Counts number of loops that cant stream from the instruction queue.
371 .It Li L2_RQSTS.LD_HIT
372 .Pq Event 24H , Umask 01H
373 Counts number of loads that hit the L2 cache. L2 loads include both L1D
374 demand misses as well as L1D prefetches. L2 loads can be rejected for
375 various reasons. Only non rejected loads are counted.
376 .It Li L2_RQSTS.LD_MISS
377 .Pq Event 24H , Umask 02H
378 Counts the number of loads that miss the L2 cache. L2 loads include both L1D
379 demand misses as well as L1D prefetches.
380 .It Li L2_RQSTS.LOADS
381 .Pq Event 24H , Umask 03H
382 Counts all L2 load requests. L2 loads include both L1D demand misses as well
384 .It Li L2_RQSTS.RFO_HIT
385 .Pq Event 24H , Umask 04H
386 Counts the number of store RFO requests that hit the L2 cache. L2 RFO
387 requests include both L1D demand RFO misses as well as L1D RFO prefetches.
388 Count includes WC memory requests, where the data is not fetched but the
389 permission to write the line is required.
390 .It Li L2_RQSTS.RFO_MISS
391 .Pq Event 24H , Umask 08H
392 Counts the number of store RFO requests that miss the L2 cache. L2 RFO
393 requests include both L1D demand RFO misses as well as L1D RFO prefetches.
395 .Pq Event 24H , Umask 0CH
396 Counts all L2 store RFO requests. L2 RFO requests include both L1D demand
397 RFO misses as well as L1D RFO prefetches.
398 .It Li L2_RQSTS.IFETCH_HIT
399 .Pq Event 24H , Umask 10H
400 Counts number of instruction fetches that hit the L2 cache. L2 instruction
401 fetches include both L1I demand misses as well as L1I instruction
403 .It Li L2_RQSTS.IFETCH_MISS
404 .Pq Event 24H , Umask 20H
405 Counts number of instruction fetches that miss the L2 cache. L2 instruction
406 fetches include both L1I demand misses as well as L1I instruction
408 .It Li L2_RQSTS.IFETCHES
409 .Pq Event 24H , Umask 30H
410 Counts all instruction fetches. L2 instruction fetches include both L1I
411 demand misses as well as L1I instruction prefetches.
412 .It Li L2_RQSTS.PREFETCH_HIT
413 .Pq Event 24H , Umask 40H
414 Counts L2 prefetch hits for both code and data.
415 .It Li L2_RQSTS.PREFETCH_MISS
416 .Pq Event 24H , Umask 80H
417 Counts L2 prefetch misses for both code and data.
418 .It Li L2_RQSTS.PREFETCHES
419 .Pq Event 24H , Umask C0H
420 Counts all L2 prefetches for both code and data.
422 .Pq Event 24H , Umask AAH
423 Counts all L2 misses for both code and data.
424 .It Li L2_RQSTS.REFERENCES
425 .Pq Event 24H , Umask FFH
426 Counts all L2 requests for both code and data.
427 .It Li L2_DATA_RQSTS.DEMAND.I_STATE
428 .Pq Event 26H , Umask 01H
429 Counts number of L2 data demand loads where the cache line to be loaded is
430 in the I (invalid) state, i.e. a cache miss. L2 demand loads are both L1D
431 demand misses and L1D prefetches.
432 .It Li L2_DATA_RQSTS.DEMAND.S_STATE
433 .Pq Event 26H , Umask 02H
434 Counts number of L2 data demand loads where the cache line to be loaded is
435 in the S (shared) state. L2 demand loads are both L1D demand misses and L1D
437 .It Li L2_DATA_RQSTS.DEMAND.E_STATE
438 .Pq Event 26H , Umask 04H
439 Counts number of L2 data demand loads where the cache line to be loaded is
440 in the E (exclusive) state. L2 demand loads are both L1D demand misses and
442 .It Li L2_DATA_RQSTS.DEMAND.M_STATE
443 .Pq Event 26H , Umask 08H
444 Counts number of L2 data demand loads where the cache line to be loaded is
445 in the M (modified) state. L2 demand loads are both L1D demand misses and
447 .It Li L2_DATA_RQSTS.DEMAND.MESI
448 .Pq Event 26H , Umask 0FH
449 Counts all L2 data demand requests. L2 demand loads are both L1D demand
450 misses and L1D prefetches.
451 .It Li L2_DATA_RQSTS.PREFETCH.I_STATE
452 .Pq Event 26H , Umask 10H
453 Counts number of L2 prefetch data loads where the cache line to be loaded is
454 in the I (invalid) state, i.e. a cache miss.
455 .It Li L2_DATA_RQSTS.PREFETCH.S_STATE
456 .Pq Event 26H , Umask 20H
457 Counts number of L2 prefetch data loads where the cache line to be loaded is
458 in the S (shared) state. A prefetch RFO will miss on an S state line, while
459 a prefetch read will hit on an S state line.
460 .It Li L2_DATA_RQSTS.PREFETCH.E_STATE
461 .Pq Event 26H , Umask 40H
462 Counts number of L2 prefetch data loads where the cache line to be loaded is
463 in the E (exclusive) state.
464 .It Li L2_DATA_RQSTS.PREFETCH.M_STATE
465 .Pq Event 26H , Umask 80H
466 Counts number of L2 prefetch data loads where the cache line to be loaded is
467 in the M (modified) state.
468 .It Li L2_DATA_RQSTS.PREFETCH.MESI
469 .Pq Event 26H , Umask F0H
470 Counts all L2 prefetch requests.
471 .It Li L2_DATA_RQSTS.ANY
472 .Pq Event 26H , Umask FFH
473 Counts all L2 data requests.
474 .It Li L2_WRITE.RFO.I_STATE
475 .Pq Event 27H , Umask 01H
476 Counts number of L2 demand store RFO requests where the cache line to be
477 loaded is in the I (invalid) state, i.e, a cache miss. The L1D prefetcher
478 does not issue a RFO prefetch.
479 This is a demand RFO request
480 .It Li L2_WRITE.RFO.S_STATE
481 .Pq Event 27H , Umask 02H
482 Counts number of L2 store RFO requests where the cache line to be loaded is
483 in the S (shared) state. The L1D prefetcher does not issue a RFO prefetch,.
484 This is a demand RFO request
485 .It Li L2_WRITE.RFO.M_STATE
486 .Pq Event 27H , Umask 08H
487 Counts number of L2 store RFO requests where the cache line to be loaded is
488 in the M (modified) state. The L1D prefetcher does not issue a RFO prefetch.
489 This is a demand RFO request
490 .It Li L2_WRITE.RFO.HIT
491 .Pq Event 27H , Umask 0EH
492 Counts number of L2 store RFO requests where the cache line to be loaded is
493 in either the S, E or M states. The L1D prefetcher does not issue a RFO
495 This is a demand RFO request
496 .It Li L2_WRITE.RFO.MESI
497 .Pq Event 27H , Umask 0FH
498 Counts all L2 store RFO requests.The L1D prefetcher does not issue a RFO
500 This is a demand RFO request
501 .It Li L2_WRITE.LOCK.I_STATE
502 .Pq Event 27H , Umask 10H
503 Counts number of L2 demand lock RFO requests where the cache line to be
504 loaded is in the I (invalid) state, i.e. a cache miss.
505 .It Li L2_WRITE.LOCK.S_STATE
506 .Pq Event 27H , Umask 20H
507 Counts number of L2 lock RFO requests where the cache line to be loaded is
508 in the S (shared) state.
509 .It Li L2_WRITE.LOCK.E_STATE
510 .Pq Event 27H , Umask 40H
511 Counts number of L2 demand lock RFO requests where the cache line to be
512 loaded is in the E (exclusive) state.
513 .It Li L2_WRITE.LOCK.M_STATE
514 .Pq Event 27H , Umask 80H
515 Counts number of L2 demand lock RFO requests where the cache line to be
516 loaded is in the M (modified) state.
517 .It Li L2_WRITE.LOCK.HIT
518 .Pq Event 27H , Umask E0H
519 Counts number of L2 demand lock RFO requests where the cache line to be
520 loaded is in either the S, E, or M state.
521 .It Li L2_WRITE.LOCK.MESI
522 .Pq Event 27H , Umask F0H
523 Counts all L2 demand lock RFO requests.
524 .It Li L1D_WB_L2.I_STATE
525 .Pq Event 28H , Umask 01H
526 Counts number of L1 writebacks to the L2 where the cache line to be written
527 is in the I (invalid) state, i.e. a cache miss.
528 .It Li L1D_WB_L2.S_STATE
529 .Pq Event 28H , Umask 02H
530 Counts number of L1 writebacks to the L2 where the cache line to be written
532 .It Li L1D_WB_L2.E_STATE
533 .Pq Event 28H , Umask 04H
534 Counts number of L1 writebacks to the L2 where the cache line to be written
535 is in the E (exclusive) state.
536 .It Li L1D_WB_L2.M_STATE
537 .Pq Event 28H , Umask 08H
538 Counts number of L1 writebacks to the L2 where the cache line to be written
539 is in the M (modified) state.
540 .It Li L1D_WB_L2.MESI
541 .Pq Event 28H , Umask 0FH
542 Counts all L1 writebacks to the L2.
543 .It Li L3_LAT_CACHE.REFERENCE
544 .Pq Event 2EH , Umask 4FH
545 This event counts requests originating from the core that reference a cache
546 line in the last level cache. The event count includes speculative traffic
547 but excludes cache line fills due to a L2 hardware-prefetch. Because cache
548 hierarchy, cache sizes and other implementation-specific characteristics;
549 value comparison to estimate performance differences is not recommended.
551 .It Li L3_LAT_CACHE.MISS
552 .Pq Event 2EH , Umask 41H
553 This event counts each cache miss condition for references to the last level
554 cache. The event count may include speculative traffic but excludes cache
555 line fills due to L2 hardware-prefetches. Because cache hierarchy, cache
556 sizes and other implementation-specific characteristics; value comparison to
557 estimate performance differences is not recommended.
559 .It Li CPU_CLK_UNHALTED.THREAD_P
560 .Pq Event 3CH , Umask 00H
561 Counts the number of thread cycles while the thread is not in a halt state.
562 The thread enters the halt state when it is running the HLT instruction. The
563 core frequency may change from time to time due to power or thermal
566 .It Li CPU_CLK_UNHALTED.REF_P
567 .Pq Event 3CH , Umask 01H
568 Increments at the frequency of TSC when not halted.
570 .It Li L1D_CACHE_LD.I_STATE
571 .Pq Event 40H , Umask 01H
572 Counts L1 data cache read requests where the cache line to be loaded is in
573 the I (invalid) state, i.e. the read request missed the cache.
575 .It Li L1D_CACHE_LD.S_STATE
576 .Pq Event 40H , Umask 02H
577 Counts L1 data cache read requests where the cache line to be loaded is in
578 the S (shared) state.
580 .It Li L1D_CACHE_LD.E_STATE
581 .Pq Event 40H , Umask 04H
582 Counts L1 data cache read requests where the cache line to be loaded is in
583 the E (exclusive) state.
585 .It Li L1D_CACHE_LD.M_STATE
586 .Pq Event 40H , Umask 08H
587 Counts L1 data cache read requests where the cache line to be loaded is in
588 the M (modified) state.
590 .It Li L1D_CACHE_LD.MESI
591 .Pq Event 40H , Umask 0FH
592 Counts L1 data cache read requests.
594 .It Li L1D_CACHE_ST.S_STATE
595 .Pq Event 41H , Umask 02H
596 Counts L1 data cache store RFO requests where the cache line to be loaded is
597 in the S (shared) state.
599 .It Li L1D_CACHE_ST.E_STATE
600 .Pq Event 41H , Umask 04H
601 Counts L1 data cache store RFO requests where the cache line to be loaded is
602 in the E (exclusive) state.
604 .It Li L1D_CACHE_ST.M_STATE
605 .Pq Event 41H , Umask 08H
606 Counts L1 data cache store RFO requests where cache line to be loaded is in
607 the M (modified) state.
609 .It Li L1D_CACHE_LOCK.HIT
610 .Pq Event 42H , Umask 01H
611 Counts retired load locks that hit in the L1 data cache or hit in an already
612 allocated fill buffer. The lock portion of the load lock transaction must
614 The initial load will pull the lock into the L1 data cache. Counter 0, 1
616 .It Li L1D_CACHE_LOCK.S_STATE
617 .Pq Event 42H , Umask 02H
618 Counts L1 data cache retired load locks that hit the target cache line in
621 .It Li L1D_CACHE_LOCK.E_STATE
622 .Pq Event 42H , Umask 04H
623 Counts L1 data cache retired load locks that hit the target cache line in
626 .It Li L1D_CACHE_LOCK.M_STATE
627 .Pq Event 42H , Umask 08H
628 Counts L1 data cache retired load locks that hit the target cache line in
631 .It Li L1D_ALL_REF.ANY
632 .Pq Event 43H , Umask 01H
633 Counts all references (uncached, speculated and retired) to the L1 data
634 cache, including all loads and stores with any memory types. The event
635 counts memory accesses only when they are actually performed. For example, a
636 load blocked by unknown store address and later performed is only counted
638 The event does not include non- memory accesses, such as I/O accesses.
640 .It Li L1D_ALL_REF.CACHEABLE
641 .Pq Event 43H , Umask 02H
642 Counts all data reads and writes (speculated and retired) from cacheable
643 memory, including locked operations.
645 .It Li DTLB_MISSES.ANY
646 .Pq Event 49H , Umask 01H
647 Counts the number of misses in the STLB which causes a page walk.
648 .It Li DTLB_MISSES.WALK_COMPLETED
649 .Pq Event 49H , Umask 02H
650 Counts number of misses in the STLB which resulted in a completed page walk.
651 .It Li DTLB_MISSES.STLB_HIT
652 .Pq Event 49H , Umask 10H
653 Counts the number of DTLB first level misses that hit in the second level
654 TLB. This event is only relevant if the core contains multiple DTLB levels.
655 .It Li DTLB_MISSES.PDE_MISS
656 .Pq Event 49H , Umask 20H
657 Number of DTLB misses caused by low part of address, includes references to 2M pages because 2M pages do not use the PDE.
658 .It Li DTLB_MISSES.LARGE_WALK_COMPLETED
659 .Pq Event 49H , Umask 80H
660 Counts number of misses in the STLB which resulted in a completed page walk for large pages.
662 .Pq Event 4CH , Umask 01H
663 Counts load operations sent to the L1 data cache while a previous SSE
664 prefetch instruction to the same cache line has started prefetching but has
666 .It Li L1D_PREFETCH.REQUESTS
667 .Pq Event 4EH , Umask 01H
668 Counts number of hardware prefetch requests dispatched out of the prefetch
670 .It Li L1D_PREFETCH.MISS
671 .Pq Event 4EH , Umask 02H
672 Counts number of hardware prefetch requests that miss the L1D. There are two
673 prefetchers in the L1D. A streamer, which predicts lines sequentially after
674 this one should be fetched, and the IP prefetcher that remembers access
675 patterns for the current instruction. The streamer prefetcher stops on an
676 L1D hit, while the IP prefetcher does not.
677 .It Li L1D_PREFETCH.TRIGGERS
678 .Pq Event 4EH , Umask 04H
679 Counts number of prefetch requests triggered by the Finite State Machine and
680 pushed into the prefetch FIFO. Some of the prefetch requests are dropped due
681 to overwrites or competition between the IP index prefetcher and streamer
682 prefetcher. The prefetch FIFO contains 4 entries.
684 .Pq Event 51H , Umask 01H
685 Counts the number of lines brought into the L1 data cache.
688 .Pq Event 51H , Umask 02H
689 Counts the number of modified lines brought into the L1 data cache.
692 .Pq Event 51H , Umask 04H
693 Counts the number of modified lines evicted from the L1 data cache due to
696 .It Li L1D.M_SNOOP_EVICT
697 .Pq Event 51H , Umask 08H
698 Counts the number of modified lines evicted from the L1 data cache due to
699 snoop HITM intervention.
701 .It Li L1D_CACHE_PREFETCH_LOCK_FB_HIT
702 .Pq Event 52H , Umask 01H
703 Counts the number of cacheable load lock speculated instructions accepted
704 into the fill buffer.
705 .It Li L1D_CACHE_LOCK_FB_HIT
706 .Pq Event 53H , Umask 01H
707 Counts the number of cacheable load lock speculated or retired instructions
708 accepted into the fill buffer.
709 .It Li CACHE_LOCK_CYCLES.L1D_L2
710 .Pq Event 63H , Umask 01H
711 Cycle count during which the L1D and L2 are locked. A lock is asserted when
712 there is a locked memory access, due to uncacheable memory, a locked
713 operation that spans two cache lines, or a page walk from an uncacheable
715 Counter 0, 1 only. L1D and L2 locks have a very high performance penalty and
716 it is highly recommended to avoid such accesses.
717 .It Li CACHE_LOCK_CYCLES.L1D
718 .Pq Event 63H , Umask 02H
719 Counts the number of cycles that cacheline in the L1 data cache unit is
722 .It Li IO_TRANSACTIONS
723 .Pq Event 6CH , Umask 01H
724 Counts the number of completed I/O transactions.
726 .Pq Event 80H , Umask 01H
727 Counts all instruction fetches that hit the L1 instruction cache.
729 .Pq Event 80H , Umask 02H
730 Counts all instruction fetches that miss the L1I cache. This includes
731 instruction cache misses, streaming buffer misses, victim cache misses and
732 uncacheable fetches. An instruction fetch miss is counted only once and not
733 once for every cycle it is outstanding.
735 .Pq Event 80H , Umask 03H
736 Counts all instruction fetches, including uncacheable fetches that bypass
738 .It Li L1I.CYCLES_STALLED
739 .Pq Event 80H , Umask 04H
740 Cycle counts for which an instruction fetch stalls due to a L1I cache miss,
741 ITLB miss or ITLB fault.
742 .It Li LARGE_ITLB.HIT
743 .Pq Event 82H , Umask 01H
744 Counts number of large ITLB hits.
745 .It Li ITLB_MISSES.ANY
746 .Pq Event 85H , Umask 01H
747 Counts the number of misses in all levels of the ITLB which causes a page
749 .It Li ITLB_MISSES.WALK_COMPLETED
750 .Pq Event 85H , Umask 02H
751 Counts number of misses in all levels of the ITLB which resulted in a
754 .Pq Event 87H , Umask 01H
755 Cycles Instruction Length Decoder stalls due to length changing prefixes:
756 66, 67 or REX.W (for EM64T) instructions which change the length of the
759 .Pq Event 87H , Umask 02H
760 Instruction Length Decoder stall cycles due to Brand Prediction Unit (PBU)
761 Most Recently Used (MRU) bypass.
762 .It Li ILD_STALL.IQ_FULL
763 .Pq Event 87H , Umask 04H
764 Stall cycles due to a full instruction queue.
765 .It Li ILD_STALL.REGEN
766 .Pq Event 87H , Umask 08H
767 Counts the number of regen stalls.
769 .Pq Event 87H , Umask 0FH
770 Counts any cycles the Instruction Length Decoder is stalled.
771 .It Li BR_INST_EXEC.COND
772 .Pq Event 88H , Umask 01H
773 Counts the number of conditional near branch instructions executed, but not
775 .It Li BR_INST_EXEC.DIRECT
776 .Pq Event 88H , Umask 02H
777 Counts all unconditional near branch instructions excluding calls and
779 .It Li BR_INST_EXEC.INDIRECT_NON_CALL
780 .Pq Event 88H , Umask 04H
781 Counts the number of executed indirect near branch instructions that are not
783 .It Li BR_INST_EXEC.NON_CALLS
784 .Pq Event 88H , Umask 07H
785 Counts all non call near branch instructions executed, but not necessarily
787 .It Li BR_INST_EXEC.RETURN_NEAR
788 .Pq Event 88H , Umask 08H
789 Counts indirect near branches that have a return mnemonic.
790 .It Li BR_INST_EXEC.DIRECT_NEAR_CALL
791 .Pq Event 88H , Umask 10H
792 Counts unconditional near call branch instructions, excluding non call
794 .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
795 .Pq Event 88H , Umask 20H
796 Counts indirect near calls, including both register and memory indirect,
798 .It Li BR_INST_EXEC.NEAR_CALLS
799 .Pq Event 88H , Umask 30H
800 Counts all near call branches executed, but not necessarily retired.
801 .It Li BR_INST_EXEC.TAKEN
802 .Pq Event 88H , Umask 40H
803 Counts taken near branches executed, but not necessarily retired.
804 .It Li BR_INST_EXEC.ANY
805 .Pq Event 88H , Umask 7FH
806 Counts all near executed branches (not necessarily retired). This includes
807 only instructions and not micro-op branches. Frequent branching is not
808 necessarily a major performance issue. However frequent branch
809 mispredictions may be a problem.
810 .It Li BR_MISP_EXEC.COND
811 .Pq Event 89H , Umask 01H
812 Counts the number of mispredicted conditional near branch instructions
813 executed, but not necessarily retired.
814 .It Li BR_MISP_EXEC.DIRECT
815 .Pq Event 89H , Umask 02H
816 Counts mispredicted macro unconditional near branch instructions, excluding
817 calls and indirect branches (should always be 0).
818 .It Li BR_MISP_EXEC.INDIRECT_NON_CALL
819 .Pq Event 89H , Umask 04H
820 Counts the number of executed mispredicted indirect near branch instructions
822 .It Li BR_MISP_EXEC.NON_CALLS
823 .Pq Event 89H , Umask 07H
824 Counts mispredicted non call near branches executed, but not necessarily
826 .It Li BR_MISP_EXEC.RETURN_NEAR
827 .Pq Event 89H , Umask 08H
828 Counts mispredicted indirect branches that have a rear return mnemonic.
829 .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
830 .Pq Event 89H , Umask 10H
831 Counts mispredicted non-indirect near calls executed, (should always be 0).
832 .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
833 .Pq Event 89H , Umask 20H
834 Counts mispredicted indirect near calls executed, including both register
836 .It Li BR_MISP_EXEC.NEAR_CALLS
837 .Pq Event 89H , Umask 30H
838 Counts all mispredicted near call branches executed, but not necessarily
840 .It Li BR_MISP_EXEC.TAKEN
841 .Pq Event 89H , Umask 40H
842 Counts executed mispredicted near branches that are taken, but not
844 .It Li BR_MISP_EXEC.ANY
845 .Pq Event 89H , Umask 7FH
846 Counts the number of mispredicted near branch instructions that were
847 executed, but not necessarily retired.
848 .It Li RESOURCE_STALLS.ANY
849 .Pq Event A2H , Umask 01H
850 Counts the number of Allocator resource related stalls. Includes register
851 renaming buffer entries, memory buffer entries. In addition to resource
852 related stalls, this event counts some other events. Includes stalls arising
853 during branch misprediction recovery, such as if retirement of the
854 mispredicted branch is delayed and stalls arising while store buffer is
855 draining from synchronizing operations.
856 Does not include stalls due to SuperQ (off core) queue full, too many cache
858 .It Li RESOURCE_STALLS.LOAD
859 .Pq Event A2H , Umask 02H
860 Counts the cycles of stall due to lack of load buffer for load operation.
861 .It Li RESOURCE_STALLS.RS_FULL
862 .Pq Event A2H , Umask 04H
863 This event counts the number of cycles when the number of instructions in
864 the pipeline waiting for execution reaches the limit the processor can
865 handle. A high count of this event indicates that there are long latency
866 operations in the pipe (possibly load and store operations that miss the L2
867 cache, or instructions dependent upon instructions further down the pipeline
868 that have yet to retire.
869 When RS is full, new instructions can not enter the reservation station and
871 .It Li RESOURCE_STALLS.STORE
872 .Pq Event A2H , Umask 08H
873 This event counts the number of cycles that a resource related stall will
874 occur due to the number of store instructions reaching the limit of the
875 pipeline, (i.e. all store buffers are used). The stall ends when a store
876 instruction commits its data to the cache or memory.
877 .It Li RESOURCE_STALLS.ROB_FULL
878 .Pq Event A2H , Umask 10H
879 Counts the cycles of stall due to re- order buffer full.
880 .It Li RESOURCE_STALLS.FPCW
881 .Pq Event A2H , Umask 20H
882 Counts the number of cycles while execution was stalled due to writing the
883 floating-point unit (FPU) control word.
884 .It Li RESOURCE_STALLS.MXCSR
885 .Pq Event A2H , Umask 40H
886 Stalls due to the MXCSR register rename occurring to close to a previous
887 MXCSR rename. The MXCSR provides control and status for the MMX registers.
888 .It Li RESOURCE_STALLS.OTHER
889 .Pq Event A2H , Umask 80H
890 Counts the number of cycles while execution was stalled due to other
892 .It Li MACRO_INSTS.FUSIONS_DECODED
893 .Pq Event A6H , Umask 01H
894 Counts the number of instructions decoded that are macro-fused but not
895 necessarily executed or retired.
896 .It Li BACLEAR_FORCE_IQ
897 .Pq Event A7H , Umask 01H
898 Counts number of times a BACLEAR was forced by the Instruction Queue. The IQ
899 is also responsible for providing conditional branch prediction direction
900 based on a static scheme and dynamic data provided by the L2 Branch
901 Prediction Unit. If the conditional branch target is not found in the Target
902 Array and the IQ predicts that the branch is taken, then the IQ will force
903 the Branch Address Calculator to issue a BACLEAR. Each BACLEAR asserted by
904 the BAC generates approximately an 8 cycle bubble in the instruction fetch
907 .Pq Event A8H , Umask 01H
908 Counts the number of micro-ops delivered by loop stream detector
909 Use cmask=1 and invert to count cycles
911 .Pq Event AEH , Umask 01H
912 Counts the number of ITLB flushes
913 .It Li OFFCORE_REQUESTS.L1D_WRITEBACK
914 .Pq Event B0H , Umask 40H
915 Counts number of L1D writebacks to the uncore.
916 .It Li UOPS_EXECUTED.PORT0
917 .Pq Event B1H , Umask 01H
918 Counts number of Uops executed that were issued on port 0. Port 0 handles
919 integer arithmetic, SIMD and FP add Uops.
920 .It Li UOPS_EXECUTED.PORT1
921 .Pq Event B1H , Umask 02H
922 Counts number of Uops executed that were issued on port 1. Port 1 handles
923 integer arithmetic, SIMD, integer shift, FP multiply and FP divide Uops.
924 .It Li UOPS_EXECUTED.PORT2_CORE
925 .Pq Event B1H , Umask 04H
926 Counts number of Uops executed that were issued on port 2. Port 2 handles
927 the load Uops. This is a core count only and can not be collected per
929 .It Li UOPS_EXECUTED.PORT3_CORE
930 .Pq Event B1H , Umask 08H
931 Counts number of Uops executed that were issued on port 3. Port 3 handles
932 store Uops. This is a core count only and can not be collected per thread.
933 .It Li UOPS_EXECUTED.PORT4_CORE
934 .Pq Event B1H , Umask 10H
935 Counts number of Uops executed that where issued on port 4. Port 4 handles
936 the value to be stored for the store Uops issued on port 3. This is a core
937 count only and can not be collected per thread.
938 .It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5
939 .Pq Event B1H , Umask 1FH
940 Counts cycles when the Uops executed were issued from any ports except port
941 5. Use Cmask=1 for active cycles; Cmask=0 for weighted cycles; Use CMask=1,
942 Invert=1 to count P0-4 stalled cycles Use Cmask=1, Edge=1, Invert=1 to count
944 .It Li UOPS_EXECUTED.PORT5
945 .Pq Event B1H , Umask 20H
946 Counts number of Uops executed that where issued on port 5.
947 .It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES
948 .Pq Event B1H , Umask 3FH
949 Counts cycles when the Uops are executing. Use Cmask=1 for active cycles;
950 Cmask=0 for weighted cycles; Use CMask=1, Invert=1 to count P0-4 stalled
951 cycles Use Cmask=1, Edge=1, Invert=1 to count P0-4 stalls.
952 .It Li UOPS_EXECUTED.PORT015
953 .Pq Event B1H , Umask 40H
954 Counts number of Uops executed that where issued on port 0, 1, or 5.
955 use cmask=1, invert=1 to count stall cycles
956 .It Li UOPS_EXECUTED.PORT234
957 .Pq Event B1H , Umask 80H
958 Counts number of Uops executed that where issued on port 2, 3, or 4.
959 .It Li OFFCORE_REQUESTS_SQ_FULL
960 .Pq Event B2H , Umask 01H
961 Counts number of cycles the SQ is full to handle off-core requests.
962 .It Li OFF_CORE_RESPONSE_0
963 .Pq Event B7H , Umask 01H
964 see Section 30.6.1.3, Off-core Response Performance Monitoring in the
966 Requires programming MSR 01A6H
967 .It Li SNOOP_RESPONSE.HIT
968 .Pq Event B8H , Umask 01H
969 Counts HIT snoop response sent by this thread in response to a snoop
971 .It Li SNOOP_RESPONSE.HITE
972 .Pq Event B8H , Umask 02H
973 Counts HIT E snoop response sent by this thread in response to a snoop
975 .It Li SNOOP_RESPONSE.HITM
976 .Pq Event B8H , Umask 04H
977 Counts HIT M snoop response sent by this thread in response to a snoop
979 .It Li OFF_CORE_RESPONSE_1
980 .Pq Event BBH , Umask 01H
981 see Section 30.6.1.3, Off-core Response Performance Monitoring in the
983 Requires programming MSR 01A7H
984 .It Li INST_RETIRED.ANY_P
985 .Pq Event C0H , Umask 01H
987 Notes: INST_RETIRED.ANY is counted by a designated fixed counter.
988 INST_RETIRED.ANY_P is counted by a programmable counter and is an
989 architectural performance event. Event is supported if CPUID.A.EBX[1] = 0.
990 Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not
991 count as retired instructions.
992 .It Li INST_RETIRED.X87
993 .Pq Event C0H , Umask 02H
994 Counts the number of MMX instructions retired.
995 .It Li INST_RETIRED.MMX
996 .Pq Event C0H , Umask 04H
997 Counts the number of floating point computational operations retired:
998 floating point computational operations executed by the assist handler and
999 sub-operations of complex floating point instructions like transcendental
1001 .It Li UOPS_RETIRED.ANY
1002 .Pq Event C2H , Umask 01H
1003 Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2,
1004 others=1; maximum count of 8 per cycle). Most instructions are composed of
1005 one or two micro-ops. Some instructions are decoded into longer sequences
1006 such as repeat instructions, floating point transcendental instructions, and
1008 Use cmask=1 and invert to count active cycles or stalled cycles
1009 .It Li UOPS_RETIRED.RETIRE_SLOTS
1010 .Pq Event C2H , Umask 02H
1011 Counts the number of retirement slots used each cycle
1012 .It Li UOPS_RETIRED.MACRO_FUSED
1013 .Pq Event C2H , Umask 04H
1014 Counts number of macro-fused uops retired.
1015 .It Li MACHINE_CLEARS.CYCLES
1016 .Pq Event C3H , Umask 01H
1017 Counts the cycles machine clear is asserted.
1018 .It Li MACHINE_CLEARS.MEM_ORDER
1019 .Pq Event C3H , Umask 02H
1020 Counts the number of machine clears due to memory order conflicts.
1021 .It Li MACHINE_CLEARS.SMC
1022 .Pq Event C3H , Umask 04H
1023 Counts the number of times that a program writes to a code section.
1024 Self-modifying code causes a sever penalty in all Intel 64 and IA-32
1025 processors. The modified cache line is written back to the L2 and L3caches.
1026 .It Li BR_INST_RETIRED.ALL_BRANCHES
1027 .Pq Event C4H , Umask 00H
1029 .It Li BR_INST_RETIRED.CONDITIONAL
1030 .Pq Event C4H , Umask 01H
1031 Counts the number of conditional branch instructions retired.
1032 .It Li BR_INST_RETIRED.NEAR_CALL
1033 .Pq Event C4H , Umask 02H
1034 Counts the number of direct & indirect near unconditional calls retired
1035 .It Li BR_INST_RETIRED.ALL_BRANCHES
1036 .Pq Event C4H , Umask 04H
1037 Counts the number of branch instructions retired
1038 .It Li BR_MISP_RETIRED.ALL_BRANCHES
1039 .Pq Event C5H , Umask 00H
1041 .It Li BR_MISP_RETIRED.NEAR_CALL
1042 .Pq Event C5H , Umask 02H
1043 Counts mispredicted direct & indirect near unconditional retired calls.
1044 .It Li SSEX_UOPS_RETIRED.PACKED_SINGLE
1045 .Pq Event C7H , Umask 01H
1046 Counts SIMD packed single-precision floating point Uops retired.
1047 .It Li SSEX_UOPS_RETIRED.SCALAR_SINGLE
1048 .Pq Event C7H , Umask 02H
1049 Counts SIMD calar single-precision floating point Uops retired.
1050 .It Li SSEX_UOPS_RETIRED.PACKED_DOUBLE
1051 .Pq Event C7H , Umask 04H
1052 Counts SIMD packed double- precision floating point Uops retired.
1053 .It Li SSEX_UOPS_RETIRED.SCALAR_DOUBLE
1054 .Pq Event C7H , Umask 08H
1055 Counts SIMD scalar double-precision floating point Uops retired.
1056 .It Li SSEX_UOPS_RETIRED.VECTOR_INTEGER
1057 .Pq Event C7H , Umask 10H
1058 Counts 128-bit SIMD vector integer Uops retired.
1059 .It Li ITLB_MISS_RETIRED
1060 .Pq Event C8H , Umask 20H
1061 Counts the number of retired instructions that missed the ITLB when the
1062 instruction was fetched.
1063 .It Li MEM_LOAD_RETIRED.L1D_HIT
1064 .Pq Event CBH , Umask 01H
1065 Counts number of retired loads that hit the L1 data cache.
1066 .It Li MEM_LOAD_RETIRED.L2_HIT
1067 .Pq Event CBH , Umask 02H
1068 Counts number of retired loads that hit the L2 data cache.
1069 .It Li MEM_LOAD_RETIRED.L3_UNSHARED_HIT
1070 .Pq Event CBH , Umask 04H
1071 Counts number of retired loads that hit their own, unshared lines in the L3
1073 .It Li MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM
1074 .Pq Event CBH , Umask 08H
1075 Counts number of retired loads that hit in a sibling core's L2 (on die
1076 core). Since the L3 is inclusive of all cores on the package, this is an L3
1077 hit. This counts both clean or modified hits.
1078 .It Li MEM_LOAD_RETIRED.L3_MISS
1079 .Pq Event CBH , Umask 10H
1080 Counts number of retired loads that miss the L3 cache. The load was
1081 satisfied by a remote socket, local memory or an IOH.
1082 .It Li MEM_LOAD_RETIRED.HIT_LFB
1083 .Pq Event CBH , Umask 40H
1084 Counts number of retired loads that miss the L1D and the address is located
1085 in an allocated line fill buffer and will soon be committed to cache. This
1086 is counting secondary L1D misses.
1087 .It Li MEM_LOAD_RETIRED.DTLB_MISS
1088 .Pq Event CBH , Umask 80H
1089 Counts the number of retired loads that missed the DTLB. The DTLB miss is
1090 not counted if the load operation causes a fault. This event counts loads
1091 from cacheable memory only. The event does not count loads by software
1092 prefetches. Counts both primary and secondary misses to the TLB.
1093 .It Li FP_MMX_TRANS.TO_FP
1094 .Pq Event CCH , Umask 01H
1095 Counts the first floating-point instruction following any MMX instruction.
1096 You can use this event to estimate the penalties for the transitions between
1097 floating-point and MMX technology states.
1098 .It Li FP_MMX_TRANS.TO_MMX
1099 .Pq Event CCH , Umask 02H
1100 Counts the first MMX instruction following a floating-point instruction. You
1101 can use this event to estimate the penalties for the transitions between
1102 floating-point and MMX technology states.
1103 .It Li FP_MMX_TRANS.ANY
1104 .Pq Event CCH , Umask 03H
1105 Counts all transitions from floating point to MMX instructions and from MMX
1106 instructions to floating point instructions. You can use this event to
1107 estimate the penalties for the transitions between floating-point and MMX
1109 .It Li MACRO_INSTS.DECODED
1110 .Pq Event D0H , Umask 01H
1111 Counts the number of instructions decoded, (but not necessarily executed or
1113 .It Li UOPS_DECODED.MS
1114 .Pq Event D1H , Umask 02H
1115 Counts the number of Uops decoded by the Microcode Sequencer, MS. The MS
1116 delivers uops when the instruction is more than 4 uops long or a microcode
1117 assist is occurring.
1118 .It Li UOPS_DECODED.ESP_FOLDING
1119 .Pq Event D1H , Umask 04H
1120 Counts number of stack pointer (ESP) instructions decoded: push , pop , call
1121 , ret, etc. ESP instructions do not generate a Uop to increment or decrement
1122 ESP. Instead, they update an ESP_Offset register that keeps track of the
1123 delta to the current value of the ESP register.
1124 .It Li UOPS_DECODED.ESP_SYNC
1125 .Pq Event D1H , Umask 08H
1126 Counts number of stack pointer (ESP) sync operations where an ESP
1127 instruction is corrected by adding the ESP offset register to the current
1128 value of the ESP register.
1129 .It Li RAT_STALLS.FLAGS
1130 .Pq Event D2H , Umask 01H
1131 Counts the number of cycles during which execution stalled due to several
1132 reasons, one of which is a partial flag register stall. A partial register
1133 stall may occur when two conditions are met: 1) an instruction modifies
1134 some, but not all, of the flags in the flag register and 2) the next
1135 instruction, which depends on flags, depends on flags that were not modified
1136 by this instruction.
1137 .It Li RAT_STALLS.REGISTERS
1138 .Pq Event D2H , Umask 02H
1139 This event counts the number of cycles instruction execution latency became
1140 longer than the defined latency because the instruction used a register that
1141 was partially written by previous instruction.
1142 .It Li RAT_STALLS.ROB_READ_PORT
1143 .Pq Event D2H , Umask 04H
1144 Counts the number of cycles when ROB read port stalls occurred, which did
1145 not allow new micro-ops to enter the out-of-order pipeline. Note that, at
1146 this stage in the pipeline, additional stalls may occur at the same cycle
1147 and prevent the stalled micro-ops from entering the pipe. In such a case,
1148 micro-ops retry entering the execution pipe in the next cycle and the
1149 ROB-read port stall is counted again.
1150 .It Li RAT_STALLS.SCOREBOARD
1151 .Pq Event D2H , Umask 08H
1152 Counts the cycles where we stall due to microarchitecturally required
1153 serialization. Microcode scoreboarding stalls.
1154 .It Li RAT_STALLS.ANY
1155 .Pq Event D2H , Umask 0FH
1156 Counts all Register Allocation Table stall cycles due to: Cycles when ROB
1157 read port stalls occurred, which did not allow new micro-ops to enter the
1158 execution pipe. Cycles when partial register stalls occurred Cycles when
1159 flag stalls occurred Cycles floating-point unit (FPU) status word stalls
1160 occurred. To count each of these conditions separately use the events:
1161 RAT_STALLS.ROB_READ_PORT, RAT_STALLS.PARTIAL, RAT_STALLS.FLAGS, and
1163 .It Li SEG_RENAME_STALLS
1164 .Pq Event D4H , Umask 01H
1165 Counts the number of stall cycles due to the lack of renaming resources for
1166 the ES, DS, FS, and GS segment registers. If a segment is renamed but not
1167 retired and a second update to the same segment occurs, a stall occurs in
1168 the front-end of the pipeline until the renamed segment retires.
1169 .It Li ES_REG_RENAMES
1170 .Pq Event D5H , Umask 01H
1171 Counts the number of times the ES segment register is renamed.
1173 .Pq Event DBH , Umask 01H
1174 Counts unfusion events due to floating point exception to a fused uop.
1175 .It Li BR_INST_DECODED
1176 .Pq Event E0H , Umask 01H
1177 Counts the number of branch instructions decoded.
1178 .It Li BPU_MISSED_CALL_RET
1179 .Pq Event E5H , Umask 01H
1180 Counts number of times the Branch Prediction Unit missed predicting a call
1182 .It Li BACLEAR.CLEAR
1183 .Pq Event E6H , Umask 01H
1184 Counts the number of times the front end is resteered, mainly when the
1185 Branch Prediction Unit cannot provide a correct prediction and this is
1186 corrected by the Branch Address Calculator at the front end. This can occur
1187 if the code has many branches such that they cannot be consumed by the BPU.
1188 Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble
1189 in the instruction fetch pipeline. The effect on total execution time
1190 depends on the surrounding code.
1191 .It Li BACLEAR.BAD_TARGET
1192 .Pq Event E6H , Umask 02H
1193 Counts number of Branch Address Calculator clears (BACLEAR) asserted due to
1194 conditional branch instructions in which there was a target hit but the
1195 direction was wrong. Each BACLEAR asserted by the BAC generates
1196 approximately an 8 cycle bubble in the instruction fetch pipeline.
1197 .It Li BPU_CLEARS.EARLY
1198 .Pq Event E8H , Umask 01H
1199 Counts early (normal) Branch Prediction Unit clears: BPU predicted a taken
1200 branch after incorrectly assuming that it was not taken.
1201 The BPU clear leads to 2 cycle bubble in the Front End.
1202 .It Li BPU_CLEARS.LATE
1203 .Pq Event E8H , Umask 02H
1204 Counts late Branch Prediction Unit clears due to Most Recently Used
1205 conflicts. The PBU clear leads to a 3 cycle bubble in the Front End.
1206 .It Li L2_TRANSACTIONS.LOAD
1207 .Pq Event F0H , Umask 01H
1208 Counts L2 load operations due to HW prefetch or demand loads.
1209 .It Li L2_TRANSACTIONS.RFO
1210 .Pq Event F0H , Umask 02H
1211 Counts L2 RFO operations due to HW prefetch or demand RFOs.
1212 .It Li L2_TRANSACTIONS.IFETCH
1213 .Pq Event F0H , Umask 04H
1214 Counts L2 instruction fetch operations due to HW prefetch or demand ifetch.
1215 .It Li L2_TRANSACTIONS.PREFETCH
1216 .Pq Event F0H , Umask 08H
1217 Counts L2 prefetch operations.
1218 .It Li L2_TRANSACTIONS.L1D_WB
1219 .Pq Event F0H , Umask 10H
1220 Counts L1D writeback operations to the L2.
1221 .It Li L2_TRANSACTIONS.FILL
1222 .Pq Event F0H , Umask 20H
1223 Counts L2 cache line fill operations due to load, RFO, L1D writeback or
1225 .It Li L2_TRANSACTIONS.WB
1226 .Pq Event F0H , Umask 40H
1227 Counts L2 writeback operations to the L3.
1228 .It Li L2_TRANSACTIONS.ANY
1229 .Pq Event F0H , Umask 80H
1230 Counts all L2 cache operations.
1231 .It Li L2_LINES_IN.S_STATE
1232 .Pq Event F1H , Umask 02H
1233 Counts the number of cache lines allocated in the L2 cache in the S (shared)
1235 .It Li L2_LINES_IN.E_STATE
1236 .Pq Event F1H , Umask 04H
1237 Counts the number of cache lines allocated in the L2 cache in the E
1239 .It Li L2_LINES_IN.ANY
1240 .Pq Event F1H , Umask 07H
1241 Counts the number of cache lines allocated in the L2 cache.
1242 .It Li L2_LINES_OUT.DEMAND_CLEAN
1243 .Pq Event F2H , Umask 01H
1244 Counts L2 clean cache lines evicted by a demand request.
1245 .It Li L2_LINES_OUT.DEMAND_DIRTY
1246 .Pq Event F2H , Umask 02H
1247 Counts L2 dirty (modified) cache lines evicted by a demand request.
1248 .It Li L2_LINES_OUT.PREFETCH_CLEAN
1249 .Pq Event F2H , Umask 04H
1250 Counts L2 clean cache line evicted by a prefetch request.
1251 .It Li L2_LINES_OUT.PREFETCH_DIRTY
1252 .Pq Event F2H , Umask 08H
1253 Counts L2 modified cache line evicted by a prefetch request.
1254 .It Li L2_LINES_OUT.ANY
1255 .Pq Event F2H , Umask 0FH
1256 Counts all L2 cache lines evicted for any reason.
1257 .It Li SQ_MISC.SPLIT_LOCK
1258 .Pq Event F4H , Umask 10H
1259 Counts the number of SQ lock splits across a cache line.
1260 .It Li SQ_FULL_STALL_CYCLES
1261 .Pq Event F6H , Umask 01H
1262 Counts cycles the Super Queue is full. Neither of the threads on this core
1263 will be able to access the uncore.
1264 .It Li FP_ASSIST.ALL
1265 .Pq Event F7H , Umask 01H
1266 Counts the number of floating point operations executed that required
1267 micro-code assist intervention. Assists are required in the following cases:
1268 SSE instructions, (Denormal input when the DAZ flag is off or Underflow
1269 result when the FTZ flag is off): x87 instructions, (NaN or denormal are
1270 loaded to a register or used as input from memory, Division by 0 or
1272 .It Li FP_ASSIST.OUTPUT
1273 .Pq Event F7H , Umask 02H
1274 Counts number of floating point micro-code assist when the output value
1275 (destination register) is invalid.
1276 .It Li FP_ASSIST.INPUT
1277 .Pq Event F7H , Umask 04H
1278 Counts number of floating point micro-code assist when the input value (one
1279 of the source operands to an FP instruction) is invalid.
1280 .It Li SIMD_INT_64.PACKED_MPY
1281 .Pq Event FDH , Umask 01H
1282 Counts number of SID integer 64 bit packed multiply operations.
1283 .It Li SIMD_INT_64.PACKED_SHIFT
1284 .Pq Event FDH , Umask 02H
1285 Counts number of SID integer 64 bit packed shift operations.
1286 .It Li SIMD_INT_64.PACK
1287 .Pq Event FDH , Umask 04H
1288 Counts number of SID integer 64 bit pack operations.
1289 .It Li SIMD_INT_64.UNPACK
1290 .Pq Event FDH , Umask 08H
1291 Counts number of SID integer 64 bit unpack operations.
1292 .It Li SIMD_INT_64.PACKED_LOGICAL
1293 .Pq Event FDH , Umask 10H
1294 Counts number of SID integer 64 bit logical operations.
1295 .It Li SIMD_INT_64.PACKED_ARITH
1296 .Pq Event FDH , Umask 20H
1297 Counts number of SID integer 64 bit arithmetic operations.
1298 .It Li SIMD_INT_64.SHUFFLE_MOVE
1299 .Pq Event FDH , Umask 40H
1300 Counts number of SID integer 64 bit shift or move operations.
1302 .Ss Event Specifiers (Programmable PMCs)
1303 Core i7 and Xeon 5500 programmable PMCs support the following events as
1304 June 2009 document (removed in December 2009):
1305 .Bl -tag -width indent
1306 .It Li SB_FORWARD.ANY
1307 .Pq Event 02H , Umask 01H
1308 Counts the number of store forwards.
1309 .It Li LOAD_BLOCK.STD
1310 .Pq Event 03H , Umask 01H
1311 Counts the number of loads blocked by a preceding store with unknown data.
1312 .It Li LOAD_BLOCK.ADDRESS_OFFSET
1313 .Pq Event 03H , Umask 04H
1314 Counts the number of loads blocked by a preceding store address.
1315 .It Li LOAD_BLOCK.ADDRESS_OFFSET
1316 .Pq Event 01H , Umask 04H
1317 Counts the cycles of store buffer drains.
1318 .It Li MISALIGN_MEM_REF.LOAD
1319 .Pq Event 05H , Umask 01H
1320 Counts the number of misaligned load references
1321 .It Li MISALIGN_MEM_REF.STORE
1322 .Pq Event 05H , Umask 02H
1323 Counts the number of misaligned store references
1324 .It Li MISALIGN_MEM_REF.ANY
1325 .Pq Event 05H , Umask 03H
1326 Counts the number of misaligned memory references
1327 .It Li STORE_BLOCKS.NOT_STA
1328 .Pq Event 06H , Umask 01H
1329 This event counts the number of load operations delayed caused by preceding
1330 stores whose addresses are known but whose data is unknown, and preceding
1331 stores that conflict with the load but which incompletely overlap the load.
1332 .It Li STORE_BLOCKS.STA
1333 .Pq Event 06H , Umask 02H
1334 This event counts load operations delayed caused by preceding stores whose
1335 addresses are unknown (STA block).
1336 .It Li STORE_BLOCKS.ANY
1337 .Pq Event 06H , Umask 0FH
1338 All loads delayed due to store blocks
1339 .It Li MEMORY_DISAMBIGURATION.RESET
1340 .Pq Event 09H , Umask 01H
1341 Counts memory disambiguration reset cycles
1342 .It Li MEMORY_DISAMBIGURATION.SUCCESS
1343 .Pq Event 09H , Umask 02H
1344 Counts the number of loads that memory disambiguration succeeded
1345 .It Li MEMORY_DISAMBIGURATION.WATCHDOG
1346 .Pq Event 09H , Umask 04H
1347 Counts the number of times the memory disambiguration watchdog kicked in.
1348 .It Li MEMORY_DISAMBIGURATION.WATCH_CYCLES
1349 .Pq Event 09H , Umask 08H
1350 Counts the cycles that the memory disambiguration watchdog is active.
1351 set invert=1, cmask = 1
1353 .Pq Event 1DH , Umask 01H
1354 Number of interrupt received
1355 .It Li HW_INT.CYCLES_MASKED
1356 .Pq Event 1DH , Umask 02H
1357 Number of cycles interrupt are masked
1358 .It Li HW_INT.CYCLES_PENDING_AND_MASKED
1359 .Pq Event 1DH , Umask 04H
1360 Number of cycles interrupts are pending and masked
1361 .It Li HW_INT.CYCLES_PENDING_AND_MASKED
1362 .Pq Event 04H , Umask 04H
1363 Counts number of L2 store RFO requests where the cache line to be loaded is
1364 in the E (exclusive) state. The L1D prefetcher does not issue a RFO
1366 This is a demand RFO request
1367 .It Li HW_INT.CYCLES_PENDING_AND_MASKED
1368 .Pq Event 27H , Umask 04H
1369 LONGEST_LAT_CACH E.MISS
1370 .It Li UOPS_DECODED.DEC0
1371 .Pq Event 3DH , Umask 01H
1372 Counts micro-ops decoded by decoder 0.
1373 .It Li UOPS_DECODED.DEC0
1374 .Pq Event 01H , Umask 01H
1375 Counts L1 data cache store RFO requests where the cache line to be loaded is
1379 .Pq Event 41H , Umask 41H
1381 Counts L1 data cache store RFO requests.
1383 .It Li DTLB_MISSES.PDE_MISS
1384 .Pq Event 49H , Umask 20H
1385 Number of DTLB cache misses where the low part of the linear to physical
1386 address translation was missed.
1387 .It Li DTLB_MISSES.PDP_MISS
1388 .Pq Event 49H , Umask 40H
1389 Number of DTLB misses where the high part of the linear to physical address
1390 translation was missed.
1391 .It Li DTLB_MISSES.LARGE_WALK_COMPLETED
1392 .Pq Event 49H , Umask 80H
1393 Counts number of completed large page walks due to misses in the STLB.
1394 .It Li SSE_MEM_EXEC.NTA
1395 .Pq Event 4BH , Umask 01H
1396 Counts number of SSE NTA prefetch/weakly-ordered instructions which missed
1398 .It Li SSE_MEM_EXEC.STREAMING_STORES
1399 .Pq Event 4BH , Umask 08H
1400 Counts number of SSE non temporal stores
1401 .It Li SFENCE_CYCLES
1402 .Pq Event 4DH , Umask 01H
1403 Counts store fence cycles
1404 .It Li EPT.EPDE_MISS
1405 .Pq Event 4FH , Umask 02H
1406 Counts Extended Page Directory Entry misses. The Extended Page Directory
1407 cache is used by Virtual Machine operating systems while the guest operating
1408 systems use the standard TLB caches.
1409 .It Li EPT.EPDPE_HIT
1410 .Pq Event 4FH , Umask 04H
1411 Counts Extended Page Directory Pointer Entry hits.
1412 .It Li EPT.EPDPE_MISS
1413 .Pq Event 4FH , Umask 08H
1414 Counts Extended Page Directory Pointer Entry misses. T
1415 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA
1416 .Pq Event 60H , Umask 01H
1417 Counts weighted cycles of offcore demand data read requests. Does not
1418 include L2 prefetch requests.
1420 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE
1421 .Pq Event 60H , Umask 02H
1422 Counts weighted cycles of offcore demand code read requests. Does not
1423 include L2 prefetch requests.
1425 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO
1426 .Pq Event 60H , Umask 04H
1427 Counts weighted cycles of offcore demand RFO requests. Does not include L2
1430 .It Li OFFCORE_REQUESTS_OUTSTANDING.ANY.READ
1431 .Pq Event 60H , Umask 08H
1432 Counts weighted cycles of offcore read requests of any kind. Include L2
1436 .Pq Event 81H , Umask 01H
1437 Instruction Fetche unit victim cache full.
1438 .It Li IFU_IVC.L1I_EVICTION
1439 .Pq Event 81H , Umask 02H
1440 L1 Instruction cache evictions.
1441 .It Li L1I_OPPORTUNISTIC_HITS
1442 .Pq Event 83H , Umask 01H
1443 Opportunistic hits in streaming.
1444 .It Li ITLB_MISSES.WALK_CYCLES
1445 .Pq Event 85H , Umask 04H
1446 Counts ITLB miss page walk cycles.
1447 .It Li ITLB_MISSES.PMH_BUSY_CYCLES
1448 .Pq Event 85H , Umask 04H
1449 Counts PMH busy cycles.
1450 .It Li ITLB_MISSES.STLB_HIT
1451 .Pq Event 85H , Umask 10H
1452 Counts the number of ITLB misses that hit in the second level TLB.
1453 .It Li ITLB_MISSES.PDE_MISS
1454 .Pq Event 85H , Umask 20H
1455 Number of ITLB misses where the low part of the linear to physical address
1456 translation was missed.
1457 .It Li ITLB_MISSES.PDP_MISS
1458 .Pq Event 85H , Umask 40H
1459 Number of ITLB misses where the high part of the linear to physical address
1460 translation was missed.
1461 .It Li ITLB_MISSES.LARGE_WALK_COMPLETED
1462 .Pq Event 85H , Umask 80H
1463 Counts number of completed large page walks due to misses in the STLB.
1464 .It Li ITLB_MISSES.LARGE_WALK_COMPLETED
1465 .Pq Event 01H , Umask 80H
1466 Counts number of offcore demand data read requests. Does not count L2
1468 .It Li OFFCORE_REQUESTS.DEMAND.READ_CODE
1469 .Pq Event B0H , Umask 02H
1470 Counts number of offcore demand code read requests. Does not count L2
1472 .It Li OFFCORE_REQUESTS.DEMAND.RFO
1473 .Pq Event B0H , Umask 04H
1474 Counts number of offcore demand RFO requests. Does not count L2 prefetch
1476 .It Li OFFCORE_REQUESTS.ANY.READ
1477 .Pq Event B0H , Umask 08H
1478 Counts number of offcore read requests. Includes L2 prefetch requests.
1479 .It Li OFFCORE_REQUESTS.ANY.RFO
1480 .Pq Event B0H , Umask 10H
1481 Counts number of offcore RFO requests. Includes L2 prefetch requests.
1482 .It Li OFFCORE_REQUESTS.UNCACHED_MEM
1483 .Pq Event B0H , Umask 20H
1484 Counts number of offcore uncached memory requests.
1485 .It Li OFFCORE_REQUESTS.ANY
1486 .Pq Event B0H , Umask 80H
1487 Counts all offcore requests.
1488 .It Li SNOOPQ_REQUESTS_OUTSTANDING.DATA
1489 .Pq Event B3H , Umask 01H
1490 Counts weighted cycles of snoopq requests for data. Counter 0 only
1491 Use cmask=1 to count cycles not empty.
1492 .It Li SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE
1493 .Pq Event B3H , Umask 02H
1494 Counts weighted cycles of snoopq invalidate requests. Counter 0 only
1495 Use cmask=1 to count cycles not empty.
1496 .It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE
1497 .Pq Event B3H , Umask 04H
1498 Counts weighted cycles of snoopq requests for code. Counter 0 only
1499 Use cmask=1 to count cycles not empty.
1500 .It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE
1501 .Pq Event BAH , Umask 04H
1502 Counts number of TPR reads
1503 .It Li PIC_ACCESSES.TPR_WRITES
1504 .Pq Event BAH , Umask 02H
1505 Counts number of TPR writes
1506 one or two micro-ops. Some instructions are decoded into longer sequences
1507 .It Li MACHINE_CLEARS.FUSION_ASSIST
1508 .Pq Event C3H , Umask 10H
1509 Counts the number of macro-fusion assists
1510 Counts SIMD packed single- precision floating point Uops retired.
1512 .Pq Event E4H , Umask 01H
1513 Counts the number of bogus branches.
1514 .It Li L2_HW_PREFETCH.HIT
1515 .Pq Event F3H , Umask 01H
1516 Count L2 HW prefetcher detector hits
1517 .It Li L2_HW_PREFETCH.ALLOC
1518 .Pq Event F3H , Umask 02H
1519 Count L2 HW prefetcher allocations
1520 .It Li L2_HW_PREFETCH.DATA_TRIGGER
1521 .Pq Event F3H , Umask 04H
1522 Count L2 HW data prefetcher triggered
1523 .It Li L2_HW_PREFETCH.CODE_TRIGGER
1524 .Pq Event F3H , Umask 08H
1525 Count L2 HW code prefetcher triggered
1526 .It Li L2_HW_PREFETCH.DCA_TRIGGER
1527 .Pq Event F3H , Umask 10H
1528 Count L2 HW DCA prefetcher triggered
1529 .It Li L2_HW_PREFETCH.KICK_START
1530 .Pq Event F3H , Umask 20H
1531 Count L2 HW prefetcher kick started
1532 .It Li SQ_MISC.PROMOTION
1533 .Pq Event F4H , Umask 01H
1534 Counts the number of L2 secondary misses that hit the Super Queue.
1535 .It Li SQ_MISC.PROMOTION_POST_GO
1536 .Pq Event F4H , Umask 02H
1537 Counts the number of L2 secondary misses during the Super Queue filling L2.
1538 .It Li SQ_MISC.LRU_HINTS
1539 .Pq Event F4H , Umask 04H
1540 Counts number of Super Queue LRU hints sent to L3.
1541 .It Li SQ_MISC.FILL_DROPPED
1542 .Pq Event F4H , Umask 08H
1543 Counts the number of SQ L2 fills dropped due to L2 busy.
1544 .It Li SEGMENT_REG_LOADS
1545 .Pq Event F8H , Umask 01H
1546 Counts number of segment register loads.
1559 .Xr pmc.corei7uc 3 ,
1560 .Xr pmc.westmere 3 ,
1561 .Xr pmc.westmereuc 3 ,
1569 library first appeared in
1574 library was written by
1576 .Aq jkoshy@FreeBSD.org .