2 .\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara@gmail.com>
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33 .Nd measurement events for
44 CPUs contain PMCs conforming to version 2 of the
46 performance measurement architecture.
47 These CPUs may contain up to two classes of PMCs:
48 .Bl -tag -width "Li PMC_CLASS_IAP"
50 Fixed-function counters that count only one hardware event per counter.
52 Programmable counters that may be configured to count one of a defined
53 set of hardware events.
56 The number of PMCs available in each class and their widths need to be
57 determined at run time by calling
60 Intel Haswell Xeon PMCs are documented in
62 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
63 .%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C"
64 .%N "Order Number: 325462-052US"
66 .%Q "Intel Corporation"
68 .Ss HASWELL FIXED FUNCTION PMCS
69 These PMCs and their supported events are documented in
71 .Ss HASWELL PROGRAMMABLE PMCS
72 The programmable PMCs support the following capabilities:
73 .Bl -column "PMC_CAP_INTERRUPT" "Support"
74 .It Em Capability Ta Em Support
75 .It PMC_CAP_CASCADE Ta \&No
76 .It PMC_CAP_EDGE Ta Yes
77 .It PMC_CAP_INTERRUPT Ta Yes
78 .It PMC_CAP_INVERT Ta Yes
79 .It PMC_CAP_READ Ta Yes
80 .It PMC_CAP_PRECISE Ta \&No
81 .It PMC_CAP_SYSTEM Ta Yes
82 .It PMC_CAP_TAGGING Ta \&No
83 .It PMC_CAP_THRESHOLD Ta Yes
84 .It PMC_CAP_USER Ta Yes
85 .It PMC_CAP_WRITE Ta Yes
88 Event specifiers for these PMCs support the following common
90 .Bl -tag -width indent
91 .It Li rsp= Ns Ar value
92 Configure the Off-core Response bits.
93 .Bl -tag -width indent
95 Counts the number of demand and DCU prefetch data reads of full
96 and partial cachelines as well as demand data page table entry
98 Does not count L2 data read prefetches or instruction fetches.
100 Counts the number of demand and DCU prefetch reads for ownership (RFO)
101 requests generated by a write to data cacheline.
102 Does not count L2 RFO prefetches.
103 .It Li REQ_DMND_IFETCH
104 Counts the number of demand and DCU prefetch instruction cacheline reads.
105 Does not count L2 code read prefetches.
107 Counts the number of writeback (modified to exclusive) transactions.
108 .It Li REQ_PF_DATA_RD
109 Counts the number of data cacheline reads generated by L2 prefetchers.
111 Counts the number of RFO requests generated by L2 prefetchers.
113 Counts the number of code reads generated by L2 prefetchers.
114 .It Li REQ_PF_LLC_DATA_RD
115 L2 prefetcher to L3 for loads.
116 .It Li REQ_PF_LLC_RFO
117 RFO requests generated by L2 prefetcher
118 .It Li REQ_PF_LLC_IFETCH
119 L2 prefetcher to L3 for instruction fetches.
121 Bus lock and split lock requests.
123 Streaming store requests.
125 Any other request that crosses IDI, including I/O.
127 Catch all value for any response types.
128 .It Li RES_SUPPLIER_NO_SUPP
129 No Supplier Information available.
130 .It Li RES_SUPPLIER_LLC_HITM
131 M-state initial lookup stat in L3.
132 .It Li RES_SUPPLIER_LLC_HITE
134 .It Li RES_SUPPLIER_LLC_HITS
136 .It Li RES_SUPPLIER_LLC_HITF
138 .It Li RES_SUPPLIER_LOCAL
139 Local DRAM Controller.
140 .It Li RES_SNOOP_SNP_NONE
141 No details on snoop-related information.
142 .It Li RES_SNOOP_SNP_NO_NEEDED
143 No snoop was needed to satisfy the request.
144 .It Li RES_SNOOP_SNP_MISS
145 A snoop was needed and it missed all snooped caches:
146 -For LLC Hit, ReslHitl was returned by all cores
147 -For LLC Miss, Rspl was returned by all sockets and data was returned from
149 .It Li RES_SNOOP_HIT_NO_FWD
150 A snoop was needed and it hits in at least one snooped cache.
151 Hit denotes a cache-line was valid before snoop effect.
153 -Snoop Hit w/ Invalidation (LLC Hit, RFO)
154 -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD)
155 -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S)
156 In the LLC Miss case, data is returned from DRAM.
157 .It Li RES_SNOOP_HIT_FWD
158 A snoop was needed and data was forwarded from a remote socket.
160 -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
161 .It Li RES_SNOOP_HITM
162 A snoop was needed and it HitM-ed in local or remote cache.
163 HitM denotes a cache-line was in modified state before effect as a results of snoop.
165 -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD)
166 -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO)
167 -Snoop MtoS (LLC Hit, IFetch/Data_RD).
169 Target was non-DRAM system address.
170 This includes MMIO transactions.
172 .It Li cmask= Ns Ar value
173 Configure the PMC to increment only if the number of configured
174 events measured in a cycle is greater than or equal to
177 Configure the PMC to count the number of de-asserted to asserted
178 transitions of the conditions expressed by the other qualifiers.
179 If specified, the counter will increment only once whenever a
180 condition becomes true, irrespective of the number of clocks during
181 which the condition remains true.
183 Invert the sense of comparison when the
185 qualifier is present, making the counter increment when the number of
186 events per cycle is less than the value specified by the
190 Configure the PMC to count events happening at processor privilege
193 Configure the PMC to count events occurring at privilege levels 1, 2
201 qualifiers are specified, the default is to enable both.
202 .Ss Event Specifiers (Programmable PMCs)
203 Haswell programmable PMCs support the following events:
204 .Bl -tag -width indent
205 .It Li LD_BLOCKS.STORE_FORWARD
206 .Pq Event 03H , Umask 02H
207 Loads blocked by overlapping with store buffer that
209 .It Li MISALIGN_MEM_REF.LOADS
210 .Pq Event 05H , Umask 01H
211 Speculative cache-line split load uops dispatched to
213 .It Li MISALIGN_MEM_REF.STORES
214 .Pq Event 05H , Umask 02H
215 Speculative cache-line split Store-address uops
217 .It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
218 .Pq Event 07H , Umask 01H
219 False dependencies in MOB due to partial compare
221 .It Li DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK
222 .Pq Event 08H , Umask 01H
223 Misses in all TLB levels that cause a page walk of any
225 .It Li DTLB_LOAD_MISSES.WALK_COMPLETED_4K
226 .Pq Event 08H , Umask 02H
227 Completed page walks due to demand load misses
228 that caused 4K page walks in any TLB levels.
229 .It Li DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K
230 .Pq Event 08H , Umask 02H
231 Completed page walks due to demand load misses
232 that caused 2M/4M page walks in any TLB levels.
233 .It Li DTLB_LOAD_MISSES.WALK_COMPLETED
234 .Pq Event 08H , Umask 0EH
235 Completed page walks in any TLB of any page size
236 due to demand load misses
237 .It Li DTLB_LOAD_MISSES.WALK_DURATION
238 .Pq Event 08H , Umask 10H
239 Cycle PMH is busy with a walk.
240 .It Li DTLB_LOAD_MISSES.STLB_HIT_4K
241 .Pq Event 08H , Umask 20H
242 Load misses that missed DTLB but hit STLB (4K).
243 .It Li DTLB_LOAD_MISSES.STLB_HIT_2M
244 .Pq Event 08H , Umask 40H
245 Load misses that missed DTLB but hit STLB (2M).
246 .It Li DTLB_LOAD_MISSES.STLB_HIT
247 .Pq Event 08H , Umask 60H
248 Number of cache load STLB hits.
250 .It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS
251 .Pq Event 08H , Umask 80H
252 DTLB demand load misses with low part of linear-to-
253 physical address translation missed
254 .It Li INT_MISC.RECOVERY_CYCLES
255 .Pq Event 0DH , Umask 03H
256 Cycles waiting to recover after Machine Clears
259 .It Li UOPS_ISSUED.ANY
260 .Pq Event 0EH , Umask 01H
261 ncrements each cycle the # of Uops issued by the
263 Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles
265 .It Li UOPS_ISSUED.FLAGS_MERGE
266 .Pq Event 0EH , Umask 10H
267 Number of flags-merge uops allocated.
268 Such uops adds delay.
269 .It Li UOPS_ISSUED.SLOW_LEA
270 .Pq Event 0EH , Umask 20H
271 Number of slow LEA or similar uops allocated.
272 Such uop has 3 sources (e.g. 2 sources + immediate)
273 regardless if as a result of LEA instruction or not.
274 .It Li UOPS_ISSUED.SiNGLE_MUL
275 .Pq Event 0EH , Umask 40H
276 Number of multiply packed/scalar single precision
278 .It Li L2_RQSTS.DEMAND_DATA_RD_MISS
279 .Pq Event 24H , Umask 21H
280 Demand Data Read requests that missed L2, no
282 .It Li L2_RQSTS.DEMAND_DATA_RD_HIT
283 .Pq Event 24H , Umask 41H
284 Demand Data Read requests that hit L2 cache.
285 .It Li L2_RQSTS.ALL_DEMAND_DATA_RD
286 .Pq Event 24H , Umask E1H
287 Counts any demand and L1 HW prefetch data load
289 .It Li L2_RQSTS.RFO_HIT
290 .Pq Event 24H , Umask 42H
291 Counts the number of store RFO requests that hit
293 .It Li L2_RQSTS.RFO_MISS
294 .Pq Event 24H , Umask 22H
295 Counts the number of store RFO requests that miss
297 .It Li L2_RQSTS.ALL_RFO
298 .Pq Event 24H , Umask E2H
299 Counts all L2 store RFO requests.
300 .It Li L2_RQSTS.CODE_RD_HIT
301 .Pq Event 24H , Umask 44H
302 Number of instruction fetches that hit the L2 cache.
303 .It Li L2_RQSTS.CODE_RD_MISS
304 .Pq Event 24H , Umask 24H
305 Number of instruction fetches that missed the L2
307 .It Li L2_RQSTS.ALL_DEMAND_MISS
308 .Pq Event 24H , Umask 27H
309 Demand requests that miss L2 cache.
310 .It Li L2_RQSTS.ALL_DEMAND_REFERENCES
311 .Pq Event 24H , Umask E7H
312 Demand requests to L2 cache.
313 .It Li L2_RQSTS.ALL_CODE_RD
314 .Pq Event 24H , Umask E4H
315 Counts all L2 code requests.
316 .It Li L2_RQSTS.L2_PF_HIT
317 .Pq Event 24H , Umask 50H
318 Counts all L2 HW prefetcher requests that hit L2.
319 .It Li L2_RQSTS.L2_PF_MISS
320 .Pq Event 24H , Umask 30H
321 Counts all L2 HW prefetcher requests that missed
323 .It Li L2_RQSTS.ALL_PF
324 .Pq Event 24H , Umask F8H
325 Counts all L2 HW prefetcher requests.
327 .Pq Event 24H , Umask 3FH
328 All requests that missed L2.
329 .It Li L2_RQSTS.REFERENCES
330 .Pq Event 24H , Umask FFH
331 All requests to L2 cache.
332 .It Li L2_DEMAND_RQSTS.WB_HIT
333 .Pq Event 27H , Umask 50H
334 Not rejected writebacks that hit L2 cache
335 .It Li LONGEST_LAT_CACHE.REFERENCE
336 .Pq Event 2EH , Umask 4FH
337 This event counts requests originating from the core
338 that reference a cache line in the last level cache.
339 .It Li LONGEST_LAT_CACHE.MISS
340 .Pq Event 2EH , Umask 41H
341 This event counts each cache miss condition for
342 references to the last level cache.
343 .It Li CPU_CLK_UNHALTED.THREAD_P
344 .Pq Event 3CH , Umask 00H
345 Counts the number of thread cycles while the thread
346 is not in a halt state.
347 The thread enters the halt state when it is running the HLT instruction.
348 The core frequency may change from time to time due to
349 power or thermal throttling.
350 .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK
351 .Pq Event 3CH , Umask 01H
352 Increments at the frequency of XCLK (100 MHz)
354 .It Li L1D_PEND_MISS.PENDING
355 .Pq Event 48H , Umask 01H
356 Increments the number of outstanding L1D misses
358 Set Cmaks = 1 and Edge =1 to count occurrences.
359 .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
360 .Pq Event 49H , Umask 01H
361 Miss in all TLB levels causes an page walk of any
362 page size (4K/2M/4M/1G).
363 .It Li DTLB_STORE_MISSES.WALK_COMPLETED_4K
364 .Pq Event 49H , Umask 02H
365 Completed page walks due to store misses in one or
366 more TLB levels of 4K page structure.
367 .It Li DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M
368 .Pq Event 49H , Umask 04H
369 Completed page walks due to store misses in one or
370 more TLB levels of 2M/4M page structure.
371 .It Li DTLB_STORE_MISSES.WALK_COMPLETED
372 .Pq Event 49H , Umask 0EH
373 Completed page walks due to store miss in any TLB
374 levels of any page size (4K/2M/4M/1G).
375 .It Li DTLB_STORE_MISSES.WALK_DURATION
376 .Pq Event 49H , Umask 10H
377 Cycles PMH is busy with this walk.
378 .It Li DTLB_STORE_MISSES.STLB_HIT_4K
379 .Pq Event 49H , Umask 20H
380 Store misses that missed DTLB but hit STLB (4K).
381 .It Li DTLB_STORE_MISSES.STLB_HIT_2M
382 .Pq Event 49H , Umask 40H
383 Store misses that missed DTLB but hit STLB (2M).
384 .It Li DTLB_STORE_MISSES.STLB_HIT
385 .Pq Event 49H , Umask 60H
386 Store operations that miss the first TLB level but hit
387 the second and do not cause page walks.
388 .It Li DTLB_STORE_MISSES.PDE_CACHE_MISS
389 .Pq Event 49H , Umask 80H
390 DTLB store misses with low part of linear-to-physical
391 address translation missed.
392 .It Li LOAD_HIT_PRE.SW_PF
393 .Pq Event 4CH , Umask 01H
394 Non-SW-prefetch load dispatches that hit fill buffer
395 allocated for S/W prefetch.
396 .It Li LOAD_HIT_PRE.HW_PF
397 .Pq Event 4CH , Umask 02H
398 Non-SW-prefetch load dispatches that hit fill buffer
399 allocated for H/W prefetch.
400 .It Li L1D.REPLACEMENT
401 .Pq Event 51H , Umask 01H
402 Counts the number of lines brought into the L1 data
404 .It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED
405 .Pq Event 58H , Umask 04H
406 Number of integer Move Elimination candidate uops
407 that were not eliminated.
408 .It Li MOVE_ELIMINATION.SMID_NOT_ELIMINATED
409 .Pq Event 58H , Umask 08H
410 Number of SIMD Move Elimination candidate uops
411 that were not eliminated.
412 .It Li MOVE_ELIMINATION.INT_ELIMINATED
413 .Pq Event 58H , Umask 01H
414 Unhalted core cycles when the thread is in ring 0.
415 .It Li MOVE_ELIMINATION.SMID_ELIMINATED
416 .Pq Event 58H , Umask 02H
417 Number of SIMD Move Elimination candidate uops
418 that were eliminated.
419 .It Li CPL_CYCLES.RING0
420 .Pq Event 5CH , Umask 02H
421 Unhalted core cycles when the thread is in ring 0.
422 .It Li CPL_CYCLES.RING123
423 .Pq Event 5CH , Umask 01H
424 Unhalted core cycles when the thread is not in ring 0.
425 .It Li RS_EVENTS.EMPTY_CYCLES
426 .Pq Event 5EH , Umask 01H
427 Cycles the RS is empty for the thread.
428 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
429 .Pq Event 60H , Umask 01H
430 Offcore outstanding Demand Data Read transactions
432 Set Cmask=1 to count cycles.
433 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD
434 .Pq Event 60H , Umask 02H
435 Offcore outstanding Demand code Read transactions
437 Set Cmask=1 to count cycles.
438 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
439 .Pq Event 60H , Umask 04H
440 Offcore outstanding RFO store transactions in SQ to uncore.
441 Set Cmask=1 to count cycles.
442 .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
443 .Pq Event 60H , Umask 08H
444 Offcore outstanding cacheable data read
445 transactions in SQ to uncore.
446 Set Cmask=1 to count cycles.
447 .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
448 .Pq Event 63H , Umask 01H
449 Cycles in which the L1D and L2 are locked, due to a
450 UC lock or split lock.
451 .It Li LOCK_CYCLES.CACHE_LOCK_DURATION
452 .Pq Event 63H , Umask 02H
453 Cycles in which the L1D is locked.
455 .Pq Event 79H , Umask 02H
456 Counts cycles the IDQ is empty.
458 .Pq Event 79H , Umask 04H
459 Increment each cycle # of uops delivered to IDQ from
461 Set Cmask = 1 to count cycles.
463 .Pq Event 79H , Umask 08H
464 Increment each cycle. # of uops delivered to IDQ
466 Set Cmask = 1 to count cycles.
467 .It Li IDQ.MS_DSB_UOPS
468 .Pq Event 79H , Umask 10H
469 Increment each cycle # of uops delivered to IDQ
471 Set Cmask = 1 to count cycles.
472 Add Edge=1 to count # of delivery.
473 .It Li IDQ.MS_MITE_UOPS
474 .Pq Event 79H , Umask 20H
475 ncrement each cycle # of uops delivered to IDQ
476 when MS_busy by MITE.
477 Set Cmask = 1 to count cycles.
479 .Pq Event 79H , Umask 30H
480 Increment each cycle # of uops delivered to IDQ from
481 MS by either DSB or MITE.
482 Set Cmask = 1 to count cycles.
483 .It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS
484 .Pq Event 79H , Umask 18H
485 Counts cycles DSB is delivered at least one uops.
487 .It Li IDQ.ALL_DSB_CYCLES_4_UOPS
488 .Pq Event 79H , Umask 18H
489 Counts cycles DSB is delivered four uops.
491 .It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS
492 .Pq Event 79H , Umask 24H
493 Counts cycles MITE is delivered at least one uops.
495 .It Li IDQ.ALL_MITE_CYCLES_4_UOPS
496 .Pq Event 79H , Umask 24H
497 Counts cycles MITE is delivered four uops.
499 .It Li IDQ.MITE_ALL_UOPS
500 .Pq Event 79H , Umask 3CH
501 # of uops delivered to IDQ from any path.
503 .Pq Event 80H , Umask 02H
504 Number of Instruction Cache, Streaming Buffer and
506 Includes UC accesses.
507 .It Li ITLB_MISSES.MISS_CAUSES_A_WALK
508 .Pq Event 85H , Umask 01H
509 Misses in ITLB that causes a page walk of any page
511 .It Li ITLB_MISSES.WALK_COMPLETED_4K
512 .Pq Event 85H , Umask 02H
513 Completed page walks due to misses in ITLB 4K page
515 .It Li TLB_MISSES.WALK_COMPLETED_2M_4M
516 .Pq Event 85H , Umask 04H
517 Completed page walks due to misses in ITLB 2M/4M
519 .It Li ITLB_MISSES.WALK_COMPLETED
520 .Pq Event 85H , Umask 0EH
521 Completed page walks in ITLB of any page size.
522 .It Li ITLB_MISSES.WALK_DURATION
523 .Pq Event 85H , Umask 10H
524 Cycle PMH is busy with a walk.
525 .It Li ITLB_MISSES.STLB_HIT_4K
526 .Pq Event 85H , Umask 20H
527 ITLB misses that hit STLB (4K).
528 .It Li ITLB_MISSES.STLB_HIT_2M
529 .Pq Event 85H , Umask 40H
530 ITLB misses that hit STLB (2K).
531 .It Li ITLB_MISSES.STLB_HIT
532 .Pq Event 85H , Umask 60H
533 TLB misses that hit STLB.
536 .Pq Event 87H , Umask 01H
537 Stalls caused by changing prefix length of the
539 .It Li ILD_STALL.IQ_FULL
540 .Pq Event 87H , Umask 04H
541 Stall cycles due to IQ is full.
542 .It Li BR_INST_EXEC.NONTAKEN_COND
543 .Pq Event 88H , Umask 41H
544 Count conditional near branch instructions that were executed (but not
545 necessarily retired) and not taken.
546 .It Li BR_INST_EXEC.TAKEN_COND
547 .Pq Event 88H , Umask 81H
548 Count conditional near branch instructions that were executed (but not
549 necessarily retired) and taken.
550 .It Li BR_INST_EXEC.DIRECT_JMP
551 .Pq Event 88H , Umask 82H
552 Count all unconditional near branch instructions excluding calls and
554 .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
555 .Pq Event 88H , Umask 84H
556 Count executed indirect near branch instructions that are not calls nor
558 .It Li BR_INST_EXEC.RETURN_NEAR
559 .Pq Event 88H , Umask 88H
560 Count indirect near branches that have a return mnemonic.
561 .It Li BR_INST_EXEC.DIRECT_NEAR_CALL
562 .Pq Event 88H , Umask 90H
563 Count unconditional near call branch instructions, excluding non call
565 .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
566 .Pq Event 88H , Umask A0H
567 Count indirect near calls, including both register and memory indirect,
569 .It Li BR_INST_EXEC.ALL_BRANCHES
570 .Pq Event 88H , Umask FFH
571 Counts all near executed branches (not necessarily retired).
572 .It Li BR_MISP_EXEC.NONTAKEN_COND
573 .Pq Event 89H , Umask 41H
574 Count conditional near branch instructions mispredicted as nontaken.
575 .It Li BR_MISP_EXEC.TAKEN_COND
576 .Pq Event 89H , Umask 81H
577 Count conditional near branch instructions mispredicted as taken.
578 .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
579 .Pq Event 89H , Umask 84H
580 Count mispredicted indirect near branch instructions that are not calls
582 .It Li BR_MISP_EXEC.RETURN_NEAR
583 .Pq Event 89H , Umask 88H
584 Count mispredicted indirect near branches that have a return mnemonic.
585 .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
586 .Pq Event 89H , Umask 90H
587 Count mispredicted unconditional near call branch instructions, excluding
588 non call branch, executed.
589 .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
590 .Pq Event 89H , Umask A0H
591 Count mispredicted indirect near calls, including both register and memory
593 .It Li BR_MISP_EXEC.ALL_BRANCHES
594 .Pq Event 89H , Umask FFH
595 Counts all mispredicted near executed branches (not necessarily retired).
596 .It Li IDQ_UOPS_NOT_DELIVERED.CORE
597 .Pq Event 9CH , Umask 01H
598 Count number of non-delivered uops to RAT per
600 .It Li UOPS_EXECUTED_PORT.PORT_0
601 .Pq Event A1H , Umask 01H
602 Cycles which a Uop is dispatched on port 0 in this
604 .It Li UOPS_EXECUTED_PORT.PORT_1
605 .Pq Event A1H , Umask 02H
606 Cycles which a Uop is dispatched on port 1 in this
608 .It Li UOPS_EXECUTED_PORT.PORT_2
609 .Pq Event A1H , Umask 04H
610 Cycles which a Uop is dispatched on port 2 in this
612 .It Li UOPS_EXECUTED_PORT.PORT_3
613 .Pq Event A1H , Umask 08H
614 Cycles which a Uop is dispatched on port 3 in this
616 .It Li UOPS_EXECUTED_PORT.PORT_4
617 .Pq Event A1H , Umask 10H
618 Cycles which a Uop is dispatched on port 4 in this
620 .It Li UOPS_EXECUTED_PORT.PORT_5
621 .Pq Event A1H , Umask 20H
622 Cycles which a Uop is dispatched on port 5 in this
624 .It Li UOPS_EXECUTED_PORT.PORT_6
625 .Pq Event A1H , Umask 40H
626 Cycles which a Uop is dispatched on port 6 in this
628 .It Li UOPS_EXECUTED_PORT.PORT_7
629 .Pq Event A1H , Umask 80H
630 Cycles which a Uop is dispatched on port 7 in this
632 .It Li RESOURCE_STALLS.ANY
633 .Pq Event A2H , Umask 01H
634 Cycles Allocation is stalled due to Resource Related
636 .It Li RESOURCE_STALLS.RS
637 .Pq Event A2H , Umask 04H
638 Cycles stalled due to no eligible RS entry available.
639 .It Li RESOURCE_STALLS.SB
640 .Pq Event A2H , Umask 08H
641 Cycles stalled due to no store buffers available (not
642 including draining form sync).
643 .It Li RESOURCE_STALLS.ROB
644 .Pq Event A2H , Umask 10H
645 Cycles stalled due to re-order buffer full.
646 .It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING
647 .Pq Event A3H , Umask 01H
648 Cycles with pending L2 miss loads.
649 Set Cmask=2 to count cycle.
650 .It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING
651 .Pq Event A3H , Umask 02H
652 Cycles with pending memory loads.
653 Set Cmask=2 to count cycle.
654 .It Li CYCLE_ACTIVITY.STALLS_L2_PENDING
655 .Pq Event A3H , Umask 05H
656 Number of loads missed L2.
657 .It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING
658 .Pq Event A3H , Umask 08H
659 Cycles with pending L1 cache miss loads.
660 Set Cmask=8 to count cycle.
661 .It Li ITLB.ITLB_FLUSH
662 .Pq Event AEH , Umask 01H
663 Counts the number of ITLB flushes, includes
665 .It Li OFFCORE_REQUESTS.DEMAND_DATA_RD
666 .Pq Event B0H , Umask 01H
667 Demand data read requests sent to uncore.
668 .It Li OFFCORE_REQUESTS.DEMAND_CODE_RD
669 .Pq Event B0H , Umask 02H
670 Demand code read requests sent to uncore.
671 .It Li OFFCORE_REQUESTS.DEMAND_RFO
672 .Pq Event B0H , Umask 04H
673 Demand RFO read requests sent to uncore, including
674 regular RFOs, locks, ItoM.
675 .It Li OFFCORE_REQUESTS.ALL_DATA_RD
676 .Pq Event B0H , Umask 08H
677 Data read requests sent to uncore (demand and prefetch).
678 .It Li UOPS_EXECUTED.CORE
679 .Pq Event B1H , Umask 02H
680 Counts total number of uops to be executed per-core
682 .It Li OFF_CORE_RESPONSE_0
683 .Pq Event B7H , Umask 01H
685 .It Li OFF_CORE_RESPONSE_1
686 .Pq Event BBH , Umask 01H
688 .It Li PAGE_WALKER_LOADS.DTLB_L1
689 .Pq Event BCH , Umask 11H
690 Number of DTLB page walker loads that hit in the
692 .It Li PAGE_WALKER_LOADS.ITLB_L1
693 .Pq Event BCH , Umask 21H
694 Number of ITLB page walker loads that hit in the
696 .It Li PAGE_WALKER_LOADS.DTLB_L2
697 .Pq Event BCH , Umask 12H
698 Number of DTLB page walker loads that hit in the L2.
699 .It Li PAGE_WALKER_LOADS.ITLB_L2
700 .Pq Event BCH , Umask 22H
701 Number of ITLB page walker loads that hit in the L2.
702 .It Li PAGE_WALKER_LOADS.DTLB_L3
703 .Pq Event BCH , Umask 14H
704 Number of DTLB page walker loads that hit in the L3.
705 .It Li PAGE_WALKER_LOADS.ITLB_L3
706 .Pq Event BCH , Umask 24H
707 Number of ITLB page walker loads that hit in the L3.
708 .It Li PAGE_WALKER_LOADS.DTLB_MEMORY
709 .Pq Event BCH , Umask 18H
710 Number of DTLB page walker loads from memory.
711 .It Li PAGE_WALKER_LOADS.ITLB_MEMORY
712 .Pq Event BCH , Umask 28H
713 Number of ITLB page walker loads from memory.
714 .It Li TLB_FLUSH.DTLB_THREAD
715 .Pq Event BDH , Umask 01H
716 DTLB flush attempts of the thread-specific entries.
717 .It Li TLB_FLUSH.STLB_ANY
718 .Pq Event BDH , Umask 20H
719 Count number of STLB flush attempts.
720 .It Li INST_RETIRED.ANY_P
721 .Pq Event C0H , Umask 00H
722 Number of instructions at retirement.
723 .It Li INST_RETIRED.ALL
724 .Pq Event C0H , Umask 01H
725 Precise instruction retired event with HW to reduce
726 effect of PEBS shadow in IP distribution.
727 .It Li OTHER_ASSISTS.AVX_TO_SSE
728 .Pq Event C1H , Umask 08H
729 Number of transitions from AVX-256 to legacy SSE
730 when penalty applicable.
731 .It Li OTHER_ASSISTS.SSE_TO_AVX
732 .Pq Event C1H , Umask 10H
733 Number of transitions from SSE to AVX-256 when
735 .It Li OTHER_ASSISTS.ANY_WB_ASSIST
736 .Pq Event C1H , Umask 40H
737 Number of microcode assists invoked by HW upon
739 .It Li UOPS_RETIRED.ALL
740 .Pq Event C2H , Umask 01H
741 Counts the number of micro-ops retired, Use
742 cmask=1 and invert to count active cycles or stalled
744 .It Li UOPS_RETIRED.RETIRE_SLOTS
745 .Pq Event C2H , Umask 02H
746 Counts the number of retirement slots used each
748 .It Li MACHINE_CLEARS.MEMORY_ORDERING
749 .Pq Event C3H , Umask 02H
750 Counts the number of machine clears due to memory
752 .It Li MACHINE_CLEARS.SMC
753 .Pq Event C3H , Umask 04H
754 Number of self-modifying-code machine clears
756 .It Li MACHINE_CLEARS.MASKMOV
757 .Pq Event C3H , Umask 20H
758 Counts the number of executed AVX masked load
759 operations that refer to an illegal address range with
760 the mask bits set to 0.
761 .It Li BR_INST_RETIRED.ALL_BRANCHES
762 .Pq Event C4H , Umask 00H
763 Branch instructions at retirement.
764 .It Li BR_INST_RETIRED.CONDITIONAL
765 .Pq Event C4H , Umask 01H
766 Counts the number of conditional branch instructions Supports PEBS
768 .It Li BR_INST_RETIRED.NEAR_CALL
769 .Pq Event C4H , Umask 02H
770 Direct and indirect near call instructions retired.
771 .It Li BR_INST_RETIRED.ALL_BRANCHES
772 .Pq Event C4H , Umask 04H
773 Counts the number of branch instructions retired.
774 .It Li BR_INST_RETIRED.NEAR_RETURN
775 .Pq Event C4H , Umask 08H
776 Counts the number of near return instructions
778 .It Li BR_INST_RETIRED.NOT_TAKEN
779 .Pq Event C4H , Umask 10H
780 Counts the number of not taken branch instructions
782 It Li BR_INST_RETIRED.NEAR_TAKEN
783 .Pq Event C4H , Umask 20H
784 Number of near taken branches retired.
785 .It Li BR_INST_RETIRED.FAR_BRANCH
786 .Pq Event C4H , Umask 40H
787 Number of far branches retired.
788 .It Li BR_MISP_RETIRED.ALL_BRANCHES
789 .Pq Event C5H , Umask 00H
790 Mispredicted branch instructions at retirement
791 .It Li BR_MISP_RETIRED.CONDITIONAL
792 .Pq Event C5H , Umask 01H
793 Mispredicted conditional branch instructions retired.
794 .It Li BR_MISP_RETIRED.CONDITIONAL
795 .Pq Event C5H , Umask 04H
796 Mispredicted macro branch instructions retired.
797 .It Li FP_ASSIST.X87_OUTPUT
798 .Pq Event CAH , Umask 02H
799 Number of X87 FP assists due to Output values.
800 .It Li FP_ASSIST.X87_INPUT
801 .Pq Event CAH , Umask 04H
802 Number of X87 FP assists due to input values.
803 .It Li FP_ASSIST.SIMD_OUTPUT
804 .Pq Event CAH , Umask 08H
805 Number of SIMD FP assists due to Output values.
806 .It Li FP_ASSIST.SIMD_INPUT
807 .Pq Event CAH , Umask 10H
808 Number of SIMD FP assists due to input values.
810 .Pq Event CAH , Umask 1EH
811 Cycles with any input/output SSE* or FP assists.
812 .It Li ROB_MISC_EVENTS.LBR_INSERTS
813 .Pq Event CCH , Umask 20H
814 Count cases of saving new LBR records by hardware.
815 .It Li MEM_TRANS_RETIRED.LOAD_LATENCY
816 .Pq Event CDH , Umask 01H
817 Randomly sampled loads whose latency is above a
818 user defined threshold.
819 A small fraction of the overall loads are sampled due to randomization.
820 .It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS
821 .Pq Event D0H , Umask 11H
822 Count retired load uops that missed the STLB.
823 .It Li MEM_UOPS_RETIRED.STLB_MISS_STORES
824 .Pq Event D0H , Umask 12H
825 Count retired store uops that missed the STLB.
826 .It Li MEM_UOPS_RETIRED.SPLIT_LOADS
827 .Pq Event D0H , Umask 41H
828 Count retired load uops that were split across a cache line.
829 .It Li MEM_UOPS_RETIRED.SPLIT_STORES
830 .Pq Event D0H , Umask 42H
831 Count retired store uops that were split across a cache line.
832 .It Li MEM_UOPS_RETIRED.ALL_LOADS
833 .Pq Event D0H , Umask 81H
834 Count all retired load uops.
835 .It Li MEM_UOPS_RETIRED.ALL_STORES
836 .Pq Event D0H , Umask 82H
837 Count all retired store uops.
838 .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
839 .Pq Event D1H , Umask 01H
840 Retired load uops with L1 cache hits as data sources.
841 .It Li MEM_LOAD_UOPS_RETIRED.L2_HIT
842 .Pq Event D1H , Umask 02H
843 Retired load uops with L2 cache hits as data sources.
844 .It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT
845 .Pq Event D1H , Umask 04H
846 Retired load uops with LLC cache hits as data
848 .It Li MEM_LOAD_UOPS_RETIRED.L2_MISS
849 .Pq Event D1H , Umask 10H
850 Retired load uops missed L2.
851 Unknown data source excluded.
852 .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB
853 .Pq Event D1H , Umask 40H
854 Retired load uops which data sources were load uops
855 missed L1 but hit FB due to preceding miss to the
856 same cache line with data not ready.
857 .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS
858 .Pq Event D2H , Umask 01H
859 Retired load uops which data sources were LLC hit
860 and cross-core snoop missed in on-pkg core cache.
861 .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT
862 .Pq Event D2H , Umask 02H
863 Retired load uops which data sources were LLC and
864 cross-core snoop hits in on-pkg core cache.
865 .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM
866 .Pq Event D2H , Umask 04H
867 Retired load uops which data sources were HitM
868 responses from shared LLC.
869 .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE
870 .Pq Event D2H , Umask 08H
871 Retired load uops which data sources were hits in
872 LLC without snoops required.
873 .It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM
874 .Pq Event D3H , Umask 01H
875 Retired load uops which data sources missed LLC but
876 serviced from local dram.
878 .Pq Event E6H , Umask 1FH
879 Number of front end re-steers due to BPU
881 .It Li L2_TRANS.DEMAND_DATA_RD
882 .Pq Event F0H , Umask 01H
883 Demand Data Read requests that access L2 cache.
885 .Pq Event F0H , Umask 02H
886 RFO requests that access L2 cache.
887 .It Li L2_TRANS.CODE_RD
888 .Pq Event F0H , Umask 04H
889 L2 cache accesses when fetching instructions.
890 .It Li L2_TRANS.ALL_PF
891 .Pq Event F0H , Umask 08H
892 Any MLC or LLC HW prefetch accessing L2, including
894 .It Li L2_TRANS.L1D_WB
895 .Pq Event F0H , Umask 10H
896 L1D writebacks that access L2 cache.
897 .It Li L2_TRANS.L2_FILL
898 .Pq Event F0H , Umask 20H
899 L2 fill requests that access L2 cache.
900 .It Li L2_TRANS.L2_WB
901 .Pq Event F0H , Umask 40H
902 L2 writebacks that access L2 cache.
903 .It Li L2_TRANS.ALL_REQUESTS
904 .Pq Event F0H , Umask 80H
905 Transactions accessing L2 pipe.
907 .Pq Event F1H , Umask 01H
908 L2 cache lines in I state filling L2.
910 .Pq Event F1H , Umask 02H
911 L2 cache lines in S state filling L2.
913 .Pq Event F1H , Umask 04H
914 L2 cache lines in E state filling L2.
915 .It Li L2_LINES_IN.ALL
916 .Pq Event F1H , Umask 07H
917 L2 cache lines filling L2.
918 .It Li L2_LINES_OUT.DEMAND_CLEAN
919 .Pq Event F2H , Umask 05H
920 Clean L2 cache lines evicted by demand.
921 .It Li L2_LINES_OUT.DEMAND_DIRTY
922 .Pq Event F2H , Umask 06H
923 Dirty L2 cache lines evicted by demand.
932 .Xr pmc.haswelluc 3 ,
934 .Xr pmc.ivybridge 3 ,
935 .Xr pmc.ivybridgexeon 3 ,
941 .Xr pmc.sandybridge 3 ,
942 .Xr pmc.sandybridgeuc 3 ,
943 .Xr pmc.sandybridgexeon 3 ,
948 .Xr pmc.westmereuc 3 ,
953 Support for the Haswell Xeon microarchitecture first appeared in
958 library was written by
960 .Aq jkoshy@FreeBSD.org .
961 The support for the Haswell Xeon
962 microarchitecture was written by
963 .An "Randall Stewart"
964 .Aq rrs@FreeBSD.org .