2 .\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara@gmail.com>
3 .\" All rights reserved.
5 .\" Redistribution and use in source and binary forms, with or without
6 .\" modification, are permitted provided that the following conditions
8 .\" 1. Redistributions of source code must retain the above copyright
9 .\" notice, this list of conditions and the following disclaimer.
10 .\" 2. Redistributions in binary form must reproduce the above copyright
11 .\" notice, this list of conditions and the following disclaimer in the
12 .\" documentation and/or other materials provided with the distribution.
14 .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 .Nd measurement events for
44 CPUs contain PMCs conforming to version 2 of the
46 performance measurement architecture.
47 These CPUs may contain up to two classes of PMCs:
48 .Bl -tag -width "Li PMC_CLASS_IAP"
50 Fixed-function counters that count only one hardware event per counter.
52 Programmable counters that may be configured to count one of a defined
53 set of hardware events.
56 The number of PMCs available in each class and their widths need to be
57 determined at run time by calling
60 Intel Haswell Xeon PMCs are documented in
62 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
63 .%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C"
64 .%N "Order Number: 325462-052US"
66 .%Q "Intel Corporation"
68 .Ss HASWELL FIXED FUNCTION PMCS
69 These PMCs and their supported events are documented in
71 .Ss HASWELL PROGRAMMABLE PMCS
72 The programmable PMCs support the following capabilities:
73 .Bl -column "PMC_CAP_INTERRUPT" "Support"
74 .It Em Capability Ta Em Support
75 .It PMC_CAP_CASCADE Ta \&No
76 .It PMC_CAP_EDGE Ta Yes
77 .It PMC_CAP_INTERRUPT Ta Yes
78 .It PMC_CAP_INVERT Ta Yes
79 .It PMC_CAP_READ Ta Yes
80 .It PMC_CAP_PRECISE Ta \&No
81 .It PMC_CAP_SYSTEM Ta Yes
82 .It PMC_CAP_TAGGING Ta \&No
83 .It PMC_CAP_THRESHOLD Ta Yes
84 .It PMC_CAP_USER Ta Yes
85 .It PMC_CAP_WRITE Ta Yes
88 Event specifiers for these PMCs support the following common
90 .Bl -tag -width indent
91 .It Li rsp= Ns Ar value
92 Configure the Off-core Response bits.
93 .Bl -tag -width indent
95 Counts the number of demand and DCU prefetch data reads of full
96 and partial cachelines as well as demand data page table entry
97 cacheline reads. Does not count L2 data read prefetches or
100 Counts the number of demand and DCU prefetch reads for ownership (RFO)
101 requests generated by a write to data cacheline. Does not count L2 RFO
103 .It Li REQ_DMND_IFETCH
104 Counts the number of demand and DCU prefetch instruction cacheline reads.
105 Does not count L2 code read prefetches.
107 Counts the number of writeback (modified to exclusive) transactions.
108 .It Li REQ_PF_DATA_RD
109 Counts the number of data cacheline reads generated by L2 prefetchers.
111 Counts the number of RFO requests generated by L2 prefetchers.
113 Counts the number of code reads generated by L2 prefetchers.
114 .It Li REQ_PF_LLC_DATA_RD
115 L2 prefetcher to L3 for loads.
116 .It Li REQ_PF_LLC_RFO
117 RFO requests generated by L2 prefetcher
118 .It Li REQ_PF_LLC_IFETCH
119 L2 prefetcher to L3 for instruction fetches.
121 Bus lock and split lock requests.
123 Streaming store requests.
125 Any other request that crosses IDI, including I/O.
127 Catch all value for any response types.
128 .It Li RES_SUPPLIER_NO_SUPP
129 No Supplier Information available.
130 .It Li RES_SUPPLIER_LLC_HITM
131 M-state initial lookup stat in L3.
132 .It Li RES_SUPPLIER_LLC_HITE
134 .It Li RES_SUPPLIER_LLC_HITS
136 .It Li RES_SUPPLIER_LLC_HITF
138 .It Li RES_SUPPLIER_LOCAL
139 Local DRAM Controller.
140 .It Li RES_SNOOP_SNP_NONE
141 No details on snoop-related information.
142 .It Li RES_SNOOP_SNP_NO_NEEDED
143 No snoop was needed to satisfy the request.
144 .It Li RES_SNOOP_SNP_MISS
145 A snoop was needed and it missed all snooped caches:
146 -For LLC Hit, ReslHitl was returned by all cores
147 -For LLC Miss, Rspl was returned by all sockets and data was returned from
149 .It Li RES_SNOOP_HIT_NO_FWD
150 A snoop was needed and it hits in at least one snooped cache. Hit denotes a
151 cache-line was valid before snoop effect. This includes:
152 -Snoop Hit w/ Invalidation (LLC Hit, RFO)
153 -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD)
154 -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S)
155 In the LLC Miss case, data is returned from DRAM.
156 .It Li RES_SNOOP_HIT_FWD
157 A snoop was needed and data was forwarded from a remote socket.
159 -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
160 .It Li RES_SNOOP_HITM
161 A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a
162 cache-line was in modified state before effect as a results of snoop. This
164 -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD)
165 -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO)
166 -Snoop MtoS (LLC Hit, IFetch/Data_RD).
168 Target was non-DRAM system address. This includes MMIO transactions.
170 .It Li cmask= Ns Ar value
171 Configure the PMC to increment only if the number of configured
172 events measured in a cycle is greater than or equal to
175 Configure the PMC to count the number of de-asserted to asserted
176 transitions of the conditions expressed by the other qualifiers.
177 If specified, the counter will increment only once whenever a
178 condition becomes true, irrespective of the number of clocks during
179 which the condition remains true.
181 Invert the sense of comparison when the
183 qualifier is present, making the counter increment when the number of
184 events per cycle is less than the value specified by the
188 Configure the PMC to count events happening at processor privilege
191 Configure the PMC to count events occurring at privilege levels 1, 2
199 qualifiers are specified, the default is to enable both.
200 .Ss Event Specifiers (Programmable PMCs)
201 Haswell programmable PMCs support the following events:
202 .Bl -tag -width indent
203 .It Li LD_BLOCKS.STORE_FORWARD
204 .Pq Event 03H , Umask 02H
205 Loads blocked by overlapping with store buffer that
207 .It Li MISALIGN_MEM_REF.LOADS
208 .Pq Event 05H , Umask 01H
209 Speculative cache-line split load uops dispatched to
211 .It Li MISALIGN_MEM_REF.STORES
212 .Pq Event 05H , Umask 02H
213 Speculative cache-line split Store-address uops
215 .It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
216 .Pq Event 07H , Umask 01H
217 False dependencies in MOB due to partial compare
219 .It Li DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK
220 .Pq Event 08H , Umask 01H
221 Misses in all TLB levels that cause a page walk of any
223 .It Li DTLB_LOAD_MISSES.WALK_COMPLETED_4K
224 .Pq Event 08H , Umask 02H
225 Completed page walks due to demand load misses
226 that caused 4K page walks in any TLB levels.
227 .It Li DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K
228 .Pq Event 08H , Umask 02H
229 Completed page walks due to demand load misses
230 that caused 2M/4M page walks in any TLB levels.
231 .It Li DTLB_LOAD_MISSES.WALK_COMPLETED
232 .Pq Event 08H , Umask 0EH
233 Completed page walks in any TLB of any page size
234 due to demand load misses
235 .It Li DTLB_LOAD_MISSES.WALK_DURATION
236 .Pq Event 08H , Umask 10H
237 Cycle PMH is busy with a walk.
238 .It Li DTLB_LOAD_MISSES.STLB_HIT_4K
239 .Pq Event 08H , Umask 20H
240 Load misses that missed DTLB but hit STLB (4K).
241 .It Li DTLB_LOAD_MISSES.STLB_HIT_2M
242 .Pq Event 08H , Umask 40H
243 Load misses that missed DTLB but hit STLB (2M).
244 .It Li DTLB_LOAD_MISSES.STLB_HIT
245 .Pq Event 08H , Umask 60H
246 Number of cache load STLB hits. No page walk.
247 .It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS
248 .Pq Event 08H , Umask 80H
249 DTLB demand load misses with low part of linear-to-
250 physical address translation missed
251 .It Li INT_MISC.RECOVERY_CYCLES
252 .Pq Event 0DH , Umask 03H
253 Cycles waiting to recover after Machine Clears
254 except JEClear. Set Cmask= 1.
255 .It Li UOPS_ISSUED.ANY
256 .Pq Event 0EH , Umask 01H
257 ncrements each cycle the # of Uops issued by the
259 Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles
261 .It Li UOPS_ISSUED.FLAGS_MERGE
262 .Pq Event 0EH , Umask 10H
263 Number of flags-merge uops allocated. Such uops
265 .It Li UOPS_ISSUED.SLOW_LEA
266 .Pq Event 0EH , Umask 20H
267 Number of slow LEA or similar uops allocated. Such
268 uop has 3 sources (e.g. 2 sources + immediate)
269 regardless if as a result of LEA instruction or not.
270 .It Li UOPS_ISSUED.SiNGLE_MUL
271 .Pq Event 0EH , Umask 40H
272 Number of multiply packed/scalar single precision
274 .It Li L2_RQSTS.DEMAND_DATA_RD_MISS
275 .Pq Event 24H , Umask 21H
276 Demand Data Read requests that missed L2, no
278 .It Li L2_RQSTS.DEMAND_DATA_RD_HIT
279 .Pq Event 24H , Umask 41H
280 Demand Data Read requests that hit L2 cache.
281 .It Li L2_RQSTS.ALL_DEMAND_DATA_RD
282 .Pq Event 24H , Umask E1H
283 Counts any demand and L1 HW prefetch data load
285 .It Li L2_RQSTS.RFO_HIT
286 .Pq Event 24H , Umask 42H
287 Counts the number of store RFO requests that hit
289 .It Li L2_RQSTS.RFO_MISS
290 .Pq Event 24H , Umask 22H
291 Counts the number of store RFO requests that miss
293 .It Li L2_RQSTS.ALL_RFO
294 .Pq Event 24H , Umask E2H
295 Counts all L2 store RFO requests.
296 .It Li L2_RQSTS.CODE_RD_HIT
297 .Pq Event 24H , Umask 44H
298 Number of instruction fetches that hit the L2 cache.
299 .It Li L2_RQSTS.CODE_RD_MISS
300 .Pq Event 24H , Umask 24H
301 Number of instruction fetches that missed the L2
303 .It Li L2_RQSTS.ALL_DEMAND_MISS
304 .Pq Event 24H , Umask 27H
305 Demand requests that miss L2 cache.
306 .It Li L2_RQSTS.ALL_DEMAND_REFERENCES
307 .Pq Event 24H , Umask E7H
308 Demand requests to L2 cache.
309 .It Li L2_RQSTS.ALL_CODE_RD
310 .Pq Event 24H , Umask E4H
311 Counts all L2 code requests.
312 .It Li L2_RQSTS.L2_PF_HIT
313 .Pq Event 24H , Umask 50H
314 Counts all L2 HW prefetcher requests that hit L2.
315 .It Li L2_RQSTS.L2_PF_MISS
316 .Pq Event 24H , Umask 30H
317 Counts all L2 HW prefetcher requests that missed
319 .It Li L2_RQSTS.ALL_PF
320 .Pq Event 24H , Umask F8H
321 Counts all L2 HW prefetcher requests.
323 .Pq Event 24H , Umask 3FH
324 All requests that missed L2.
325 .It Li L2_RQSTS.REFERENCES
326 .Pq Event 24H , Umask FFH
327 All requests to L2 cache.
328 .It Li L2_DEMAND_RQSTS.WB_HIT
329 .Pq Event 27H , Umask 50H
330 Not rejected writebacks that hit L2 cache
331 .It Li LONGEST_LAT_CACHE.REFERENCE
332 .Pq Event 2EH , Umask 4FH
333 This event counts requests originating from the core
334 that reference a cache line in the last level cache.
335 .It Li LONGEST_LAT_CACHE.MISS
336 .Pq Event 2EH , Umask 41H
337 This event counts each cache miss condition for
338 references to the last level cache.
339 .It Li CPU_CLK_UNHALTED.THREAD_P
340 .Pq Event 3CH , Umask 00H
341 Counts the number of thread cycles while the thread
342 is not in a halt state. The thread enters the halt state
343 when it is running the HLT instruction. The core
344 frequency may change from time to time due to
345 power or thermal throttling.
346 .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK
347 .Pq Event 3CH , Umask 01H
348 Increments at the frequency of XCLK (100 MHz)
350 .It Li L1D_PEND_MISS.PENDING
351 .Pq Event 48H , Umask 01H
352 Increments the number of outstanding L1D misses
353 every cycle. Set Cmaks = 1 and Edge =1 to count
355 .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
356 .Pq Event 49H , Umask 01H
357 Miss in all TLB levels causes an page walk of any
358 page size (4K/2M/4M/1G).
359 .It Li DTLB_STORE_MISSES.WALK_COMPLETED_4K
360 .Pq Event 49H , Umask 02H
361 Completed page walks due to store misses in one or
362 more TLB levels of 4K page structure.
363 .It Li DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M
364 .Pq Event 49H , Umask 04H
365 Completed page walks due to store misses in one or
366 more TLB levels of 2M/4M page structure.
367 .It Li DTLB_STORE_MISSES.WALK_COMPLETED
368 .Pq Event 49H , Umask 0EH
369 Completed page walks due to store miss in any TLB
370 levels of any page size (4K/2M/4M/1G).
371 .It Li DTLB_STORE_MISSES.WALK_DURATION
372 .Pq Event 49H , Umask 10H
373 Cycles PMH is busy with this walk.
374 .It Li DTLB_STORE_MISSES.STLB_HIT_4K
375 .Pq Event 49H , Umask 20H
376 Store misses that missed DTLB but hit STLB (4K).
377 .It Li DTLB_STORE_MISSES.STLB_HIT_2M
378 .Pq Event 49H , Umask 40H
379 Store misses that missed DTLB but hit STLB (2M).
380 .It Li DTLB_STORE_MISSES.STLB_HIT
381 .Pq Event 49H , Umask 60H
382 Store operations that miss the first TLB level but hit
383 the second and do not cause page walks.
384 .It Li DTLB_STORE_MISSES.PDE_CACHE_MISS
385 .Pq Event 49H , Umask 80H
386 DTLB store misses with low part of linear-to-physical
387 address translation missed.
388 .It Li LOAD_HIT_PRE.SW_PF
389 .Pq Event 4CH , Umask 01H
390 Non-SW-prefetch load dispatches that hit fill buffer
391 allocated for S/W prefetch.
392 .It Li LOAD_HIT_PRE.HW_PF
393 .Pq Event 4CH , Umask 02H
394 Non-SW-prefetch load dispatches that hit fill buffer
395 allocated for H/W prefetch.
396 .It Li L1D.REPLACEMENT
397 .Pq Event 51H , Umask 01H
398 Counts the number of lines brought into the L1 data
400 .It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED
401 .Pq Event 58H , Umask 04H
402 Number of integer Move Elimination candidate uops
403 that were not eliminated.
404 .It Li MOVE_ELIMINATION.SMID_NOT_ELIMINATED
405 .Pq Event 58H , Umask 08H
406 Number of SIMD Move Elimination candidate uops
407 that were not eliminated.
408 .It Li MOVE_ELIMINATION.INT_ELIMINATED
409 .Pq Event 58H , Umask 01H
410 Unhalted core cycles when the thread is in ring 0.
411 .It Li MOVE_ELIMINATION.SMID_ELIMINATED
412 .Pq Event 58H , Umask 02H
413 Number of SIMD Move Elimination candidate uops
414 that were eliminated.
415 .It Li CPL_CYCLES.RING0
416 .Pq Event 5CH , Umask 02H
417 Unhalted core cycles when the thread is in ring 0.
418 .It Li CPL_CYCLES.RING123
419 .Pq Event 5CH , Umask 01H
420 Unhalted core cycles when the thread is not in ring 0.
421 .It Li RS_EVENTS.EMPTY_CYCLES
422 .Pq Event 5EH , Umask 01H
423 Cycles the RS is empty for the thread.
424 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
425 .Pq Event 60H , Umask 01H
426 Offcore outstanding Demand Data Read transactions
427 in SQ to uncore. Set Cmask=1 to count cycles.
428 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD
429 .Pq Event 60H , Umask 02H
430 Offcore outstanding Demand code Read transactions
431 in SQ to uncore. Set Cmask=1 to count cycles.
432 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
433 .Pq Event 60H , Umask 04H
434 Offcore outstanding RFO store transactions in SQ to
435 uncore. Set Cmask=1 to count cycles.
436 .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
437 .Pq Event 60H , Umask 08H
438 Offcore outstanding cacheable data read
439 transactions in SQ to uncore. Set Cmask=1 to count
441 .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
442 .Pq Event 63H , Umask 01H
443 Cycles in which the L1D and L2 are locked, due to a
444 UC lock or split lock.
445 .It Li LOCK_CYCLES.CACHE_LOCK_DURATION
446 .Pq Event 63H , Umask 02H
447 Cycles in which the L1D is locked.
449 .Pq Event 79H , Umask 02H
450 Counts cycles the IDQ is empty.
452 .Pq Event 79H , Umask 04H
453 Increment each cycle # of uops delivered to IDQ from
455 Set Cmask = 1 to count cycles.
457 .Pq Event 79H , Umask 08H
458 Increment each cycle. # of uops delivered to IDQ
460 Set Cmask = 1 to count cycles.
461 .It Li IDQ.MS_DSB_UOPS
462 .Pq Event 79H , Umask 10H
463 Increment each cycle # of uops delivered to IDQ
464 when MS_busy by DSB. Set Cmask = 1 to count
465 cycles. Add Edge=1 to count # of delivery.
466 .It Li IDQ.MS_MITE_UOPS
467 .Pq Event 79H , Umask 20H
468 ncrement each cycle # of uops delivered to IDQ
469 when MS_busy by MITE. Set Cmask = 1 to count
472 .Pq Event 79H , Umask 30H
473 Increment each cycle # of uops delivered to IDQ from
474 MS by either DSB or MITE. Set Cmask = 1 to count
476 .It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS
477 .Pq Event 79H , Umask 18H
478 Counts cycles DSB is delivered at least one uops. Set
480 .It Li IDQ.ALL_DSB_CYCLES_4_UOPS
481 .Pq Event 79H , Umask 18H
482 Counts cycles DSB is delivered four uops. Set Cmask
484 .It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS
485 .Pq Event 79H , Umask 24H
486 Counts cycles MITE is delivered at least one uops. Set
488 .It Li IDQ.ALL_MITE_CYCLES_4_UOPS
489 .Pq Event 79H , Umask 24H
490 Counts cycles MITE is delivered four uops. Set Cmask
492 .It Li IDQ.MITE_ALL_UOPS
493 .Pq Event 79H , Umask 3CH
494 # of uops delivered to IDQ from any path.
496 .Pq Event 80H , Umask 02H
497 Number of Instruction Cache, Streaming Buffer and
498 Victim Cache Misses. Includes UC accesses.
499 .It Li ITLB_MISSES.MISS_CAUSES_A_WALK
500 .Pq Event 85H , Umask 01H
501 Misses in ITLB that causes a page walk of any page
503 .It Li ITLB_MISSES.WALK_COMPLETED_4K
504 .Pq Event 85H , Umask 02H
505 Completed page walks due to misses in ITLB 4K page
507 .It Li TLB_MISSES.WALK_COMPLETED_2M_4M
508 .Pq Event 85H , Umask 04H
509 Completed page walks due to misses in ITLB 2M/4M
511 .It Li ITLB_MISSES.WALK_COMPLETED
512 .Pq Event 85H , Umask 0EH
513 Completed page walks in ITLB of any page size.
514 .It Li ITLB_MISSES.WALK_DURATION
515 .Pq Event 85H , Umask 10H
516 Cycle PMH is busy with a walk.
517 .It Li ITLB_MISSES.STLB_HIT_4K
518 .Pq Event 85H , Umask 20H
519 ITLB misses that hit STLB (4K).
520 .It Li ITLB_MISSES.STLB_HIT_2M
521 .Pq Event 85H , Umask 40H
522 ITLB misses that hit STLB (2K).
523 .It Li ITLB_MISSES.STLB_HIT
524 .Pq Event 85H , Umask 60H
525 TLB misses that hit STLB. No page walk.
527 .Pq Event 87H , Umask 01H
528 Stalls caused by changing prefix length of the
530 .It Li ILD_STALL.IQ_FULL
531 .Pq Event 87H , Umask 04H
532 Stall cycles due to IQ is full.
533 .It Li BR_INST_EXEC.COND
534 .Pq Event 88H , Umask 01H
535 Qualify conditional near branch instructions
536 executed, but not necessarily retired.
537 .It Li BR_INST_EXEC.DIRECT_JMP
538 .Pq Event 88H , Umask 02H
539 Qualify all unconditional near branch instructions
540 excluding calls and indirect branches.
541 .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
542 .Pq Event 88H , Umask 04H
543 Qualify executed indirect near branch instructions
544 that are not calls nor returns.
545 .It Li BR_INST_EXEC.RETURN_NEAR
546 .Pq Event 88H , Umask 08H
547 Qualify indirect near branches that have a return
549 .It Li BR_INST_EXEC.DIRECT_NEAR_CALL
550 .Pq Event 88H , Umask 10H
551 Qualify unconditional near call branch instructions,
552 excluding non call branch, executed.
553 .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
554 .Pq Event 88H , Umask 20H
555 Qualify indirect near calls, including both register and
556 memory indirect, executed.
557 .It Li BR_INST_EXEC.NONTAKEN
558 .Pq Event 88H , Umask 40H
559 Qualify non-taken near branches executed.
560 .It Li BR_INST_EXEC.TAKEN
561 .Pq Event 88H , Umask 80H
562 Qualify taken near branches executed. Must combine
563 with 01H,02H, 04H, 08H, 10H, 20H.
564 .It Li BR_INST_EXEC.ALL_BRANCHES
565 .Pq Event 88H , Umask FFH
566 Counts all near executed branches (not necessarily
568 .It Li BR_MISP_EXEC.COND
569 .Pq Event 89H , Umask 01H
570 Qualify conditional near branch instructions
572 .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
573 .Pq Event 89H , Umask 04H
574 Qualify mispredicted indirect near branch
575 instructions that are not calls nor returns.
576 .It Li BR_MISP_EXEC.RETURN_NEAR
577 .Pq Event 89H , Umask 08H
578 Qualify mispredicted indirect near branches that
579 have a return mnemonic.
580 .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
581 .Pq Event 89H , Umask 10H
582 Qualify mispredicted unconditional near call branch
583 instructions, excluding non call branch, executed.
584 .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
585 .Pq Event 89H , Umask 20H
586 Qualify mispredicted indirect near calls, including
587 both register and memory indirect, executed.
588 .It Li BR_MISP_EXEC.NONTAKEN
589 .Pq Event 89H , Umask 40H
590 Qualify mispredicted non-taken near branches
592 .It Li BR_MISP_EXEC.TAKEN
593 .Pq Event 89H , Umask 80H
594 Qualify mispredicted taken near branches executed.
595 Must combine with 01H,02H, 04H, 08H, 10H, 20H.
596 .It Li BR_MISP_EXEC.ALL_BRANCHES
597 .Pq Event 89H , Umask FFH
598 Counts all near executed branches (not necessarily
600 .It Li IDQ_UOPS_NOT_DELIVERED.CORE
601 .Pq Event 9CH , Umask 01H
602 Count number of non-delivered uops to RAT per
604 .It Li UOPS_EXECUTED_PORT.PORT_0
605 .Pq Event A1H , Umask 01H
606 Cycles which a Uop is dispatched on port 0 in this
608 .It Li UOPS_EXECUTED_PORT.PORT_1
609 .Pq Event A1H , Umask 02H
610 Cycles which a Uop is dispatched on port 1 in this
612 .It Li UOPS_EXECUTED_PORT.PORT_2
613 .Pq Event A1H , Umask 04H
614 Cycles which a Uop is dispatched on port 2 in this
616 .It Li UOPS_EXECUTED_PORT.PORT_3
617 .Pq Event A1H , Umask 08H
618 Cycles which a Uop is dispatched on port 3 in this
620 .It Li UOPS_EXECUTED_PORT.PORT_4
621 .Pq Event A1H , Umask 10H
622 Cycles which a Uop is dispatched on port 4 in this
624 .It Li UOPS_EXECUTED_PORT.PORT_5
625 .Pq Event A1H , Umask 20H
626 Cycles which a Uop is dispatched on port 5 in this
628 .It Li UOPS_EXECUTED_PORT.PORT_6
629 .Pq Event A1H , Umask 40H
630 Cycles which a Uop is dispatched on port 6 in this
632 .It Li UOPS_EXECUTED_PORT.PORT_7
633 .Pq Event A1H , Umask 80H
634 Cycles which a Uop is dispatched on port 7 in this
636 .It Li RESOURCE_STALLS.ANY
637 .Pq Event A2H , Umask 01H
638 Cycles Allocation is stalled due to Resource Related
640 .It Li RESOURCE_STALLS.RS
641 .Pq Event A2H , Umask 04H
642 Cycles stalled due to no eligible RS entry available.
643 .It Li RESOURCE_STALLS.SB
644 .Pq Event A2H , Umask 08H
645 Cycles stalled due to no store buffers available (not
646 including draining form sync).
647 .It Li RESOURCE_STALLS.ROB
648 .Pq Event A2H , Umask 10H
649 Cycles stalled due to re-order buffer full.
650 .It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING
651 .Pq Event A3H , Umask 01H
652 Cycles with pending L2 miss loads. Set Cmask=2 to
654 .It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING
655 .Pq Event A3H , Umask 02H
656 Cycles with pending memory loads. Set Cmask=2 to
658 .It Li CYCLE_ACTIVITY.STALLS_L2_PENDING
659 .Pq Event A3H , Umask 05H
660 Number of loads missed L2.
661 .It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING
662 .Pq Event A3H , Umask 08H
663 Cycles with pending L1 cache miss loads. Set
664 Cmask=8 to count cycle.
665 .It Li ITLB.ITLB_FLUSH
666 .Pq Event AEH , Umask 01H
667 Counts the number of ITLB flushes, includes
669 .It Li OFFCORE_REQUESTS.DEMAND_DATA_RD
670 .Pq Event B0H , Umask 01H
671 Demand data read requests sent to uncore.
672 .It Li OFFCORE_REQUESTS.DEMAND_CODE_RD
673 .Pq Event B0H , Umask 02H
674 Demand code read requests sent to uncore.
675 .It Li OFFCORE_REQUESTS.DEMAND_RFO
676 .Pq Event B0H , Umask 04H
677 Demand RFO read requests sent to uncore, including
678 regular RFOs, locks, ItoM.
679 .It Li OFFCORE_REQUESTS.ALL_DATA_RD
680 .Pq Event B0H , Umask 08H
681 Data read requests sent to uncore (demand and
683 .It Li UOPS_EXECUTED.CORE
684 .Pq Event B1H , Umask 02H
685 Counts total number of uops to be executed per-core
687 .It Li OFF_CORE_RESPONSE_0
688 .Pq Event B7H , Umask 01H
690 .It Li OFF_CORE_RESPONSE_1
691 .Pq Event BBH , Umask 01H
693 .It Li PAGE_WALKER_LOADS.DTLB_L1
694 .Pq Event BCH , Umask 11H
695 Number of DTLB page walker loads that hit in the
697 .It Li PAGE_WALKER_LOADS.ITLB_L1
698 .Pq Event BCH , Umask 21H
699 Number of ITLB page walker loads that hit in the
701 .It Li PAGE_WALKER_LOADS.DTLB_L2
702 .Pq Event BCH , Umask 12H
703 Number of DTLB page walker loads that hit in the L2.
704 .It Li PAGE_WALKER_LOADS.ITLB_L2
705 .Pq Event BCH , Umask 22H
706 Number of ITLB page walker loads that hit in the L2.
707 .It Li PAGE_WALKER_LOADS.DTLB_L3
708 .Pq Event BCH , Umask 14H
709 Number of DTLB page walker loads that hit in the L3.
710 .It Li PAGE_WALKER_LOADS.ITLB_L3
711 .Pq Event BCH , Umask 24H
712 Number of ITLB page walker loads that hit in the L3.
713 .It Li PAGE_WALKER_LOADS.DTLB_MEMORY
714 .Pq Event BCH , Umask 18H
715 Number of DTLB page walker loads from memory.
716 .It Li PAGE_WALKER_LOADS.ITLB_MEMORY
717 .Pq Event BCH , Umask 28H
718 Number of ITLB page walker loads from memory.
719 .It Li TLB_FLUSH.DTLB_THREAD
720 .Pq Event BDH , Umask 01H
721 DTLB flush attempts of the thread-specific entries.
722 .It Li TLB_FLUSH.STLB_ANY
723 .Pq Event BDH , Umask 20H
724 Count number of STLB flush attempts.
725 .It Li INST_RETIRED.ANY_P
726 .Pq Event C0H , Umask 00H
727 Number of instructions at retirement.
728 .It Li INST_RETIRED.ALL
729 .Pq Event C0H , Umask 01H
730 Precise instruction retired event with HW to reduce
731 effect of PEBS shadow in IP distribution.
732 .It Li OTHER_ASSISTS.AVX_TO_SSE
733 .Pq Event C1H , Umask 08H
734 Number of transitions from AVX-256 to legacy SSE
735 when penalty applicable.
736 .It Li OTHER_ASSISTS.SSE_TO_AVX
737 .Pq Event C1H , Umask 10H
738 Number of transitions from SSE to AVX-256 when
740 .It Li OTHER_ASSISTS.ANY_WB_ASSIST
741 .Pq Event C1H , Umask 40H
742 Number of microcode assists invoked by HW upon
744 .It Li UOPS_RETIRED.ALL
745 .Pq Event C2H , Umask 01H
746 Counts the number of micro-ops retired, Use
747 cmask=1 and invert to count active cycles or stalled
749 .It Li UOPS_RETIRED.RETIRE_SLOTS
750 .Pq Event C2H , Umask 02H
751 Counts the number of retirement slots used each
753 .It Li MACHINE_CLEARS.MEMORY_ORDERING
754 .Pq Event C3H , Umask 02H
755 Counts the number of machine clears due to memory
757 .It Li MACHINE_CLEARS.SMC
758 .Pq Event C3H , Umask 04H
759 Number of self-modifying-code machine clears
761 .It Li MACHINE_CLEARS.MASKMOV
762 .Pq Event C3H , Umask 20H
763 Counts the number of executed AVX masked load
764 operations that refer to an illegal address range with
765 the mask bits set to 0.
766 .It Li BR_INST_RETIRED.ALL_BRANCHES
767 .Pq Event C4H , Umask 00H
768 Branch instructions at retirement.
769 .It Li BR_INST_RETIRED.CONDITIONAL
770 .Pq Event C4H , Umask 01H
771 Counts the number of conditional branch instructions Supports PEBS
773 .It Li BR_INST_RETIRED.NEAR_CALL
774 .Pq Event C4H , Umask 02H
775 Direct and indirect near call instructions retired.
776 .It Li BR_INST_RETIRED.ALL_BRANCHES
777 .Pq Event C4H , Umask 04H
778 Counts the number of branch instructions retired.
779 .It Li BR_INST_RETIRED.NEAR_RETURN
780 .Pq Event C4H , Umask 08H
781 Counts the number of near return instructions
783 .It Li BR_INST_RETIRED.NOT_TAKEN
784 .Pq Event C4H , Umask 10H
785 Counts the number of not taken branch instructions
787 It Li BR_INST_RETIRED.NEAR_TAKEN
788 .Pq Event C4H , Umask 20H
789 Number of near taken branches retired.
790 .It Li BR_INST_RETIRED.FAR_BRANCH
791 .Pq Event C4H , Umask 40H
792 Number of far branches retired.
793 .It Li BR_MISP_RETIRED.ALL_BRANCHES
794 .Pq Event C5H , Umask 00H
795 Mispredicted branch instructions at retirement
796 .It Li BR_MISP_RETIRED.CONDITIONAL
797 .Pq Event C5H , Umask 01H
798 Mispredicted conditional branch instructions retired.
799 .It Li BR_MISP_RETIRED.CONDITIONAL
800 .Pq Event C5H , Umask 04H
801 Mispredicted macro branch instructions retired.
802 .It Li FP_ASSIST.X87_OUTPUT
803 .Pq Event CAH , Umask 02H
804 Number of X87 FP assists due to Output values.
805 .It Li FP_ASSIST.X87_INPUT
806 .Pq Event CAH , Umask 04H
807 Number of X87 FP assists due to input values.
808 .It Li FP_ASSIST.SIMD_OUTPUT
809 .Pq Event CAH , Umask 08H
810 Number of SIMD FP assists due to Output values.
811 .It Li FP_ASSIST.SIMD_INPUT
812 .Pq Event CAH , Umask 10H
813 Number of SIMD FP assists due to input values.
815 .Pq Event CAH , Umask 1EH
816 Cycles with any input/output SSE* or FP assists.
817 .It Li ROB_MISC_EVENTS.LBR_INSERTS
818 .Pq Event CCH , Umask 20H
819 Count cases of saving new LBR records by hardware.
820 .It Li MEM_TRANS_RETIRED.LOAD_LATENCY
821 .Pq Event CDH , Umask 01H
822 Randomly sampled loads whose latency is above a
823 user defined threshold. A small fraction of the overall
824 loads are sampled due to randomization.
825 .It Li MEM_UOP_RETIRED.LOADS
826 .Pq Event D0H , Umask 01H
827 Qualify retired memory uops that are loads. Combine Supports PEBS and
828 with umask 10H, 20H, 40H, 80H.
829 .It Li MEM_UOP_RETIRED.STORES
830 .Pq Event D0H , Umask 02H
831 Qualify retired memory uops that are stores.
832 Combine with umask 10H, 20H, 40H, 80H.
833 .It Li MEM_UOP_RETIRED.STLB_MISS
834 .Pq Event D0H , Umask 10H
835 Qualify retired memory uops with STLB miss. Must
836 combine with umask 01H, 02H, to produce counts.
837 .It Li MEM_UOP_RETIRED.LOCK
838 .Pq Event D0H , Umask 20H
839 Qualify retired memory uops with lock. Must combine Supports PEBS and
840 with umask 01H, 02H, to produce counts.
841 .It Li MEM_UOP_RETIRED.SPLIT
842 .Pq Event D0H , Umask 40H
843 Qualify retired memory uops with line split. Must
844 combine with umask 01H, 02H, to produce counts.
845 .It Li MEM_UOP_RETIRED.ALL
846 .Pq Event D0H , Umask 80H
847 Qualify any retired memory uops. Must combine with Supports PEBS and
848 umask 01H, 02H, to produce counts.
849 .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
850 .Pq Event D1H , Umask 01H
851 Retired load uops with L1 cache hits as data sources.
852 .It Li MEM_LOAD_UOPS_RETIRED.L2_HIT
853 .Pq Event D1H , Umask 02H
854 Retired load uops with L2 cache hits as data sources.
855 .It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT
856 .Pq Event D1H , Umask 04H
857 Retired load uops with LLC cache hits as data
859 .It Li MEM_LOAD_UOPS_RETIRED.L2_MISS
860 .Pq Event D1H , Umask 10H
861 Retired load uops missed L2. Unknown data source
863 .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB
864 .Pq Event D1H , Umask 40H
865 Retired load uops which data sources were load uops
866 missed L1 but hit FB due to preceding miss to the
867 same cache line with data not ready.
868 .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS
869 .Pq Event D2H , Umask 01H
870 Retired load uops which data sources were LLC hit
871 and cross-core snoop missed in on-pkg core cache.
872 .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT
873 .Pq Event D2H , Umask 02H
874 Retired load uops which data sources were LLC and
875 cross-core snoop hits in on-pkg core cache.
876 .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM
877 .Pq Event D2H , Umask 04H
878 Retired load uops which data sources were HitM
879 responses from shared LLC.
880 .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE
881 .Pq Event D2H , Umask 08H
882 Retired load uops which data sources were hits in
883 LLC without snoops required.
884 .It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM
885 .Pq Event D3H , Umask 01H
886 Retired load uops which data sources missed LLC but
887 serviced from local dram.
889 .Pq Event E6H , Umask 1FH
890 Number of front end re-steers due to BPU
892 .It Li L2_TRANS.DEMAND_DATA_RD
893 .Pq Event F0H , Umask 01H
894 Demand Data Read requests that access L2 cache.
896 .Pq Event F0H , Umask 02H
897 RFO requests that access L2 cache.
898 .It Li L2_TRANS.CODE_RD
899 .Pq Event F0H , Umask 04H
900 L2 cache accesses when fetching instructions.
901 .It Li L2_TRANS.ALL_PF
902 .Pq Event F0H , Umask 08H
903 Any MLC or LLC HW prefetch accessing L2, including
905 .It Li L2_TRANS.L1D_WB
906 .Pq Event F0H , Umask 10H
907 L1D writebacks that access L2 cache.
908 .It Li L2_TRANS.L2_FILL
909 .Pq Event F0H , Umask 20H
910 L2 fill requests that access L2 cache.
911 .It Li L2_TRANS.L2_WB
912 .Pq Event F0H , Umask 40H
913 L2 writebacks that access L2 cache.
914 .It Li L2_TRANS.ALL_REQUESTS
915 .Pq Event F0H , Umask 80H
916 Transactions accessing L2 pipe.
918 .Pq Event F1H , Umask 01H
919 L2 cache lines in I state filling L2.
921 .Pq Event F1H , Umask 02H
922 L2 cache lines in S state filling L2.
924 .Pq Event F1H , Umask 04H
925 L2 cache lines in E state filling L2.
926 .It Li L2_LINES_IN.ALL
927 .Pq Event F1H , Umask 07H
928 L2 cache lines filling L2.
929 .It Li L2_LINES_OUT.DEMAND_CLEAN
930 .Pq Event F2H , Umask 05H
931 Clean L2 cache lines evicted by demand.
932 .It Li L2_LINES_OUT.DEMAND_DIRTY
933 .Pq Event F2H , Umask 06H
934 Dirty L2 cache lines evicted by demand.
950 .Xr pmc.haswelluc 3 ,
951 .Xr pmc.ivybridge 3 ,
952 .Xr pmc.ivybridgexeon 3 ,
953 .Xr pmc.sandybridge 3 ,
954 .Xr pmc.sandybridgeuc 3 ,
955 .Xr pmc.sandybridgexeon 3 ,
957 .Xr pmc.westmereuc 3 ,
964 Support for the Haswell Xeon microarchitecture first appeared in
969 library was written by
971 .Aq jkoshy@FreeBSD.org .
972 The support for the Haswell Xeon
973 microarchitecture was written by
974 .An "Randall Stewart"
975 .Aq rrs@FreeBSD.org .