lib/libpmcstat/pmu-events/arch/arm64/arm/cortex-a53/other.json

   1 [
   2   {
   3         "ArchStdEvent": "EXC_IRQ",
   4   },
   5   {
   6         "ArchStdEvent": "EXC_FIQ",
   7   },
   8   {
   9         "EventCode": "0xC6",
  10         "EventName": "PRE_DECODE_ERR",
  11         "BriefDescription": "Pre-decode error"
  12   },
  13   {
  14         "EventCode": "0xD0",
  15         "EventName": "L1I_CACHE_ERR",
  16         "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
  17   },
  18   {
  19         "EventCode": "0xD1",
  20         "EventName": "L1D_CACHE_ERR",
  21         "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
  22   },
  23   {
  24         "EventCode": "0xD2",
  25         "EventName": "TLB_ERR",
  26         "BriefDescription": "TLB memory error"
  27   }
  28 ]