3 "ArchStdEvent": "L1D_CACHE_RD",
6 "ArchStdEvent": "L1D_CACHE_WR",
9 "ArchStdEvent": "L1D_CACHE_REFILL_RD",
12 "ArchStdEvent": "L1D_CACHE_REFILL_WR",
15 "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
18 "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
21 "ArchStdEvent": "L1D_CACHE_INVAL",
24 "ArchStdEvent": "L1D_TLB_REFILL_RD",
27 "ArchStdEvent": "L1D_TLB_REFILL_WR",
30 "ArchStdEvent": "L1D_TLB_RD",
33 "ArchStdEvent": "L1D_TLB_WR",
36 "ArchStdEvent": "L2D_CACHE_RD",
39 "ArchStdEvent": "L2D_CACHE_WR",
42 "ArchStdEvent": "L2D_CACHE_REFILL_RD",
45 "ArchStdEvent": "L2D_CACHE_REFILL_WR",
48 "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
51 "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
54 "ArchStdEvent": "L2D_CACHE_INVAL",
57 "PublicDescription": "Level 1 instruction cache prefetch access count",
58 "EventCode": "0x102e",
59 "EventName": "L1I_CACHE_PRF",
60 "BriefDescription": "L1I cache prefetch access count",
63 "PublicDescription": "Level 1 instruction cache miss due to prefetch access count",
64 "EventCode": "0x102f",
65 "EventName": "L1I_CACHE_PRF_REFILL",
66 "BriefDescription": "L1I cache miss due to prefetch access count",
69 "PublicDescription": "Instruction queue is empty",
70 "EventCode": "0x1043",
71 "EventName": "IQ_IS_EMPTY",
72 "BriefDescription": "Instruction queue is empty",
75 "PublicDescription": "Instruction fetch stall cycles",
76 "EventCode": "0x1044",
77 "EventName": "IF_IS_STALL",
78 "BriefDescription": "Instruction fetch stall cycles",
81 "PublicDescription": "Instructions can receive, but not send",
82 "EventCode": "0x2014",
83 "EventName": "FETCH_BUBBLE",
84 "BriefDescription": "Instructions can receive, but not send",
87 "PublicDescription": "Prefetch request from LSU",
88 "EventCode": "0x6013",
89 "EventName": "PRF_REQ",
90 "BriefDescription": "Prefetch request from LSU",
93 "PublicDescription": "Hit on prefetched data",
94 "EventCode": "0x6014",
95 "EventName": "HIT_ON_PRF",
96 "BriefDescription": "Hit on prefetched data",
99 "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4",
100 "EventCode": "0x7001",
101 "EventName": "EXE_STALL_CYCLE",
102 "BriefDescription": "Cycles of that the number of issue ups are less than 4",
105 "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
106 "EventCode": "0x7004",
107 "EventName": "MEM_STALL_ANYLOAD",
108 "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
111 "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
112 "EventCode": "0x7006",
113 "EventName": "MEM_STALL_L1MISS",
114 "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
117 "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
118 "EventCode": "0x7007",
119 "EventName": "MEM_STALL_L2MISS",
120 "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",