lib/libpmcstat/pmu-events/arch/x86/nehalemep/cache.json

   1 [
   2     {
   3         "EventCode": "0x63",
   4         "Counter": "0,1",
   5         "UMask": "0x2",
   6         "EventName": "CACHE_LOCK_CYCLES.L1D",
   7         "SampleAfterValue": "2000000",
   8         "BriefDescription": "Cycles L1D locked"
   9     },
  10     {
  11         "EventCode": "0x63",
  12         "Counter": "0,1",
  13         "UMask": "0x1",
  14         "EventName": "CACHE_LOCK_CYCLES.L1D_L2",
  15         "SampleAfterValue": "2000000",
  16         "BriefDescription": "Cycles L1D and L2 locked"
  17     },
  18     {
  19         "EventCode": "0x51",
  20         "Counter": "0,1",
  21         "UMask": "0x4",
  22         "EventName": "L1D.M_EVICT",
  23         "SampleAfterValue": "2000000",
  24         "BriefDescription": "L1D cache lines replaced in M state"
  25     },
  26     {
  27         "EventCode": "0x51",
  28         "Counter": "0,1",
  29         "UMask": "0x2",
  30         "EventName": "L1D.M_REPL",
  31         "SampleAfterValue": "2000000",
  32         "BriefDescription": "L1D cache lines allocated in the M state"
  33     },
  34     {
  35         "EventCode": "0x51",
  36         "Counter": "0,1",
  37         "UMask": "0x8",
  38         "EventName": "L1D.M_SNOOP_EVICT",
  39         "SampleAfterValue": "2000000",
  40         "BriefDescription": "L1D snoop eviction of cache lines in M state"
  41     },
  42     {
  43         "EventCode": "0x51",
  44         "Counter": "0,1",
  45         "UMask": "0x1",
  46         "EventName": "L1D.REPL",
  47         "SampleAfterValue": "2000000",
  48         "BriefDescription": "L1 data cache lines allocated"
  49     },
  50     {
  51         "EventCode": "0x43",
  52         "Counter": "0,1",
  53         "UMask": "0x1",
  54         "EventName": "L1D_ALL_REF.ANY",
  55         "SampleAfterValue": "2000000",
  56         "BriefDescription": "All references to the L1 data cache"
  57     },
  58     {
  59         "EventCode": "0x43",
  60         "Counter": "0,1",
  61         "UMask": "0x2",
  62         "EventName": "L1D_ALL_REF.CACHEABLE",
  63         "SampleAfterValue": "2000000",
  64         "BriefDescription": "L1 data cacheable reads and writes"
  65     },
  66     {
  67         "EventCode": "0x40",
  68         "Counter": "0,1",
  69         "UMask": "0x4",
  70         "EventName": "L1D_CACHE_LD.E_STATE",
  71         "SampleAfterValue": "2000000",
  72         "BriefDescription": "L1 data cache read in E state"
  73     },
  74     {
  75         "EventCode": "0x40",
  76         "Counter": "0,1",
  77         "UMask": "0x1",
  78         "EventName": "L1D_CACHE_LD.I_STATE",
  79         "SampleAfterValue": "2000000",
  80         "BriefDescription": "L1 data cache read in I state (misses)"
  81     },
  82     {
  83         "EventCode": "0x40",
  84         "Counter": "0,1",
  85         "UMask": "0x8",
  86         "EventName": "L1D_CACHE_LD.M_STATE",
  87         "SampleAfterValue": "2000000",
  88         "BriefDescription": "L1 data cache read in M state"
  89     },
  90     {
  91         "EventCode": "0x40",
  92         "Counter": "0,1",
  93         "UMask": "0xf",
  94         "EventName": "L1D_CACHE_LD.MESI",
  95         "SampleAfterValue": "2000000",
  96         "BriefDescription": "L1 data cache reads"
  97     },
  98     {
  99         "EventCode": "0x40",
 100         "Counter": "0,1",
 101         "UMask": "0x2",
 102         "EventName": "L1D_CACHE_LD.S_STATE",
 103         "SampleAfterValue": "2000000",
 104         "BriefDescription": "L1 data cache read in S state"
 105     },
 106     {
 107         "EventCode": "0x42",
 108         "Counter": "0,1",
 109         "UMask": "0x4",
 110         "EventName": "L1D_CACHE_LOCK.E_STATE",
 111         "SampleAfterValue": "2000000",
 112         "BriefDescription": "L1 data cache load locks in E state"
 113     },
 114     {
 115         "EventCode": "0x42",
 116         "Counter": "0,1",
 117         "UMask": "0x1",
 118         "EventName": "L1D_CACHE_LOCK.HIT",
 119         "SampleAfterValue": "2000000",
 120         "BriefDescription": "L1 data cache load lock hits"
 121     },
 122     {
 123         "EventCode": "0x42",
 124         "Counter": "0,1",
 125         "UMask": "0x8",
 126         "EventName": "L1D_CACHE_LOCK.M_STATE",
 127         "SampleAfterValue": "2000000",
 128         "BriefDescription": "L1 data cache load locks in M state"
 129     },
 130     {
 131         "EventCode": "0x42",
 132         "Counter": "0,1",
 133         "UMask": "0x2",
 134         "EventName": "L1D_CACHE_LOCK.S_STATE",
 135         "SampleAfterValue": "2000000",
 136         "BriefDescription": "L1 data cache load locks in S state"
 137     },
 138     {
 139         "EventCode": "0x53",
 140         "Counter": "0,1",
 141         "UMask": "0x1",
 142         "EventName": "L1D_CACHE_LOCK_FB_HIT",
 143         "SampleAfterValue": "2000000",
 144         "BriefDescription": "L1D load lock accepted in fill buffer"
 145     },
 146     {
 147         "EventCode": "0x52",
 148         "Counter": "0,1",
 149         "UMask": "0x1",
 150         "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
 151         "SampleAfterValue": "2000000",
 152         "BriefDescription": "L1D prefetch load lock accepted in fill buffer"
 153     },
 154     {
 155         "EventCode": "0x41",
 156         "Counter": "0,1",
 157         "UMask": "0x4",
 158         "EventName": "L1D_CACHE_ST.E_STATE",
 159         "SampleAfterValue": "2000000",
 160         "BriefDescription": "L1 data cache stores in E state"
 161     },
 162     {
 163         "EventCode": "0x41",
 164         "Counter": "0,1",
 165         "UMask": "0x8",
 166         "EventName": "L1D_CACHE_ST.M_STATE",
 167         "SampleAfterValue": "2000000",
 168         "BriefDescription": "L1 data cache stores in M state"
 169     },
 170     {
 171         "EventCode": "0x41",
 172         "Counter": "0,1",
 173         "UMask": "0x2",
 174         "EventName": "L1D_CACHE_ST.S_STATE",
 175         "SampleAfterValue": "2000000",
 176         "BriefDescription": "L1 data cache stores in S state"
 177     },
 178     {
 179         "EventCode": "0x4E",
 180         "Counter": "0,1",
 181         "UMask": "0x2",
 182         "EventName": "L1D_PREFETCH.MISS",
 183         "SampleAfterValue": "200000",
 184         "BriefDescription": "L1D hardware prefetch misses"
 185     },
 186     {
 187         "EventCode": "0x4E",
 188         "Counter": "0,1",
 189         "UMask": "0x1",
 190         "EventName": "L1D_PREFETCH.REQUESTS",
 191         "SampleAfterValue": "200000",
 192         "BriefDescription": "L1D hardware prefetch requests"
 193     },
 194     {
 195         "EventCode": "0x4E",
 196         "Counter": "0,1",
 197         "UMask": "0x4",
 198         "EventName": "L1D_PREFETCH.TRIGGERS",
 199         "SampleAfterValue": "200000",
 200         "BriefDescription": "L1D hardware prefetch requests triggered"
 201     },
 202     {
 203         "EventCode": "0x28",
 204         "Counter": "0,1,2,3",
 205         "UMask": "0x4",
 206         "EventName": "L1D_WB_L2.E_STATE",
 207         "SampleAfterValue": "100000",
 208         "BriefDescription": "L1 writebacks to L2 in E state"
 209     },
 210     {
 211         "EventCode": "0x28",
 212         "Counter": "0,1,2,3",
 213         "UMask": "0x1",
 214         "EventName": "L1D_WB_L2.I_STATE",
 215         "SampleAfterValue": "100000",
 216         "BriefDescription": "L1 writebacks to L2 in I state (misses)"
 217     },
 218     {
 219         "EventCode": "0x28",
 220         "Counter": "0,1,2,3",
 221         "UMask": "0x8",
 222         "EventName": "L1D_WB_L2.M_STATE",
 223         "SampleAfterValue": "100000",
 224         "BriefDescription": "L1 writebacks to L2 in M state"
 225     },
 226     {
 227         "EventCode": "0x28",
 228         "Counter": "0,1,2,3",
 229         "UMask": "0xf",
 230         "EventName": "L1D_WB_L2.MESI",
 231         "SampleAfterValue": "100000",
 232         "BriefDescription": "All L1 writebacks to L2"
 233     },
 234     {
 235         "EventCode": "0x28",
 236         "Counter": "0,1,2,3",
 237         "UMask": "0x2",
 238         "EventName": "L1D_WB_L2.S_STATE",
 239         "SampleAfterValue": "100000",
 240         "BriefDescription": "L1 writebacks to L2 in S state"
 241     },
 242     {
 243         "EventCode": "0x26",
 244         "Counter": "0,1,2,3",
 245         "UMask": "0xff",
 246         "EventName": "L2_DATA_RQSTS.ANY",
 247         "SampleAfterValue": "200000",
 248         "BriefDescription": "All L2 data requests"
 249     },
 250     {
 251         "EventCode": "0x26",
 252         "Counter": "0,1,2,3",
 253         "UMask": "0x4",
 254         "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
 255         "SampleAfterValue": "200000",
 256         "BriefDescription": "L2 data demand loads in E state"
 257     },
 258     {
 259         "EventCode": "0x26",
 260         "Counter": "0,1,2,3",
 261         "UMask": "0x1",
 262         "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
 263         "SampleAfterValue": "200000",
 264         "BriefDescription": "L2 data demand loads in I state (misses)"
 265     },
 266     {
 267         "EventCode": "0x26",
 268         "Counter": "0,1,2,3",
 269         "UMask": "0x8",
 270         "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
 271         "SampleAfterValue": "200000",
 272         "BriefDescription": "L2 data demand loads in M state"
 273     },
 274     {
 275         "EventCode": "0x26",
 276         "Counter": "0,1,2,3",
 277         "UMask": "0xf",
 278         "EventName": "L2_DATA_RQSTS.DEMAND.MESI",
 279         "SampleAfterValue": "200000",
 280         "BriefDescription": "L2 data demand requests"
 281     },
 282     {
 283         "EventCode": "0x26",
 284         "Counter": "0,1,2,3",
 285         "UMask": "0x2",
 286         "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
 287         "SampleAfterValue": "200000",
 288         "BriefDescription": "L2 data demand loads in S state"
 289     },
 290     {
 291         "EventCode": "0x26",
 292         "Counter": "0,1,2,3",
 293         "UMask": "0x40",
 294         "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
 295         "SampleAfterValue": "200000",
 296         "BriefDescription": "L2 data prefetches in E state"
 297     },
 298     {
 299         "EventCode": "0x26",
 300         "Counter": "0,1,2,3",
 301         "UMask": "0x10",
 302         "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
 303         "SampleAfterValue": "200000",
 304         "BriefDescription": "L2 data prefetches in the I state (misses)"
 305     },
 306     {
 307         "EventCode": "0x26",
 308         "Counter": "0,1,2,3",
 309         "UMask": "0x80",
 310         "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
 311         "SampleAfterValue": "200000",
 312         "BriefDescription": "L2 data prefetches in M state"
 313     },
 314     {
 315         "EventCode": "0x26",
 316         "Counter": "0,1,2,3",
 317         "UMask": "0xf0",
 318         "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
 319         "SampleAfterValue": "200000",
 320         "BriefDescription": "All L2 data prefetches"
 321     },
 322     {
 323         "EventCode": "0x26",
 324         "Counter": "0,1,2,3",
 325         "UMask": "0x20",
 326         "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
 327         "SampleAfterValue": "200000",
 328         "BriefDescription": "L2 data prefetches in the S state"
 329     },
 330     {
 331         "EventCode": "0xF1",
 332         "Counter": "0,1,2,3",
 333         "UMask": "0x7",
 334         "EventName": "L2_LINES_IN.ANY",
 335         "SampleAfterValue": "100000",
 336         "BriefDescription": "L2 lines alloacated"
 337     },
 338     {
 339         "EventCode": "0xF1",
 340         "Counter": "0,1,2,3",
 341         "UMask": "0x4",
 342         "EventName": "L2_LINES_IN.E_STATE",
 343         "SampleAfterValue": "100000",
 344         "BriefDescription": "L2 lines allocated in the E state"
 345     },
 346     {
 347         "EventCode": "0xF1",
 348         "Counter": "0,1,2,3",
 349         "UMask": "0x2",
 350         "EventName": "L2_LINES_IN.S_STATE",
 351         "SampleAfterValue": "100000",
 352         "BriefDescription": "L2 lines allocated in the S state"
 353     },
 354     {
 355         "EventCode": "0xF2",
 356         "Counter": "0,1,2,3",
 357         "UMask": "0xf",
 358         "EventName": "L2_LINES_OUT.ANY",
 359         "SampleAfterValue": "100000",
 360         "BriefDescription": "L2 lines evicted"
 361     },
 362     {
 363         "EventCode": "0xF2",
 364         "Counter": "0,1,2,3",
 365         "UMask": "0x1",
 366         "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
 367         "SampleAfterValue": "100000",
 368         "BriefDescription": "L2 lines evicted by a demand request"
 369     },
 370     {
 371         "EventCode": "0xF2",
 372         "Counter": "0,1,2,3",
 373         "UMask": "0x2",
 374         "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
 375         "SampleAfterValue": "100000",
 376         "BriefDescription": "L2 modified lines evicted by a demand request"
 377     },
 378     {
 379         "EventCode": "0xF2",
 380         "Counter": "0,1,2,3",
 381         "UMask": "0x4",
 382         "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
 383         "SampleAfterValue": "100000",
 384         "BriefDescription": "L2 lines evicted by a prefetch request"
 385     },
 386     {
 387         "EventCode": "0xF2",
 388         "Counter": "0,1,2,3",
 389         "UMask": "0x8",
 390         "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
 391         "SampleAfterValue": "100000",
 392         "BriefDescription": "L2 modified lines evicted by a prefetch request"
 393     },
 394     {
 395         "EventCode": "0x24",
 396         "Counter": "0,1,2,3",
 397         "UMask": "0x10",
 398         "EventName": "L2_RQSTS.IFETCH_HIT",
 399         "SampleAfterValue": "200000",
 400         "BriefDescription": "L2 instruction fetch hits"
 401     },
 402     {
 403         "EventCode": "0x24",
 404         "Counter": "0,1,2,3",
 405         "UMask": "0x20",
 406         "EventName": "L2_RQSTS.IFETCH_MISS",
 407         "SampleAfterValue": "200000",
 408         "BriefDescription": "L2 instruction fetch misses"
 409     },
 410     {
 411         "EventCode": "0x24",
 412         "Counter": "0,1,2,3",
 413         "UMask": "0x30",
 414         "EventName": "L2_RQSTS.IFETCHES",
 415         "SampleAfterValue": "200000",
 416         "BriefDescription": "L2 instruction fetches"
 417     },
 418     {
 419         "EventCode": "0x24",
 420         "Counter": "0,1,2,3",
 421         "UMask": "0x1",
 422         "EventName": "L2_RQSTS.LD_HIT",
 423         "SampleAfterValue": "200000",
 424         "BriefDescription": "L2 load hits"
 425     },
 426     {
 427         "EventCode": "0x24",
 428         "Counter": "0,1,2,3",
 429         "UMask": "0x2",
 430         "EventName": "L2_RQSTS.LD_MISS",
 431         "SampleAfterValue": "200000",
 432         "BriefDescription": "L2 load misses"
 433     },
 434     {
 435         "EventCode": "0x24",
 436         "Counter": "0,1,2,3",
 437         "UMask": "0x3",
 438         "EventName": "L2_RQSTS.LOADS",
 439         "SampleAfterValue": "200000",
 440         "BriefDescription": "L2 requests"
 441     },
 442     {
 443         "EventCode": "0x24",
 444         "Counter": "0,1,2,3",
 445         "UMask": "0xaa",
 446         "EventName": "L2_RQSTS.MISS",
 447         "SampleAfterValue": "200000",
 448         "BriefDescription": "All L2 misses"
 449     },
 450     {
 451         "EventCode": "0x24",
 452         "Counter": "0,1,2,3",
 453         "UMask": "0x40",
 454         "EventName": "L2_RQSTS.PREFETCH_HIT",
 455         "SampleAfterValue": "200000",
 456         "BriefDescription": "L2 prefetch hits"
 457     },
 458     {
 459         "EventCode": "0x24",
 460         "Counter": "0,1,2,3",
 461         "UMask": "0x80",
 462         "EventName": "L2_RQSTS.PREFETCH_MISS",
 463         "SampleAfterValue": "200000",
 464         "BriefDescription": "L2 prefetch misses"
 465     },
 466     {
 467         "EventCode": "0x24",
 468         "Counter": "0,1,2,3",
 469         "UMask": "0xc0",
 470         "EventName": "L2_RQSTS.PREFETCHES",
 471         "SampleAfterValue": "200000",
 472         "BriefDescription": "All L2 prefetches"
 473     },
 474     {
 475         "EventCode": "0x24",
 476         "Counter": "0,1,2,3",
 477         "UMask": "0xff",
 478         "EventName": "L2_RQSTS.REFERENCES",
 479         "SampleAfterValue": "200000",
 480         "BriefDescription": "All L2 requests"
 481     },
 482     {
 483         "EventCode": "0x24",
 484         "Counter": "0,1,2,3",
 485         "UMask": "0x4",
 486         "EventName": "L2_RQSTS.RFO_HIT",
 487         "SampleAfterValue": "200000",
 488         "BriefDescription": "L2 RFO hits"
 489     },
 490     {
 491         "EventCode": "0x24",
 492         "Counter": "0,1,2,3",
 493         "UMask": "0x8",
 494         "EventName": "L2_RQSTS.RFO_MISS",
 495         "SampleAfterValue": "200000",
 496         "BriefDescription": "L2 RFO misses"
 497     },
 498     {
 499         "EventCode": "0x24",
 500         "Counter": "0,1,2,3",
 501         "UMask": "0xc",
 502         "EventName": "L2_RQSTS.RFOS",
 503         "SampleAfterValue": "200000",
 504         "BriefDescription": "L2 RFO requests"
 505     },
 506     {
 507         "EventCode": "0xF0",
 508         "Counter": "0,1,2,3",
 509         "UMask": "0x80",
 510         "EventName": "L2_TRANSACTIONS.ANY",
 511         "SampleAfterValue": "200000",
 512         "BriefDescription": "All L2 transactions"
 513     },
 514     {
 515         "EventCode": "0xF0",
 516         "Counter": "0,1,2,3",
 517         "UMask": "0x20",
 518         "EventName": "L2_TRANSACTIONS.FILL",
 519         "SampleAfterValue": "200000",
 520         "BriefDescription": "L2 fill transactions"
 521     },
 522     {
 523         "EventCode": "0xF0",
 524         "Counter": "0,1,2,3",
 525         "UMask": "0x4",
 526         "EventName": "L2_TRANSACTIONS.IFETCH",
 527         "SampleAfterValue": "200000",
 528         "BriefDescription": "L2 instruction fetch transactions"
 529     },
 530     {
 531         "EventCode": "0xF0",
 532         "Counter": "0,1,2,3",
 533         "UMask": "0x10",
 534         "EventName": "L2_TRANSACTIONS.L1D_WB",
 535         "SampleAfterValue": "200000",
 536         "BriefDescription": "L1D writeback to L2 transactions"
 537     },
 538     {
 539         "EventCode": "0xF0",
 540         "Counter": "0,1,2,3",
 541         "UMask": "0x1",
 542         "EventName": "L2_TRANSACTIONS.LOAD",
 543         "SampleAfterValue": "200000",
 544         "BriefDescription": "L2 Load transactions"
 545     },
 546     {
 547         "EventCode": "0xF0",
 548         "Counter": "0,1,2,3",
 549         "UMask": "0x8",
 550         "EventName": "L2_TRANSACTIONS.PREFETCH",
 551         "SampleAfterValue": "200000",
 552         "BriefDescription": "L2 prefetch transactions"
 553     },
 554     {
 555         "EventCode": "0xF0",
 556         "Counter": "0,1,2,3",
 557         "UMask": "0x2",
 558         "EventName": "L2_TRANSACTIONS.RFO",
 559         "SampleAfterValue": "200000",
 560         "BriefDescription": "L2 RFO transactions"
 561     },
 562     {
 563         "EventCode": "0xF0",
 564         "Counter": "0,1,2,3",
 565         "UMask": "0x40",
 566         "EventName": "L2_TRANSACTIONS.WB",
 567         "SampleAfterValue": "200000",
 568         "BriefDescription": "L2 writeback to LLC transactions"
 569     },
 570     {
 571         "EventCode": "0x27",
 572         "Counter": "0,1,2,3",
 573         "UMask": "0x40",
 574         "EventName": "L2_WRITE.LOCK.E_STATE",
 575         "SampleAfterValue": "100000",
 576         "BriefDescription": "L2 demand lock RFOs in E state"
 577     },
 578     {
 579         "EventCode": "0x27",
 580         "Counter": "0,1,2,3",
 581         "UMask": "0xe0",
 582         "EventName": "L2_WRITE.LOCK.HIT",
 583         "SampleAfterValue": "100000",
 584         "BriefDescription": "All demand L2 lock RFOs that hit the cache"
 585     },
 586     {
 587         "EventCode": "0x27",
 588         "Counter": "0,1,2,3",
 589         "UMask": "0x10",
 590         "EventName": "L2_WRITE.LOCK.I_STATE",
 591         "SampleAfterValue": "100000",
 592         "BriefDescription": "L2 demand lock RFOs in I state (misses)"
 593     },
 594     {
 595         "EventCode": "0x27",
 596         "Counter": "0,1,2,3",
 597         "UMask": "0x80",
 598         "EventName": "L2_WRITE.LOCK.M_STATE",
 599         "SampleAfterValue": "100000",
 600         "BriefDescription": "L2 demand lock RFOs in M state"
 601     },
 602     {
 603         "EventCode": "0x27",
 604         "Counter": "0,1,2,3",
 605         "UMask": "0xf0",
 606         "EventName": "L2_WRITE.LOCK.MESI",
 607         "SampleAfterValue": "100000",
 608         "BriefDescription": "All demand L2 lock RFOs"
 609     },
 610     {
 611         "EventCode": "0x27",
 612         "Counter": "0,1,2,3",
 613         "UMask": "0x20",
 614         "EventName": "L2_WRITE.LOCK.S_STATE",
 615         "SampleAfterValue": "100000",
 616         "BriefDescription": "L2 demand lock RFOs in S state"
 617     },
 618     {
 619         "EventCode": "0x27",
 620         "Counter": "0,1,2,3",
 621         "UMask": "0xe",
 622         "EventName": "L2_WRITE.RFO.HIT",
 623         "SampleAfterValue": "100000",
 624         "BriefDescription": "All L2 demand store RFOs that hit the cache"
 625     },
 626     {
 627         "EventCode": "0x27",
 628         "Counter": "0,1,2,3",
 629         "UMask": "0x1",
 630         "EventName": "L2_WRITE.RFO.I_STATE",
 631         "SampleAfterValue": "100000",
 632         "BriefDescription": "L2 demand store RFOs in I state (misses)"
 633     },
 634     {
 635         "EventCode": "0x27",
 636         "Counter": "0,1,2,3",
 637         "UMask": "0x8",
 638         "EventName": "L2_WRITE.RFO.M_STATE",
 639         "SampleAfterValue": "100000",
 640         "BriefDescription": "L2 demand store RFOs in M state"
 641     },
 642     {
 643         "EventCode": "0x27",
 644         "Counter": "0,1,2,3",
 645         "UMask": "0xf",
 646         "EventName": "L2_WRITE.RFO.MESI",
 647         "SampleAfterValue": "100000",
 648         "BriefDescription": "All L2 demand store RFOs"
 649     },
 650     {
 651         "EventCode": "0x27",
 652         "Counter": "0,1,2,3",
 653         "UMask": "0x2",
 654         "EventName": "L2_WRITE.RFO.S_STATE",
 655         "SampleAfterValue": "100000",
 656         "BriefDescription": "L2 demand store RFOs in S state"
 657     },
 658     {
 659         "EventCode": "0x2E",
 660         "Counter": "0,1,2,3",
 661         "UMask": "0x41",
 662         "EventName": "LONGEST_LAT_CACHE.MISS",
 663         "SampleAfterValue": "100000",
 664         "BriefDescription": "Longest latency cache miss"
 665     },
 666     {
 667         "EventCode": "0x2E",
 668         "Counter": "0,1,2,3",
 669         "UMask": "0x4f",
 670         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
 671         "SampleAfterValue": "200000",
 672         "BriefDescription": "Longest latency cache reference"
 673     },
 674     {
 675         "PEBS": "1",
 676         "EventCode": "0xB",
 677         "Counter": "0,1,2,3",
 678         "UMask": "0x1",
 679         "EventName": "MEM_INST_RETIRED.LOADS",
 680         "SampleAfterValue": "2000000",
 681         "BriefDescription": "Instructions retired which contains a load (Precise Event)"
 682     },
 683     {
 684         "PEBS": "1",
 685         "EventCode": "0xB",
 686         "Counter": "0,1,2,3",
 687         "UMask": "0x2",
 688         "EventName": "MEM_INST_RETIRED.STORES",
 689         "SampleAfterValue": "2000000",
 690         "BriefDescription": "Instructions retired which contains a store (Precise Event)"
 691     },
 692     {
 693         "PEBS": "1",
 694         "EventCode": "0xCB",
 695         "Counter": "0,1,2,3",
 696         "UMask": "0x40",
 697         "EventName": "MEM_LOAD_RETIRED.HIT_LFB",
 698         "SampleAfterValue": "200000",
 699         "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)"
 700     },
 701     {
 702         "PEBS": "1",
 703         "EventCode": "0xCB",
 704         "Counter": "0,1,2,3",
 705         "UMask": "0x1",
 706         "EventName": "MEM_LOAD_RETIRED.L1D_HIT",
 707         "SampleAfterValue": "2000000",
 708         "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)"
 709     },
 710     {
 711         "PEBS": "1",
 712         "EventCode": "0xCB",
 713         "Counter": "0,1,2,3",
 714         "UMask": "0x2",
 715         "EventName": "MEM_LOAD_RETIRED.L2_HIT",
 716         "SampleAfterValue": "200000",
 717         "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)"
 718     },
 719     {
 720         "PEBS": "1",
 721         "EventCode": "0xCB",
 722         "Counter": "0,1,2,3",
 723         "UMask": "0x10",
 724         "EventName": "MEM_LOAD_RETIRED.LLC_MISS",
 725         "SampleAfterValue": "10000",
 726         "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)"
 727     },
 728     {
 729         "PEBS": "1",
 730         "EventCode": "0xCB",
 731         "Counter": "0,1,2,3",
 732         "UMask": "0x4",
 733         "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
 734         "SampleAfterValue": "40000",
 735         "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)"
 736     },
 737     {
 738         "PEBS": "1",
 739         "EventCode": "0xCB",
 740         "Counter": "0,1,2,3",
 741         "UMask": "0x8",
 742         "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
 743         "SampleAfterValue": "40000",
 744         "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)"
 745     },
 746     {
 747         "PEBS": "1",
 748         "EventCode": "0xF",
 749         "Counter": "0,1,2,3",
 750         "UMask": "0x20",
 751         "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM",
 752         "SampleAfterValue": "10000",
 753         "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)"
 754     },
 755     {
 756         "PEBS": "1",
 757         "EventCode": "0xF",
 758         "Counter": "0,1,2,3",
 759         "UMask": "0x2",
 760         "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM",
 761         "SampleAfterValue": "40000",
 762         "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)"
 763     },
 764     {
 765         "PEBS": "1",
 766         "EventCode": "0xF",
 767         "Counter": "0,1,2,3",
 768         "UMask": "0x8",
 769         "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT",
 770         "SampleAfterValue": "20000",
 771         "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)"
 772     },
 773     {
 774         "PEBS": "1",
 775         "EventCode": "0xF",
 776         "Counter": "0,1,2,3",
 777         "UMask": "0x10",
 778         "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",
 779         "SampleAfterValue": "10000",
 780         "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)"
 781     },
 782     {
 783         "PEBS": "1",
 784         "EventCode": "0xF",
 785         "Counter": "0,1,2,3",
 786         "UMask": "0x80",
 787         "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",
 788         "SampleAfterValue": "4000",
 789         "BriefDescription": "Load instructions retired IO (Precise Event)"
 790     },
 791     {
 792         "EventCode": "0xB0",
 793         "Counter": "0,1,2,3",
 794         "UMask": "0x40",
 795         "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
 796         "SampleAfterValue": "100000",
 797         "BriefDescription": "Offcore L1 data cache writebacks"
 798     },
 799     {
 800         "EventCode": "0xB2",
 801         "Counter": "0,1,2,3",
 802         "UMask": "0x1",
 803         "EventName": "OFFCORE_REQUESTS_SQ_FULL",
 804         "SampleAfterValue": "100000",
 805         "BriefDescription": "Offcore requests blocked due to Super Queue full"
 806     },
 807     {
 808         "EventCode": "0xF4",
 809         "Counter": "0,1,2,3",
 810         "UMask": "0x10",
 811         "EventName": "SQ_MISC.SPLIT_LOCK",
 812         "SampleAfterValue": "2000000",
 813         "BriefDescription": "Super Queue lock splits across a cache line"
 814     },
 815     {
 816         "EventCode": "0x6",
 817         "Counter": "0,1,2,3",
 818         "UMask": "0x4",
 819         "EventName": "STORE_BLOCKS.AT_RET",
 820         "SampleAfterValue": "200000",
 821         "BriefDescription": "Loads delayed with at-Retirement block code"
 822     },
 823     {
 824         "EventCode": "0x6",
 825         "Counter": "0,1,2,3",
 826         "UMask": "0x8",
 827         "EventName": "STORE_BLOCKS.L1D_BLOCK",
 828         "SampleAfterValue": "200000",
 829         "BriefDescription": "Cacheable loads delayed with L1D block code"
 830     },
 831     {
 832         "PEBS": "2",
 833         "EventCode": "0xB",
 834         "MSRValue": "0x0",
 835         "Counter": "3",
 836         "UMask": "0x10",
 837         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
 838         "MSRIndex": "0x3F6",
 839         "SampleAfterValue": "2000000",
 840         "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)"
 841     },
 842     {
 843         "PEBS": "2",
 844         "EventCode": "0xB",
 845         "MSRValue": "0x400",
 846         "Counter": "3",
 847         "UMask": "0x10",
 848         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
 849         "MSRIndex": "0x3F6",
 850         "SampleAfterValue": "100",
 851         "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)"
 852     },
 853     {
 854         "PEBS": "2",
 855         "EventCode": "0xB",
 856         "MSRValue": "0x80",
 857         "Counter": "3",
 858         "UMask": "0x10",
 859         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
 860         "MSRIndex": "0x3F6",
 861         "SampleAfterValue": "1000",
 862         "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)"
 863     },
 864     {
 865         "PEBS": "2",
 866         "EventCode": "0xB",
 867         "MSRValue": "0x10",
 868         "Counter": "3",
 869         "UMask": "0x10",
 870         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
 871         "MSRIndex": "0x3F6",
 872         "SampleAfterValue": "10000",
 873         "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)"
 874     },
 875     {
 876         "PEBS": "2",
 877         "EventCode": "0xB",
 878         "MSRValue": "0x4000",
 879         "Counter": "3",
 880         "UMask": "0x10",
 881         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
 882         "MSRIndex": "0x3F6",
 883         "SampleAfterValue": "5",
 884         "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)"
 885     },
 886     {
 887         "PEBS": "2",
 888         "EventCode": "0xB",
 889         "MSRValue": "0x800",
 890         "Counter": "3",
 891         "UMask": "0x10",
 892         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
 893         "MSRIndex": "0x3F6",
 894         "SampleAfterValue": "50",
 895         "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)"
 896     },
 897     {
 898         "PEBS": "2",
 899         "EventCode": "0xB",
 900         "MSRValue": "0x100",
 901         "Counter": "3",
 902         "UMask": "0x10",
 903         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
 904         "MSRIndex": "0x3F6",
 905         "SampleAfterValue": "500",
 906         "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)"
 907     },
 908     {
 909         "PEBS": "2",
 910         "EventCode": "0xB",
 911         "MSRValue": "0x20",
 912         "Counter": "3",
 913         "UMask": "0x10",
 914         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
 915         "MSRIndex": "0x3F6",
 916         "SampleAfterValue": "5000",
 917         "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)"
 918     },
 919     {
 920         "PEBS": "2",
 921         "EventCode": "0xB",
 922         "MSRValue": "0x8000",
 923         "Counter": "3",
 924         "UMask": "0x10",
 925         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
 926         "MSRIndex": "0x3F6",
 927         "SampleAfterValue": "3",
 928         "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)"
 929     },
 930     {
 931         "PEBS": "2",
 932         "EventCode": "0xB",
 933         "MSRValue": "0x4",
 934         "Counter": "3",
 935         "UMask": "0x10",
 936         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
 937         "MSRIndex": "0x3F6",
 938         "SampleAfterValue": "50000",
 939         "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)"
 940     },
 941     {
 942         "PEBS": "2",
 943         "EventCode": "0xB",
 944         "MSRValue": "0x1000",
 945         "Counter": "3",
 946         "UMask": "0x10",
 947         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
 948         "MSRIndex": "0x3F6",
 949         "SampleAfterValue": "20",
 950         "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)"
 951     },
 952     {
 953         "PEBS": "2",
 954         "EventCode": "0xB",
 955         "MSRValue": "0x200",
 956         "Counter": "3",
 957         "UMask": "0x10",
 958         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
 959         "MSRIndex": "0x3F6",
 960         "SampleAfterValue": "200",
 961         "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)"
 962     },
 963     {
 964         "PEBS": "2",
 965         "EventCode": "0xB",
 966         "MSRValue": "0x40",
 967         "Counter": "3",
 968         "UMask": "0x10",
 969         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
 970         "MSRIndex": "0x3F6",
 971         "SampleAfterValue": "2000",
 972         "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)"
 973     },
 974     {
 975         "PEBS": "2",
 976         "EventCode": "0xB",
 977         "MSRValue": "0x8",
 978         "Counter": "3",
 979         "UMask": "0x10",
 980         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
 981         "MSRIndex": "0x3F6",
 982         "SampleAfterValue": "20000",
 983         "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)"
 984     },
 985     {
 986         "PEBS": "2",
 987         "EventCode": "0xB",
 988         "MSRValue": "0x2000",
 989         "Counter": "3",
 990         "UMask": "0x10",
 991         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
 992         "MSRIndex": "0x3F6",
 993         "SampleAfterValue": "10",
 994         "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)"
 995     },
 996     {
 997         "EventCode": "0xB7",
 998         "MSRValue": "0x7F11",
 999         "Counter": "2",
1000         "UMask": "0x1",
1001         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
1002         "MSRIndex": "0x1A6",
1003         "SampleAfterValue": "100000",
1004         "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
1005         "Offcore": "1"
1006     },
1007     {
1008         "EventCode": "0xB7",
1009         "MSRValue": "0xFF11",
1010         "Counter": "2",
1011         "UMask": "0x1",
1012         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
1013         "MSRIndex": "0x1A6",
1014         "SampleAfterValue": "100000",
1015         "BriefDescription": "All offcore data reads",
1016         "Offcore": "1"
1017     },
1018     {
1019         "EventCode": "0xB7",
1020         "MSRValue": "0x8011",
1021         "Counter": "2",
1022         "UMask": "0x1",
1023         "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
1024         "MSRIndex": "0x1A6",
1025         "SampleAfterValue": "100000",
1026         "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
1027         "Offcore": "1"
1028     },
1029     {
1030         "EventCode": "0xB7",
1031         "MSRValue": "0x111",
1032         "Counter": "2",
1033         "UMask": "0x1",
1034         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
1035         "MSRIndex": "0x1A6",
1036         "SampleAfterValue": "100000",
1037         "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
1038         "Offcore": "1"
1039     },
1040     {
1041         "EventCode": "0xB7",
1042         "MSRValue": "0x211",
1043         "Counter": "2",
1044         "UMask": "0x1",
1045         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
1046         "MSRIndex": "0x1A6",
1047         "SampleAfterValue": "100000",
1048         "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
1049         "Offcore": "1"
1050     },
1051     {
1052         "EventCode": "0xB7",
1053         "MSRValue": "0x411",
1054         "Counter": "2",
1055         "UMask": "0x1",
1056         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
1057         "MSRIndex": "0x1A6",
1058         "SampleAfterValue": "100000",
1059         "BriefDescription": "Offcore data reads satisfied by the LLC  and HITM in a sibling core",
1060         "Offcore": "1"
1061     },
1062     {
1063         "EventCode": "0xB7",
1064         "MSRValue": "0x711",
1065         "Counter": "2",
1066         "UMask": "0x1",
1067         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
1068         "MSRIndex": "0x1A6",
1069         "SampleAfterValue": "100000",
1070         "BriefDescription": "Offcore data reads satisfied by the LLC",
1071         "Offcore": "1"
1072     },
1073     {
1074         "EventCode": "0xB7",
1075         "MSRValue": "0x4711",
1076         "Counter": "2",
1077         "UMask": "0x1",
1078         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
1079         "MSRIndex": "0x1A6",
1080         "SampleAfterValue": "100000",
1081         "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
1082         "Offcore": "1"
1083     },
1084     {
1085         "EventCode": "0xB7",
1086         "MSRValue": "0x1811",
1087         "Counter": "2",
1088         "UMask": "0x1",
1089         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
1090         "MSRIndex": "0x1A6",
1091         "SampleAfterValue": "100000",
1092         "BriefDescription": "Offcore data reads satisfied by a remote cache",
1093         "Offcore": "1"
1094     },
1095     {
1096         "EventCode": "0xB7",
1097         "MSRValue": "0x3811",
1098         "Counter": "2",
1099         "UMask": "0x1",
1100         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
1101         "MSRIndex": "0x1A6",
1102         "SampleAfterValue": "100000",
1103         "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
1104         "Offcore": "1"
1105     },
1106     {
1107         "EventCode": "0xB7",
1108         "MSRValue": "0x1011",
1109         "Counter": "2",
1110         "UMask": "0x1",
1111         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
1112         "MSRIndex": "0x1A6",
1113         "SampleAfterValue": "100000",
1114         "BriefDescription": "Offcore data reads that HIT in a remote cache",
1115         "Offcore": "1"
1116     },
1117     {
1118         "EventCode": "0xB7",
1119         "MSRValue": "0x811",
1120         "Counter": "2",
1121         "UMask": "0x1",
1122         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
1123         "MSRIndex": "0x1A6",
1124         "SampleAfterValue": "100000",
1125         "BriefDescription": "Offcore data reads that HITM in a remote cache",
1126         "Offcore": "1"
1127     },
1128     {
1129         "EventCode": "0xB7",
1130         "MSRValue": "0x7F44",
1131         "Counter": "2",
1132         "UMask": "0x1",
1133         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
1134         "MSRIndex": "0x1A6",
1135         "SampleAfterValue": "100000",
1136         "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
1137         "Offcore": "1"
1138     },
1139     {
1140         "EventCode": "0xB7",
1141         "MSRValue": "0xFF44",
1142         "Counter": "2",
1143         "UMask": "0x1",
1144         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
1145         "MSRIndex": "0x1A6",
1146         "SampleAfterValue": "100000",
1147         "BriefDescription": "All offcore code reads",
1148         "Offcore": "1"
1149     },
1150     {
1151         "EventCode": "0xB7",
1152         "MSRValue": "0x8044",
1153         "Counter": "2",
1154         "UMask": "0x1",
1155         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
1156         "MSRIndex": "0x1A6",
1157         "SampleAfterValue": "100000",
1158         "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
1159         "Offcore": "1"
1160     },
1161     {
1162         "EventCode": "0xB7",
1163         "MSRValue": "0x144",
1164         "Counter": "2",
1165         "UMask": "0x1",
1166         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
1167         "MSRIndex": "0x1A6",
1168         "SampleAfterValue": "100000",
1169         "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
1170         "Offcore": "1"
1171     },
1172     {
1173         "EventCode": "0xB7",
1174         "MSRValue": "0x244",
1175         "Counter": "2",
1176         "UMask": "0x1",
1177         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1178         "MSRIndex": "0x1A6",
1179         "SampleAfterValue": "100000",
1180         "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
1181         "Offcore": "1"
1182     },
1183     {
1184         "EventCode": "0xB7",
1185         "MSRValue": "0x444",
1186         "Counter": "2",
1187         "UMask": "0x1",
1188         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1189         "MSRIndex": "0x1A6",
1190         "SampleAfterValue": "100000",
1191         "BriefDescription": "Offcore code reads satisfied by the LLC  and HITM in a sibling core",
1192         "Offcore": "1"
1193     },
1194     {
1195         "EventCode": "0xB7",
1196         "MSRValue": "0x744",
1197         "Counter": "2",
1198         "UMask": "0x1",
1199         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
1200         "MSRIndex": "0x1A6",
1201         "SampleAfterValue": "100000",
1202         "BriefDescription": "Offcore code reads satisfied by the LLC",
1203         "Offcore": "1"
1204     },
1205     {
1206         "EventCode": "0xB7",
1207         "MSRValue": "0x4744",
1208         "Counter": "2",
1209         "UMask": "0x1",
1210         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
1211         "MSRIndex": "0x1A6",
1212         "SampleAfterValue": "100000",
1213         "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
1214         "Offcore": "1"
1215     },
1216     {
1217         "EventCode": "0xB7",
1218         "MSRValue": "0x1844",
1219         "Counter": "2",
1220         "UMask": "0x1",
1221         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
1222         "MSRIndex": "0x1A6",
1223         "SampleAfterValue": "100000",
1224         "BriefDescription": "Offcore code reads satisfied by a remote cache",
1225         "Offcore": "1"
1226     },
1227     {
1228         "EventCode": "0xB7",
1229         "MSRValue": "0x3844",
1230         "Counter": "2",
1231         "UMask": "0x1",
1232         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
1233         "MSRIndex": "0x1A6",
1234         "SampleAfterValue": "100000",
1235         "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
1236         "Offcore": "1"
1237     },
1238     {
1239         "EventCode": "0xB7",
1240         "MSRValue": "0x1044",
1241         "Counter": "2",
1242         "UMask": "0x1",
1243         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
1244         "MSRIndex": "0x1A6",
1245         "SampleAfterValue": "100000",
1246         "BriefDescription": "Offcore code reads that HIT in a remote cache",
1247         "Offcore": "1"
1248     },
1249     {
1250         "EventCode": "0xB7",
1251         "MSRValue": "0x844",
1252         "Counter": "2",
1253         "UMask": "0x1",
1254         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
1255         "MSRIndex": "0x1A6",
1256         "SampleAfterValue": "100000",
1257         "BriefDescription": "Offcore code reads that HITM in a remote cache",
1258         "Offcore": "1"
1259     },
1260     {
1261         "EventCode": "0xB7",
1262         "MSRValue": "0x7FFF",
1263         "Counter": "2",
1264         "UMask": "0x1",
1265         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
1266         "MSRIndex": "0x1A6",
1267         "SampleAfterValue": "100000",
1268         "BriefDescription": "Offcore requests satisfied by any cache or DRAM",
1269         "Offcore": "1"
1270     },
1271     {
1272         "EventCode": "0xB7",
1273         "MSRValue": "0xFFFF",
1274         "Counter": "2",
1275         "UMask": "0x1",
1276         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
1277         "MSRIndex": "0x1A6",
1278         "SampleAfterValue": "100000",
1279         "BriefDescription": "All offcore requests",
1280         "Offcore": "1"
1281     },
1282     {
1283         "EventCode": "0xB7",
1284         "MSRValue": "0x80FF",
1285         "Counter": "2",
1286         "UMask": "0x1",
1287         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
1288         "MSRIndex": "0x1A6",
1289         "SampleAfterValue": "100000",
1290         "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
1291         "Offcore": "1"
1292     },
1293     {
1294         "EventCode": "0xB7",
1295         "MSRValue": "0x1FF",
1296         "Counter": "2",
1297         "UMask": "0x1",
1298         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
1299         "MSRIndex": "0x1A6",
1300         "SampleAfterValue": "100000",
1301         "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
1302         "Offcore": "1"
1303     },
1304     {
1305         "EventCode": "0xB7",
1306         "MSRValue": "0x2FF",
1307         "Counter": "2",
1308         "UMask": "0x1",
1309         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
1310         "MSRIndex": "0x1A6",
1311         "SampleAfterValue": "100000",
1312         "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
1313         "Offcore": "1"
1314     },
1315     {
1316         "EventCode": "0xB7",
1317         "MSRValue": "0x4FF",
1318         "Counter": "2",
1319         "UMask": "0x1",
1320         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
1321         "MSRIndex": "0x1A6",
1322         "SampleAfterValue": "100000",
1323         "BriefDescription": "Offcore requests satisfied by the LLC  and HITM in a sibling core",
1324         "Offcore": "1"
1325     },
1326     {
1327         "EventCode": "0xB7",
1328         "MSRValue": "0x7FF",
1329         "Counter": "2",
1330         "UMask": "0x1",
1331         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
1332         "MSRIndex": "0x1A6",
1333         "SampleAfterValue": "100000",
1334         "BriefDescription": "Offcore requests satisfied by the LLC",
1335         "Offcore": "1"
1336     },
1337     {
1338         "EventCode": "0xB7",
1339         "MSRValue": "0x47FF",
1340         "Counter": "2",
1341         "UMask": "0x1",
1342         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
1343         "MSRIndex": "0x1A6",
1344         "SampleAfterValue": "100000",
1345         "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
1346         "Offcore": "1"
1347     },
1348     {
1349         "EventCode": "0xB7",
1350         "MSRValue": "0x18FF",
1351         "Counter": "2",
1352         "UMask": "0x1",
1353         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
1354         "MSRIndex": "0x1A6",
1355         "SampleAfterValue": "100000",
1356         "BriefDescription": "Offcore requests satisfied by a remote cache",
1357         "Offcore": "1"
1358     },
1359     {
1360         "EventCode": "0xB7",
1361         "MSRValue": "0x38FF",
1362         "Counter": "2",
1363         "UMask": "0x1",
1364         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
1365         "MSRIndex": "0x1A6",
1366         "SampleAfterValue": "100000",
1367         "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
1368         "Offcore": "1"
1369     },
1370     {
1371         "EventCode": "0xB7",
1372         "MSRValue": "0x10FF",
1373         "Counter": "2",
1374         "UMask": "0x1",
1375         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
1376         "MSRIndex": "0x1A6",
1377         "SampleAfterValue": "100000",
1378         "BriefDescription": "Offcore requests that HIT in a remote cache",
1379         "Offcore": "1"
1380     },
1381     {
1382         "EventCode": "0xB7",
1383         "MSRValue": "0x8FF",
1384         "Counter": "2",
1385         "UMask": "0x1",
1386         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
1387         "MSRIndex": "0x1A6",
1388         "SampleAfterValue": "100000",
1389         "BriefDescription": "Offcore requests that HITM in a remote cache",
1390         "Offcore": "1"
1391     },
1392     {
1393         "EventCode": "0xB7",
1394         "MSRValue": "0x7F22",
1395         "Counter": "2",
1396         "UMask": "0x1",
1397         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
1398         "MSRIndex": "0x1A6",
1399         "SampleAfterValue": "100000",
1400         "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
1401         "Offcore": "1"
1402     },
1403     {
1404         "EventCode": "0xB7",
1405         "MSRValue": "0xFF22",
1406         "Counter": "2",
1407         "UMask": "0x1",
1408         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
1409         "MSRIndex": "0x1A6",
1410         "SampleAfterValue": "100000",
1411         "BriefDescription": "All offcore RFO requests",
1412         "Offcore": "1"
1413     },
1414     {
1415         "EventCode": "0xB7",
1416         "MSRValue": "0x8022",
1417         "Counter": "2",
1418         "UMask": "0x1",
1419         "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
1420         "MSRIndex": "0x1A6",
1421         "SampleAfterValue": "100000",
1422         "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
1423         "Offcore": "1"
1424     },
1425     {
1426         "EventCode": "0xB7",
1427         "MSRValue": "0x122",
1428         "Counter": "2",
1429         "UMask": "0x1",
1430         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
1431         "MSRIndex": "0x1A6",
1432         "SampleAfterValue": "100000",
1433         "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
1434         "Offcore": "1"
1435     },
1436     {
1437         "EventCode": "0xB7",
1438         "MSRValue": "0x222",
1439         "Counter": "2",
1440         "UMask": "0x1",
1441         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
1442         "MSRIndex": "0x1A6",
1443         "SampleAfterValue": "100000",
1444         "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
1445         "Offcore": "1"
1446     },
1447     {
1448         "EventCode": "0xB7",
1449         "MSRValue": "0x422",
1450         "Counter": "2",
1451         "UMask": "0x1",
1452         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
1453         "MSRIndex": "0x1A6",
1454         "SampleAfterValue": "100000",
1455         "BriefDescription": "Offcore RFO requests satisfied by the LLC  and HITM in a sibling core",
1456         "Offcore": "1"
1457     },
1458     {
1459         "EventCode": "0xB7",
1460         "MSRValue": "0x722",
1461         "Counter": "2",
1462         "UMask": "0x1",
1463         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
1464         "MSRIndex": "0x1A6",
1465         "SampleAfterValue": "100000",
1466         "BriefDescription": "Offcore RFO requests satisfied by the LLC",
1467         "Offcore": "1"
1468     },
1469     {
1470         "EventCode": "0xB7",
1471         "MSRValue": "0x4722",
1472         "Counter": "2",
1473         "UMask": "0x1",
1474         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
1475         "MSRIndex": "0x1A6",
1476         "SampleAfterValue": "100000",
1477         "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
1478         "Offcore": "1"
1479     },
1480     {
1481         "EventCode": "0xB7",
1482         "MSRValue": "0x1822",
1483         "Counter": "2",
1484         "UMask": "0x1",
1485         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
1486         "MSRIndex": "0x1A6",
1487         "SampleAfterValue": "100000",
1488         "BriefDescription": "Offcore RFO requests satisfied by a remote cache",
1489         "Offcore": "1"
1490     },
1491     {
1492         "EventCode": "0xB7",
1493         "MSRValue": "0x3822",
1494         "Counter": "2",
1495         "UMask": "0x1",
1496         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
1497         "MSRIndex": "0x1A6",
1498         "SampleAfterValue": "100000",
1499         "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
1500         "Offcore": "1"
1501     },
1502     {
1503         "EventCode": "0xB7",
1504         "MSRValue": "0x1022",
1505         "Counter": "2",
1506         "UMask": "0x1",
1507         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
1508         "MSRIndex": "0x1A6",
1509         "SampleAfterValue": "100000",
1510         "BriefDescription": "Offcore RFO requests that HIT in a remote cache",
1511         "Offcore": "1"
1512     },
1513     {
1514         "EventCode": "0xB7",
1515         "MSRValue": "0x822",
1516         "Counter": "2",
1517         "UMask": "0x1",
1518         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
1519         "MSRIndex": "0x1A6",
1520         "SampleAfterValue": "100000",
1521         "BriefDescription": "Offcore RFO requests that HITM in a remote cache",
1522         "Offcore": "1"
1523     },
1524     {
1525         "EventCode": "0xB7",
1526         "MSRValue": "0x7F08",
1527         "Counter": "2",
1528         "UMask": "0x1",
1529         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
1530         "MSRIndex": "0x1A6",
1531         "SampleAfterValue": "100000",
1532         "BriefDescription": "Offcore writebacks to any cache or DRAM.",
1533         "Offcore": "1"
1534     },
1535     {
1536         "EventCode": "0xB7",
1537         "MSRValue": "0xFF08",
1538         "Counter": "2",
1539         "UMask": "0x1",
1540         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
1541         "MSRIndex": "0x1A6",
1542         "SampleAfterValue": "100000",
1543         "BriefDescription": "All offcore writebacks",
1544         "Offcore": "1"
1545     },
1546     {
1547         "EventCode": "0xB7",
1548         "MSRValue": "0x8008",
1549         "Counter": "2",
1550         "UMask": "0x1",
1551         "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
1552         "MSRIndex": "0x1A6",
1553         "SampleAfterValue": "100000",
1554         "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
1555         "Offcore": "1"
1556     },
1557     {
1558         "EventCode": "0xB7",
1559         "MSRValue": "0x108",
1560         "Counter": "2",
1561         "UMask": "0x1",
1562         "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
1563         "MSRIndex": "0x1A6",
1564         "SampleAfterValue": "100000",
1565         "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
1566         "Offcore": "1"
1567     },
1568     {
1569         "EventCode": "0xB7",
1570         "MSRValue": "0x408",
1571         "Counter": "2",
1572         "UMask": "0x1",
1573         "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
1574         "MSRIndex": "0x1A6",
1575         "SampleAfterValue": "100000",
1576         "BriefDescription": "Offcore writebacks to the LLC  and HITM in a sibling core",
1577         "Offcore": "1"
1578     },
1579     {
1580         "EventCode": "0xB7",
1581         "MSRValue": "0x708",
1582         "Counter": "2",
1583         "UMask": "0x1",
1584         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
1585         "MSRIndex": "0x1A6",
1586         "SampleAfterValue": "100000",
1587         "BriefDescription": "Offcore writebacks to the LLC",
1588         "Offcore": "1"
1589     },
1590     {
1591         "EventCode": "0xB7",
1592         "MSRValue": "0x4708",
1593         "Counter": "2",
1594         "UMask": "0x1",
1595         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
1596         "MSRIndex": "0x1A6",
1597         "SampleAfterValue": "100000",
1598         "BriefDescription": "Offcore writebacks to the LLC or local DRAM",
1599         "Offcore": "1"
1600     },
1601     {
1602         "EventCode": "0xB7",
1603         "MSRValue": "0x1808",
1604         "Counter": "2",
1605         "UMask": "0x1",
1606         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
1607         "MSRIndex": "0x1A6",
1608         "SampleAfterValue": "100000",
1609         "BriefDescription": "Offcore writebacks to a remote cache",
1610         "Offcore": "1"
1611     },
1612     {
1613         "EventCode": "0xB7",
1614         "MSRValue": "0x3808",
1615         "Counter": "2",
1616         "UMask": "0x1",
1617         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
1618         "MSRIndex": "0x1A6",
1619         "SampleAfterValue": "100000",
1620         "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
1621         "Offcore": "1"
1622     },
1623     {
1624         "EventCode": "0xB7",
1625         "MSRValue": "0x1008",
1626         "Counter": "2",
1627         "UMask": "0x1",
1628         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
1629         "MSRIndex": "0x1A6",
1630         "SampleAfterValue": "100000",
1631         "BriefDescription": "Offcore writebacks that HIT in a remote cache",
1632         "Offcore": "1"
1633     },
1634     {
1635         "EventCode": "0xB7",
1636         "MSRValue": "0x808",
1637         "Counter": "2",
1638         "UMask": "0x1",
1639         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
1640         "MSRIndex": "0x1A6",
1641         "SampleAfterValue": "100000",
1642         "BriefDescription": "Offcore writebacks that HITM in a remote cache",
1643         "Offcore": "1"
1644     },
1645     {
1646         "EventCode": "0xB7",
1647         "MSRValue": "0x7F77",
1648         "Counter": "2",
1649         "UMask": "0x1",
1650         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
1651         "MSRIndex": "0x1A6",
1652         "SampleAfterValue": "100000",
1653         "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
1654         "Offcore": "1"
1655     },
1656     {
1657         "EventCode": "0xB7",
1658         "MSRValue": "0xFF77",
1659         "Counter": "2",
1660         "UMask": "0x1",
1661         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
1662         "MSRIndex": "0x1A6",
1663         "SampleAfterValue": "100000",
1664         "BriefDescription": "All offcore code or data read requests",
1665         "Offcore": "1"
1666     },
1667     {
1668         "EventCode": "0xB7",
1669         "MSRValue": "0x8077",
1670         "Counter": "2",
1671         "UMask": "0x1",
1672         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
1673         "MSRIndex": "0x1A6",
1674         "SampleAfterValue": "100000",
1675         "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
1676         "Offcore": "1"
1677     },
1678     {
1679         "EventCode": "0xB7",
1680         "MSRValue": "0x177",
1681         "Counter": "2",
1682         "UMask": "0x1",
1683         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
1684         "MSRIndex": "0x1A6",
1685         "SampleAfterValue": "100000",
1686         "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
1687         "Offcore": "1"
1688     },
1689     {
1690         "EventCode": "0xB7",
1691         "MSRValue": "0x277",
1692         "Counter": "2",
1693         "UMask": "0x1",
1694         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1695         "MSRIndex": "0x1A6",
1696         "SampleAfterValue": "100000",
1697         "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
1698         "Offcore": "1"
1699     },
1700     {
1701         "EventCode": "0xB7",
1702         "MSRValue": "0x477",
1703         "Counter": "2",
1704         "UMask": "0x1",
1705         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1706         "MSRIndex": "0x1A6",
1707         "SampleAfterValue": "100000",
1708         "BriefDescription": "Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core",
1709         "Offcore": "1"
1710     },
1711     {
1712         "EventCode": "0xB7",
1713         "MSRValue": "0x777",
1714         "Counter": "2",
1715         "UMask": "0x1",
1716         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
1717         "MSRIndex": "0x1A6",
1718         "SampleAfterValue": "100000",
1719         "BriefDescription": "Offcore code or data read requests satisfied by the LLC",
1720         "Offcore": "1"
1721     },
1722     {
1723         "EventCode": "0xB7",
1724         "MSRValue": "0x4777",
1725         "Counter": "2",
1726         "UMask": "0x1",
1727         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
1728         "MSRIndex": "0x1A6",
1729         "SampleAfterValue": "100000",
1730         "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
1731         "Offcore": "1"
1732     },
1733     {
1734         "EventCode": "0xB7",
1735         "MSRValue": "0x1877",
1736         "Counter": "2",
1737         "UMask": "0x1",
1738         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
1739         "MSRIndex": "0x1A6",
1740         "SampleAfterValue": "100000",
1741         "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
1742         "Offcore": "1"
1743     },
1744     {
1745         "EventCode": "0xB7",
1746         "MSRValue": "0x3877",
1747         "Counter": "2",
1748         "UMask": "0x1",
1749         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
1750         "MSRIndex": "0x1A6",
1751         "SampleAfterValue": "100000",
1752         "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
1753         "Offcore": "1"
1754     },
1755     {
1756         "EventCode": "0xB7",
1757         "MSRValue": "0x1077",
1758         "Counter": "2",
1759         "UMask": "0x1",
1760         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
1761         "MSRIndex": "0x1A6",
1762         "SampleAfterValue": "100000",
1763         "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
1764         "Offcore": "1"
1765     },
1766     {
1767         "EventCode": "0xB7",
1768         "MSRValue": "0x877",
1769         "Counter": "2",
1770         "UMask": "0x1",
1771         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
1772         "MSRIndex": "0x1A6",
1773         "SampleAfterValue": "100000",
1774         "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
1775         "Offcore": "1"
1776     },
1777     {
1778         "EventCode": "0xB7",
1779         "MSRValue": "0x7F33",
1780         "Counter": "2",
1781         "UMask": "0x1",
1782         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
1783         "MSRIndex": "0x1A6",
1784         "SampleAfterValue": "100000",
1785         "BriefDescription": "Offcore request = all data, response = any cache_dram",
1786         "Offcore": "1"
1787     },
1788     {
1789         "EventCode": "0xB7",
1790         "MSRValue": "0xFF33",
1791         "Counter": "2",
1792         "UMask": "0x1",
1793         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
1794         "MSRIndex": "0x1A6",
1795         "SampleAfterValue": "100000",
1796         "BriefDescription": "Offcore request = all data, response = any location",
1797         "Offcore": "1"
1798     },
1799     {
1800         "EventCode": "0xB7",
1801         "MSRValue": "0x8033",
1802         "Counter": "2",
1803         "UMask": "0x1",
1804         "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
1805         "MSRIndex": "0x1A6",
1806         "SampleAfterValue": "100000",
1807         "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit",
1808         "Offcore": "1"
1809     },
1810     {
1811         "EventCode": "0xB7",
1812         "MSRValue": "0x133",
1813         "Counter": "2",
1814         "UMask": "0x1",
1815         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
1816         "MSRIndex": "0x1A6",
1817         "SampleAfterValue": "100000",
1818         "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core",
1819         "Offcore": "1"
1820     },
1821     {
1822         "EventCode": "0xB7",
1823         "MSRValue": "0x233",
1824         "Counter": "2",
1825         "UMask": "0x1",
1826         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
1827         "MSRIndex": "0x1A6",
1828         "SampleAfterValue": "100000",
1829         "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core",
1830         "Offcore": "1"
1831     },
1832     {
1833         "EventCode": "0xB7",
1834         "MSRValue": "0x433",
1835         "Counter": "2",
1836         "UMask": "0x1",
1837         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
1838         "MSRIndex": "0x1A6",
1839         "SampleAfterValue": "100000",
1840         "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling core",
1841         "Offcore": "1"
1842     },
1843     {
1844         "EventCode": "0xB7",
1845         "MSRValue": "0x733",
1846         "Counter": "2",
1847         "UMask": "0x1",
1848         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
1849         "MSRIndex": "0x1A6",
1850         "SampleAfterValue": "100000",
1851         "BriefDescription": "Offcore request = all data, response = local cache",
1852         "Offcore": "1"
1853     },
1854     {
1855         "EventCode": "0xB7",
1856         "MSRValue": "0x4733",
1857         "Counter": "2",
1858         "UMask": "0x1",
1859         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
1860         "MSRIndex": "0x1A6",
1861         "SampleAfterValue": "100000",
1862         "BriefDescription": "Offcore request = all data, response = local cache or dram",
1863         "Offcore": "1"
1864     },
1865     {
1866         "EventCode": "0xB7",
1867         "MSRValue": "0x1833",
1868         "Counter": "2",
1869         "UMask": "0x1",
1870         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
1871         "MSRIndex": "0x1A6",
1872         "SampleAfterValue": "100000",
1873         "BriefDescription": "Offcore request = all data, response = remote cache",
1874         "Offcore": "1"
1875     },
1876     {
1877         "EventCode": "0xB7",
1878         "MSRValue": "0x3833",
1879         "Counter": "2",
1880         "UMask": "0x1",
1881         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
1882         "MSRIndex": "0x1A6",
1883         "SampleAfterValue": "100000",
1884         "BriefDescription": "Offcore request = all data, response = remote cache or dram",
1885         "Offcore": "1"
1886     },
1887     {
1888         "EventCode": "0xB7",
1889         "MSRValue": "0x1033",
1890         "Counter": "2",
1891         "UMask": "0x1",
1892         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
1893         "MSRIndex": "0x1A6",
1894         "SampleAfterValue": "100000",
1895         "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ",
1896         "Offcore": "1"
1897     },
1898     {
1899         "EventCode": "0xB7",
1900         "MSRValue": "0x833",
1901         "Counter": "2",
1902         "UMask": "0x1",
1903         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
1904         "MSRIndex": "0x1A6",
1905         "SampleAfterValue": "100000",
1906         "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache",
1907         "Offcore": "1"
1908     },
1909     {
1910         "EventCode": "0xB7",
1911         "MSRValue": "0x7F03",
1912         "Counter": "2",
1913         "UMask": "0x1",
1914         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
1915         "MSRIndex": "0x1A6",
1916         "SampleAfterValue": "100000",
1917         "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
1918         "Offcore": "1"
1919     },
1920     {
1921         "EventCode": "0xB7",
1922         "MSRValue": "0xFF03",
1923         "Counter": "2",
1924         "UMask": "0x1",
1925         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
1926         "MSRIndex": "0x1A6",
1927         "SampleAfterValue": "100000",
1928         "BriefDescription": "All offcore demand data requests",
1929         "Offcore": "1"
1930     },
1931     {
1932         "EventCode": "0xB7",
1933         "MSRValue": "0x8003",
1934         "Counter": "2",
1935         "UMask": "0x1",
1936         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
1937         "MSRIndex": "0x1A6",
1938         "SampleAfterValue": "100000",
1939         "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
1940         "Offcore": "1"
1941     },
1942     {
1943         "EventCode": "0xB7",
1944         "MSRValue": "0x103",
1945         "Counter": "2",
1946         "UMask": "0x1",
1947         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
1948         "MSRIndex": "0x1A6",
1949         "SampleAfterValue": "100000",
1950         "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
1951         "Offcore": "1"
1952     },
1953     {
1954         "EventCode": "0xB7",
1955         "MSRValue": "0x203",
1956         "Counter": "2",
1957         "UMask": "0x1",
1958         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
1959         "MSRIndex": "0x1A6",
1960         "SampleAfterValue": "100000",
1961         "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
1962         "Offcore": "1"
1963     },
1964     {
1965         "EventCode": "0xB7",
1966         "MSRValue": "0x403",
1967         "Counter": "2",
1968         "UMask": "0x1",
1969         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
1970         "MSRIndex": "0x1A6",
1971         "SampleAfterValue": "100000",
1972         "BriefDescription": "Offcore demand data requests satisfied by the LLC  and HITM in a sibling core",
1973         "Offcore": "1"
1974     },
1975     {
1976         "EventCode": "0xB7",
1977         "MSRValue": "0x703",
1978         "Counter": "2",
1979         "UMask": "0x1",
1980         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
1981         "MSRIndex": "0x1A6",
1982         "SampleAfterValue": "100000",
1983         "BriefDescription": "Offcore demand data requests satisfied by the LLC",
1984         "Offcore": "1"
1985     },
1986     {
1987         "EventCode": "0xB7",
1988         "MSRValue": "0x4703",
1989         "Counter": "2",
1990         "UMask": "0x1",
1991         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
1992         "MSRIndex": "0x1A6",
1993         "SampleAfterValue": "100000",
1994         "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
1995         "Offcore": "1"
1996     },
1997     {
1998         "EventCode": "0xB7",
1999         "MSRValue": "0x1803",
2000         "Counter": "2",
2001         "UMask": "0x1",
2002         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
2003         "MSRIndex": "0x1A6",
2004         "SampleAfterValue": "100000",
2005         "BriefDescription": "Offcore demand data requests satisfied by a remote cache",
2006         "Offcore": "1"
2007     },
2008     {
2009         "EventCode": "0xB7",
2010         "MSRValue": "0x3803",
2011         "Counter": "2",
2012         "UMask": "0x1",
2013         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
2014         "MSRIndex": "0x1A6",
2015         "SampleAfterValue": "100000",
2016         "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
2017         "Offcore": "1"
2018     },
2019     {
2020         "EventCode": "0xB7",
2021         "MSRValue": "0x1003",
2022         "Counter": "2",
2023         "UMask": "0x1",
2024         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
2025         "MSRIndex": "0x1A6",
2026         "SampleAfterValue": "100000",
2027         "BriefDescription": "Offcore demand data requests that HIT in a remote cache",
2028         "Offcore": "1"
2029     },
2030     {
2031         "EventCode": "0xB7",
2032         "MSRValue": "0x803",
2033         "Counter": "2",
2034         "UMask": "0x1",
2035         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
2036         "MSRIndex": "0x1A6",
2037         "SampleAfterValue": "100000",
2038         "BriefDescription": "Offcore demand data requests that HITM in a remote cache",
2039         "Offcore": "1"
2040     },
2041     {
2042         "EventCode": "0xB7",
2043         "MSRValue": "0x7F01",
2044         "Counter": "2",
2045         "UMask": "0x1",
2046         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
2047         "MSRIndex": "0x1A6",
2048         "SampleAfterValue": "100000",
2049         "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
2050         "Offcore": "1"
2051     },
2052     {
2053         "EventCode": "0xB7",
2054         "MSRValue": "0xFF01",
2055         "Counter": "2",
2056         "UMask": "0x1",
2057         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
2058         "MSRIndex": "0x1A6",
2059         "SampleAfterValue": "100000",
2060         "BriefDescription": "All offcore demand data reads",
2061         "Offcore": "1"
2062     },
2063     {
2064         "EventCode": "0xB7",
2065         "MSRValue": "0x8001",
2066         "Counter": "2",
2067         "UMask": "0x1",
2068         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
2069         "MSRIndex": "0x1A6",
2070         "SampleAfterValue": "100000",
2071         "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
2072         "Offcore": "1"
2073     },
2074     {
2075         "EventCode": "0xB7",
2076         "MSRValue": "0x101",
2077         "Counter": "2",
2078         "UMask": "0x1",
2079         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
2080         "MSRIndex": "0x1A6",
2081         "SampleAfterValue": "100000",
2082         "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
2083         "Offcore": "1"
2084     },
2085     {
2086         "EventCode": "0xB7",
2087         "MSRValue": "0x201",
2088         "Counter": "2",
2089         "UMask": "0x1",
2090         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
2091         "MSRIndex": "0x1A6",
2092         "SampleAfterValue": "100000",
2093         "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
2094         "Offcore": "1"
2095     },
2096     {
2097         "EventCode": "0xB7",
2098         "MSRValue": "0x401",
2099         "Counter": "2",
2100         "UMask": "0x1",
2101         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
2102         "MSRIndex": "0x1A6",
2103         "SampleAfterValue": "100000",
2104         "BriefDescription": "Offcore demand data reads satisfied by the LLC  and HITM in a sibling core",
2105         "Offcore": "1"
2106     },
2107     {
2108         "EventCode": "0xB7",
2109         "MSRValue": "0x701",
2110         "Counter": "2",
2111         "UMask": "0x1",
2112         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
2113         "MSRIndex": "0x1A6",
2114         "SampleAfterValue": "100000",
2115         "BriefDescription": "Offcore demand data reads satisfied by the LLC",
2116         "Offcore": "1"
2117     },
2118     {
2119         "EventCode": "0xB7",
2120         "MSRValue": "0x4701",
2121         "Counter": "2",
2122         "UMask": "0x1",
2123         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
2124         "MSRIndex": "0x1A6",
2125         "SampleAfterValue": "100000",
2126         "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
2127         "Offcore": "1"
2128     },
2129     {
2130         "EventCode": "0xB7",
2131         "MSRValue": "0x1801",
2132         "Counter": "2",
2133         "UMask": "0x1",
2134         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
2135         "MSRIndex": "0x1A6",
2136         "SampleAfterValue": "100000",
2137         "BriefDescription": "Offcore demand data reads satisfied by a remote cache",
2138         "Offcore": "1"
2139     },
2140     {
2141         "EventCode": "0xB7",
2142         "MSRValue": "0x3801",
2143         "Counter": "2",
2144         "UMask": "0x1",
2145         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
2146         "MSRIndex": "0x1A6",
2147         "SampleAfterValue": "100000",
2148         "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
2149         "Offcore": "1"
2150     },
2151     {
2152         "EventCode": "0xB7",
2153         "MSRValue": "0x1001",
2154         "Counter": "2",
2155         "UMask": "0x1",
2156         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
2157         "MSRIndex": "0x1A6",
2158         "SampleAfterValue": "100000",
2159         "BriefDescription": "Offcore demand data reads that HIT in a remote cache",
2160         "Offcore": "1"
2161     },
2162     {
2163         "EventCode": "0xB7",
2164         "MSRValue": "0x801",
2165         "Counter": "2",
2166         "UMask": "0x1",
2167         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
2168         "MSRIndex": "0x1A6",
2169         "SampleAfterValue": "100000",
2170         "BriefDescription": "Offcore demand data reads that HITM in a remote cache",
2171         "Offcore": "1"
2172     },
2173     {
2174         "EventCode": "0xB7",
2175         "MSRValue": "0x7F04",
2176         "Counter": "2",
2177         "UMask": "0x1",
2178         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
2179         "MSRIndex": "0x1A6",
2180         "SampleAfterValue": "100000",
2181         "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
2182         "Offcore": "1"
2183     },
2184     {
2185         "EventCode": "0xB7",
2186         "MSRValue": "0xFF04",
2187         "Counter": "2",
2188         "UMask": "0x1",
2189         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
2190         "MSRIndex": "0x1A6",
2191         "SampleAfterValue": "100000",
2192         "BriefDescription": "All offcore demand code reads",
2193         "Offcore": "1"
2194     },
2195     {
2196         "EventCode": "0xB7",
2197         "MSRValue": "0x8004",
2198         "Counter": "2",
2199         "UMask": "0x1",
2200         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
2201         "MSRIndex": "0x1A6",
2202         "SampleAfterValue": "100000",
2203         "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
2204         "Offcore": "1"
2205     },
2206     {
2207         "EventCode": "0xB7",
2208         "MSRValue": "0x104",
2209         "Counter": "2",
2210         "UMask": "0x1",
2211         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
2212         "MSRIndex": "0x1A6",
2213         "SampleAfterValue": "100000",
2214         "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
2215         "Offcore": "1"
2216     },
2217     {
2218         "EventCode": "0xB7",
2219         "MSRValue": "0x204",
2220         "Counter": "2",
2221         "UMask": "0x1",
2222         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2223         "MSRIndex": "0x1A6",
2224         "SampleAfterValue": "100000",
2225         "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
2226         "Offcore": "1"
2227     },
2228     {
2229         "EventCode": "0xB7",
2230         "MSRValue": "0x404",
2231         "Counter": "2",
2232         "UMask": "0x1",
2233         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2234         "MSRIndex": "0x1A6",
2235         "SampleAfterValue": "100000",
2236         "BriefDescription": "Offcore demand code reads satisfied by the LLC  and HITM in a sibling core",
2237         "Offcore": "1"
2238     },
2239     {
2240         "EventCode": "0xB7",
2241         "MSRValue": "0x704",
2242         "Counter": "2",
2243         "UMask": "0x1",
2244         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
2245         "MSRIndex": "0x1A6",
2246         "SampleAfterValue": "100000",
2247         "BriefDescription": "Offcore demand code reads satisfied by the LLC",
2248         "Offcore": "1"
2249     },
2250     {
2251         "EventCode": "0xB7",
2252         "MSRValue": "0x4704",
2253         "Counter": "2",
2254         "UMask": "0x1",
2255         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
2256         "MSRIndex": "0x1A6",
2257         "SampleAfterValue": "100000",
2258         "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
2259         "Offcore": "1"
2260     },
2261     {
2262         "EventCode": "0xB7",
2263         "MSRValue": "0x1804",
2264         "Counter": "2",
2265         "UMask": "0x1",
2266         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
2267         "MSRIndex": "0x1A6",
2268         "SampleAfterValue": "100000",
2269         "BriefDescription": "Offcore demand code reads satisfied by a remote cache",
2270         "Offcore": "1"
2271     },
2272     {
2273         "EventCode": "0xB7",
2274         "MSRValue": "0x3804",
2275         "Counter": "2",
2276         "UMask": "0x1",
2277         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
2278         "MSRIndex": "0x1A6",
2279         "SampleAfterValue": "100000",
2280         "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
2281         "Offcore": "1"
2282     },
2283     {
2284         "EventCode": "0xB7",
2285         "MSRValue": "0x1004",
2286         "Counter": "2",
2287         "UMask": "0x1",
2288         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
2289         "MSRIndex": "0x1A6",
2290         "SampleAfterValue": "100000",
2291         "BriefDescription": "Offcore demand code reads that HIT in a remote cache",
2292         "Offcore": "1"
2293     },
2294     {
2295         "EventCode": "0xB7",
2296         "MSRValue": "0x804",
2297         "Counter": "2",
2298         "UMask": "0x1",
2299         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
2300         "MSRIndex": "0x1A6",
2301         "SampleAfterValue": "100000",
2302         "BriefDescription": "Offcore demand code reads that HITM in a remote cache",
2303         "Offcore": "1"
2304     },
2305     {
2306         "EventCode": "0xB7",
2307         "MSRValue": "0x7F02",
2308         "Counter": "2",
2309         "UMask": "0x1",
2310         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
2311         "MSRIndex": "0x1A6",
2312         "SampleAfterValue": "100000",
2313         "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
2314         "Offcore": "1"
2315     },
2316     {
2317         "EventCode": "0xB7",
2318         "MSRValue": "0xFF02",
2319         "Counter": "2",
2320         "UMask": "0x1",
2321         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
2322         "MSRIndex": "0x1A6",
2323         "SampleAfterValue": "100000",
2324         "BriefDescription": "All offcore demand RFO requests",
2325         "Offcore": "1"
2326     },
2327     {
2328         "EventCode": "0xB7",
2329         "MSRValue": "0x8002",
2330         "Counter": "2",
2331         "UMask": "0x1",
2332         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
2333         "MSRIndex": "0x1A6",
2334         "SampleAfterValue": "100000",
2335         "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
2336         "Offcore": "1"
2337     },
2338     {
2339         "EventCode": "0xB7",
2340         "MSRValue": "0x102",
2341         "Counter": "2",
2342         "UMask": "0x1",
2343         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
2344         "MSRIndex": "0x1A6",
2345         "SampleAfterValue": "100000",
2346         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
2347         "Offcore": "1"
2348     },
2349     {
2350         "EventCode": "0xB7",
2351         "MSRValue": "0x202",
2352         "Counter": "2",
2353         "UMask": "0x1",
2354         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
2355         "MSRIndex": "0x1A6",
2356         "SampleAfterValue": "100000",
2357         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
2358         "Offcore": "1"
2359     },
2360     {
2361         "EventCode": "0xB7",
2362         "MSRValue": "0x402",
2363         "Counter": "2",
2364         "UMask": "0x1",
2365         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
2366         "MSRIndex": "0x1A6",
2367         "SampleAfterValue": "100000",
2368         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core",
2369         "Offcore": "1"
2370     },
2371     {
2372         "EventCode": "0xB7",
2373         "MSRValue": "0x702",
2374         "Counter": "2",
2375         "UMask": "0x1",
2376         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
2377         "MSRIndex": "0x1A6",
2378         "SampleAfterValue": "100000",
2379         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
2380         "Offcore": "1"
2381     },
2382     {
2383         "EventCode": "0xB7",
2384         "MSRValue": "0x4702",
2385         "Counter": "2",
2386         "UMask": "0x1",
2387         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
2388         "MSRIndex": "0x1A6",
2389         "SampleAfterValue": "100000",
2390         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
2391         "Offcore": "1"
2392     },
2393     {
2394         "EventCode": "0xB7",
2395         "MSRValue": "0x1802",
2396         "Counter": "2",
2397         "UMask": "0x1",
2398         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
2399         "MSRIndex": "0x1A6",
2400         "SampleAfterValue": "100000",
2401         "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
2402         "Offcore": "1"
2403     },
2404     {
2405         "EventCode": "0xB7",
2406         "MSRValue": "0x3802",
2407         "Counter": "2",
2408         "UMask": "0x1",
2409         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
2410         "MSRIndex": "0x1A6",
2411         "SampleAfterValue": "100000",
2412         "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
2413         "Offcore": "1"
2414     },
2415     {
2416         "EventCode": "0xB7",
2417         "MSRValue": "0x1002",
2418         "Counter": "2",
2419         "UMask": "0x1",
2420         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
2421         "MSRIndex": "0x1A6",
2422         "SampleAfterValue": "100000",
2423         "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
2424         "Offcore": "1"
2425     },
2426     {
2427         "EventCode": "0xB7",
2428         "MSRValue": "0x802",
2429         "Counter": "2",
2430         "UMask": "0x1",
2431         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
2432         "MSRIndex": "0x1A6",
2433         "SampleAfterValue": "100000",
2434         "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
2435         "Offcore": "1"
2436     },
2437     {
2438         "EventCode": "0xB7",
2439         "MSRValue": "0x7F80",
2440         "Counter": "2",
2441         "UMask": "0x1",
2442         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
2443         "MSRIndex": "0x1A6",
2444         "SampleAfterValue": "100000",
2445         "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
2446         "Offcore": "1"
2447     },
2448     {
2449         "EventCode": "0xB7",
2450         "MSRValue": "0xFF80",
2451         "Counter": "2",
2452         "UMask": "0x1",
2453         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
2454         "MSRIndex": "0x1A6",
2455         "SampleAfterValue": "100000",
2456         "BriefDescription": "All offcore other requests",
2457         "Offcore": "1"
2458     },
2459     {
2460         "EventCode": "0xB7",
2461         "MSRValue": "0x8080",
2462         "Counter": "2",
2463         "UMask": "0x1",
2464         "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
2465         "MSRIndex": "0x1A6",
2466         "SampleAfterValue": "100000",
2467         "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
2468         "Offcore": "1"
2469     },
2470     {
2471         "EventCode": "0xB7",
2472         "MSRValue": "0x180",
2473         "Counter": "2",
2474         "UMask": "0x1",
2475         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
2476         "MSRIndex": "0x1A6",
2477         "SampleAfterValue": "100000",
2478         "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
2479         "Offcore": "1"
2480     },
2481     {
2482         "EventCode": "0xB7",
2483         "MSRValue": "0x280",
2484         "Counter": "2",
2485         "UMask": "0x1",
2486         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
2487         "MSRIndex": "0x1A6",
2488         "SampleAfterValue": "100000",
2489         "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
2490         "Offcore": "1"
2491     },
2492     {
2493         "EventCode": "0xB7",
2494         "MSRValue": "0x480",
2495         "Counter": "2",
2496         "UMask": "0x1",
2497         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
2498         "MSRIndex": "0x1A6",
2499         "SampleAfterValue": "100000",
2500         "BriefDescription": "Offcore other requests satisfied by the LLC  and HITM in a sibling core",
2501         "Offcore": "1"
2502     },
2503     {
2504         "EventCode": "0xB7",
2505         "MSRValue": "0x780",
2506         "Counter": "2",
2507         "UMask": "0x1",
2508         "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
2509         "MSRIndex": "0x1A6",
2510         "SampleAfterValue": "100000",
2511         "BriefDescription": "Offcore other requests satisfied by the LLC",
2512         "Offcore": "1"
2513     },
2514     {
2515         "EventCode": "0xB7",
2516         "MSRValue": "0x4780",
2517         "Counter": "2",
2518         "UMask": "0x1",
2519         "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
2520         "MSRIndex": "0x1A6",
2521         "SampleAfterValue": "100000",
2522         "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
2523         "Offcore": "1"
2524     },
2525     {
2526         "EventCode": "0xB7",
2527         "MSRValue": "0x1880",
2528         "Counter": "2",
2529         "UMask": "0x1",
2530         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
2531         "MSRIndex": "0x1A6",
2532         "SampleAfterValue": "100000",
2533         "BriefDescription": "Offcore other requests satisfied by a remote cache",
2534         "Offcore": "1"
2535     },
2536     {
2537         "EventCode": "0xB7",
2538         "MSRValue": "0x3880",
2539         "Counter": "2",
2540         "UMask": "0x1",
2541         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
2542         "MSRIndex": "0x1A6",
2543         "SampleAfterValue": "100000",
2544         "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
2545         "Offcore": "1"
2546     },
2547     {
2548         "EventCode": "0xB7",
2549         "MSRValue": "0x1080",
2550         "Counter": "2",
2551         "UMask": "0x1",
2552         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
2553         "MSRIndex": "0x1A6",
2554         "SampleAfterValue": "100000",
2555         "BriefDescription": "Offcore other requests that HIT in a remote cache",
2556         "Offcore": "1"
2557     },
2558     {
2559         "EventCode": "0xB7",
2560         "MSRValue": "0x880",
2561         "Counter": "2",
2562         "UMask": "0x1",
2563         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
2564         "MSRIndex": "0x1A6",
2565         "SampleAfterValue": "100000",
2566         "BriefDescription": "Offcore other requests that HITM in a remote cache",
2567         "Offcore": "1"
2568     },
2569     {
2570         "EventCode": "0xB7",
2571         "MSRValue": "0x7F30",
2572         "Counter": "2",
2573         "UMask": "0x1",
2574         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
2575         "MSRIndex": "0x1A6",
2576         "SampleAfterValue": "100000",
2577         "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
2578         "Offcore": "1"
2579     },
2580     {
2581         "EventCode": "0xB7",
2582         "MSRValue": "0xFF30",
2583         "Counter": "2",
2584         "UMask": "0x1",
2585         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
2586         "MSRIndex": "0x1A6",
2587         "SampleAfterValue": "100000",
2588         "BriefDescription": "All offcore prefetch data requests",
2589         "Offcore": "1"
2590     },
2591     {
2592         "EventCode": "0xB7",
2593         "MSRValue": "0x8030",
2594         "Counter": "2",
2595         "UMask": "0x1",
2596         "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
2597         "MSRIndex": "0x1A6",
2598         "SampleAfterValue": "100000",
2599         "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
2600         "Offcore": "1"
2601     },
2602     {
2603         "EventCode": "0xB7",
2604         "MSRValue": "0x130",
2605         "Counter": "2",
2606         "UMask": "0x1",
2607         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
2608         "MSRIndex": "0x1A6",
2609         "SampleAfterValue": "100000",
2610         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
2611         "Offcore": "1"
2612     },
2613     {
2614         "EventCode": "0xB7",
2615         "MSRValue": "0x230",
2616         "Counter": "2",
2617         "UMask": "0x1",
2618         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
2619         "MSRIndex": "0x1A6",
2620         "SampleAfterValue": "100000",
2621         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
2622         "Offcore": "1"
2623     },
2624     {
2625         "EventCode": "0xB7",
2626         "MSRValue": "0x430",
2627         "Counter": "2",
2628         "UMask": "0x1",
2629         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
2630         "MSRIndex": "0x1A6",
2631         "SampleAfterValue": "100000",
2632         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core",
2633         "Offcore": "1"
2634     },
2635     {
2636         "EventCode": "0xB7",
2637         "MSRValue": "0x730",
2638         "Counter": "2",
2639         "UMask": "0x1",
2640         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
2641         "MSRIndex": "0x1A6",
2642         "SampleAfterValue": "100000",
2643         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
2644         "Offcore": "1"
2645     },
2646     {
2647         "EventCode": "0xB7",
2648         "MSRValue": "0x4730",
2649         "Counter": "2",
2650         "UMask": "0x1",
2651         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
2652         "MSRIndex": "0x1A6",
2653         "SampleAfterValue": "100000",
2654         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
2655         "Offcore": "1"
2656     },
2657     {
2658         "EventCode": "0xB7",
2659         "MSRValue": "0x1830",
2660         "Counter": "2",
2661         "UMask": "0x1",
2662         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
2663         "MSRIndex": "0x1A6",
2664         "SampleAfterValue": "100000",
2665         "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
2666         "Offcore": "1"
2667     },
2668     {
2669         "EventCode": "0xB7",
2670         "MSRValue": "0x3830",
2671         "Counter": "2",
2672         "UMask": "0x1",
2673         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
2674         "MSRIndex": "0x1A6",
2675         "SampleAfterValue": "100000",
2676         "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
2677         "Offcore": "1"
2678     },
2679     {
2680         "EventCode": "0xB7",
2681         "MSRValue": "0x1030",
2682         "Counter": "2",
2683         "UMask": "0x1",
2684         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
2685         "MSRIndex": "0x1A6",
2686         "SampleAfterValue": "100000",
2687         "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
2688         "Offcore": "1"
2689     },
2690     {
2691         "EventCode": "0xB7",
2692         "MSRValue": "0x830",
2693         "Counter": "2",
2694         "UMask": "0x1",
2695         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
2696         "MSRIndex": "0x1A6",
2697         "SampleAfterValue": "100000",
2698         "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
2699         "Offcore": "1"
2700     },
2701     {
2702         "EventCode": "0xB7",
2703         "MSRValue": "0x7F10",
2704         "Counter": "2",
2705         "UMask": "0x1",
2706         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
2707         "MSRIndex": "0x1A6",
2708         "SampleAfterValue": "100000",
2709         "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
2710         "Offcore": "1"
2711     },
2712     {
2713         "EventCode": "0xB7",
2714         "MSRValue": "0xFF10",
2715         "Counter": "2",
2716         "UMask": "0x1",
2717         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
2718         "MSRIndex": "0x1A6",
2719         "SampleAfterValue": "100000",
2720         "BriefDescription": "All offcore prefetch data reads",
2721         "Offcore": "1"
2722     },
2723     {
2724         "EventCode": "0xB7",
2725         "MSRValue": "0x8010",
2726         "Counter": "2",
2727         "UMask": "0x1",
2728         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
2729         "MSRIndex": "0x1A6",
2730         "SampleAfterValue": "100000",
2731         "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
2732         "Offcore": "1"
2733     },
2734     {
2735         "EventCode": "0xB7",
2736         "MSRValue": "0x110",
2737         "Counter": "2",
2738         "UMask": "0x1",
2739         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
2740         "MSRIndex": "0x1A6",
2741         "SampleAfterValue": "100000",
2742         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
2743         "Offcore": "1"
2744     },
2745     {
2746         "EventCode": "0xB7",
2747         "MSRValue": "0x210",
2748         "Counter": "2",
2749         "UMask": "0x1",
2750         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
2751         "MSRIndex": "0x1A6",
2752         "SampleAfterValue": "100000",
2753         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
2754         "Offcore": "1"
2755     },
2756     {
2757         "EventCode": "0xB7",
2758         "MSRValue": "0x410",
2759         "Counter": "2",
2760         "UMask": "0x1",
2761         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
2762         "MSRIndex": "0x1A6",
2763         "SampleAfterValue": "100000",
2764         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core",
2765         "Offcore": "1"
2766     },
2767     {
2768         "EventCode": "0xB7",
2769         "MSRValue": "0x710",
2770         "Counter": "2",
2771         "UMask": "0x1",
2772         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
2773         "MSRIndex": "0x1A6",
2774         "SampleAfterValue": "100000",
2775         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
2776         "Offcore": "1"
2777     },
2778     {
2779         "EventCode": "0xB7",
2780         "MSRValue": "0x4710",
2781         "Counter": "2",
2782         "UMask": "0x1",
2783         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
2784         "MSRIndex": "0x1A6",
2785         "SampleAfterValue": "100000",
2786         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
2787         "Offcore": "1"
2788     },
2789     {
2790         "EventCode": "0xB7",
2791         "MSRValue": "0x1810",
2792         "Counter": "2",
2793         "UMask": "0x1",
2794         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
2795         "MSRIndex": "0x1A6",
2796         "SampleAfterValue": "100000",
2797         "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
2798         "Offcore": "1"
2799     },
2800     {
2801         "EventCode": "0xB7",
2802         "MSRValue": "0x3810",
2803         "Counter": "2",
2804         "UMask": "0x1",
2805         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
2806         "MSRIndex": "0x1A6",
2807         "SampleAfterValue": "100000",
2808         "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
2809         "Offcore": "1"
2810     },
2811     {
2812         "EventCode": "0xB7",
2813         "MSRValue": "0x1010",
2814         "Counter": "2",
2815         "UMask": "0x1",
2816         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
2817         "MSRIndex": "0x1A6",
2818         "SampleAfterValue": "100000",
2819         "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
2820         "Offcore": "1"
2821     },
2822     {
2823         "EventCode": "0xB7",
2824         "MSRValue": "0x810",
2825         "Counter": "2",
2826         "UMask": "0x1",
2827         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
2828         "MSRIndex": "0x1A6",
2829         "SampleAfterValue": "100000",
2830         "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
2831         "Offcore": "1"
2832     },
2833     {
2834         "EventCode": "0xB7",
2835         "MSRValue": "0x7F40",
2836         "Counter": "2",
2837         "UMask": "0x1",
2838         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
2839         "MSRIndex": "0x1A6",
2840         "SampleAfterValue": "100000",
2841         "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
2842         "Offcore": "1"
2843     },
2844     {
2845         "EventCode": "0xB7",
2846         "MSRValue": "0xFF40",
2847         "Counter": "2",
2848         "UMask": "0x1",
2849         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
2850         "MSRIndex": "0x1A6",
2851         "SampleAfterValue": "100000",
2852         "BriefDescription": "All offcore prefetch code reads",
2853         "Offcore": "1"
2854     },
2855     {
2856         "EventCode": "0xB7",
2857         "MSRValue": "0x8040",
2858         "Counter": "2",
2859         "UMask": "0x1",
2860         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
2861         "MSRIndex": "0x1A6",
2862         "SampleAfterValue": "100000",
2863         "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
2864         "Offcore": "1"
2865     },
2866     {
2867         "EventCode": "0xB7",
2868         "MSRValue": "0x140",
2869         "Counter": "2",
2870         "UMask": "0x1",
2871         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
2872         "MSRIndex": "0x1A6",
2873         "SampleAfterValue": "100000",
2874         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
2875         "Offcore": "1"
2876     },
2877     {
2878         "EventCode": "0xB7",
2879         "MSRValue": "0x240",
2880         "Counter": "2",
2881         "UMask": "0x1",
2882         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2883         "MSRIndex": "0x1A6",
2884         "SampleAfterValue": "100000",
2885         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
2886         "Offcore": "1"
2887     },
2888     {
2889         "EventCode": "0xB7",
2890         "MSRValue": "0x440",
2891         "Counter": "2",
2892         "UMask": "0x1",
2893         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2894         "MSRIndex": "0x1A6",
2895         "SampleAfterValue": "100000",
2896         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core",
2897         "Offcore": "1"
2898     },
2899     {
2900         "EventCode": "0xB7",
2901         "MSRValue": "0x740",
2902         "Counter": "2",
2903         "UMask": "0x1",
2904         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
2905         "MSRIndex": "0x1A6",
2906         "SampleAfterValue": "100000",
2907         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
2908         "Offcore": "1"
2909     },
2910     {
2911         "EventCode": "0xB7",
2912         "MSRValue": "0x4740",
2913         "Counter": "2",
2914         "UMask": "0x1",
2915         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
2916         "MSRIndex": "0x1A6",
2917         "SampleAfterValue": "100000",
2918         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
2919         "Offcore": "1"
2920     },
2921     {
2922         "EventCode": "0xB7",
2923         "MSRValue": "0x1840",
2924         "Counter": "2",
2925         "UMask": "0x1",
2926         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
2927         "MSRIndex": "0x1A6",
2928         "SampleAfterValue": "100000",
2929         "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
2930         "Offcore": "1"
2931     },
2932     {
2933         "EventCode": "0xB7",
2934         "MSRValue": "0x3840",
2935         "Counter": "2",
2936         "UMask": "0x1",
2937         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
2938         "MSRIndex": "0x1A6",
2939         "SampleAfterValue": "100000",
2940         "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
2941         "Offcore": "1"
2942     },
2943     {
2944         "EventCode": "0xB7",
2945         "MSRValue": "0x1040",
2946         "Counter": "2",
2947         "UMask": "0x1",
2948         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
2949         "MSRIndex": "0x1A6",
2950         "SampleAfterValue": "100000",
2951         "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
2952         "Offcore": "1"
2953     },
2954     {
2955         "EventCode": "0xB7",
2956         "MSRValue": "0x840",
2957         "Counter": "2",
2958         "UMask": "0x1",
2959         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
2960         "MSRIndex": "0x1A6",
2961         "SampleAfterValue": "100000",
2962         "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
2963         "Offcore": "1"
2964     },
2965     {
2966         "EventCode": "0xB7",
2967         "MSRValue": "0x7F20",
2968         "Counter": "2",
2969         "UMask": "0x1",
2970         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
2971         "MSRIndex": "0x1A6",
2972         "SampleAfterValue": "100000",
2973         "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
2974         "Offcore": "1"
2975     },
2976     {
2977         "EventCode": "0xB7",
2978         "MSRValue": "0xFF20",
2979         "Counter": "2",
2980         "UMask": "0x1",
2981         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
2982         "MSRIndex": "0x1A6",
2983         "SampleAfterValue": "100000",
2984         "BriefDescription": "All offcore prefetch RFO requests",
2985         "Offcore": "1"
2986     },
2987     {
2988         "EventCode": "0xB7",
2989         "MSRValue": "0x8020",
2990         "Counter": "2",
2991         "UMask": "0x1",
2992         "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
2993         "MSRIndex": "0x1A6",
2994         "SampleAfterValue": "100000",
2995         "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
2996         "Offcore": "1"
2997     },
2998     {
2999         "EventCode": "0xB7",
3000         "MSRValue": "0x120",
3001         "Counter": "2",
3002         "UMask": "0x1",
3003         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
3004         "MSRIndex": "0x1A6",
3005         "SampleAfterValue": "100000",
3006         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
3007         "Offcore": "1"
3008     },
3009     {
3010         "EventCode": "0xB7",
3011         "MSRValue": "0x220",
3012         "Counter": "2",
3013         "UMask": "0x1",
3014         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
3015         "MSRIndex": "0x1A6",
3016         "SampleAfterValue": "100000",
3017         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
3018         "Offcore": "1"
3019     },
3020     {
3021         "EventCode": "0xB7",
3022         "MSRValue": "0x420",
3023         "Counter": "2",
3024         "UMask": "0x1",
3025         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
3026         "MSRIndex": "0x1A6",
3027         "SampleAfterValue": "100000",
3028         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core",
3029         "Offcore": "1"
3030     },
3031     {
3032         "EventCode": "0xB7",
3033         "MSRValue": "0x720",
3034         "Counter": "2",
3035         "UMask": "0x1",
3036         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
3037         "MSRIndex": "0x1A6",
3038         "SampleAfterValue": "100000",
3039         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
3040         "Offcore": "1"
3041     },
3042     {
3043         "EventCode": "0xB7",
3044         "MSRValue": "0x4720",
3045         "Counter": "2",
3046         "UMask": "0x1",
3047         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
3048         "MSRIndex": "0x1A6",
3049         "SampleAfterValue": "100000",
3050         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
3051         "Offcore": "1"
3052     },
3053     {
3054         "EventCode": "0xB7",
3055         "MSRValue": "0x1820",
3056         "Counter": "2",
3057         "UMask": "0x1",
3058         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
3059         "MSRIndex": "0x1A6",
3060         "SampleAfterValue": "100000",
3061         "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
3062         "Offcore": "1"
3063     },
3064     {
3065         "EventCode": "0xB7",
3066         "MSRValue": "0x3820",
3067         "Counter": "2",
3068         "UMask": "0x1",
3069         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
3070         "MSRIndex": "0x1A6",
3071         "SampleAfterValue": "100000",
3072         "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
3073         "Offcore": "1"
3074     },
3075     {
3076         "EventCode": "0xB7",
3077         "MSRValue": "0x1020",
3078         "Counter": "2",
3079         "UMask": "0x1",
3080         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
3081         "MSRIndex": "0x1A6",
3082         "SampleAfterValue": "100000",
3083         "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
3084         "Offcore": "1"
3085     },
3086     {
3087         "EventCode": "0xB7",
3088         "MSRValue": "0x820",
3089         "Counter": "2",
3090         "UMask": "0x1",
3091         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
3092         "MSRIndex": "0x1A6",
3093         "SampleAfterValue": "100000",
3094         "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
3095         "Offcore": "1"
3096     },
3097     {
3098         "EventCode": "0xB7",
3099         "MSRValue": "0x7F70",
3100         "Counter": "2",
3101         "UMask": "0x1",
3102         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
3103         "MSRIndex": "0x1A6",
3104         "SampleAfterValue": "100000",
3105         "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
3106         "Offcore": "1"
3107     },
3108     {
3109         "EventCode": "0xB7",
3110         "MSRValue": "0xFF70",
3111         "Counter": "2",
3112         "UMask": "0x1",
3113         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
3114         "MSRIndex": "0x1A6",
3115         "SampleAfterValue": "100000",
3116         "BriefDescription": "All offcore prefetch requests",
3117         "Offcore": "1"
3118     },
3119     {
3120         "EventCode": "0xB7",
3121         "MSRValue": "0x8070",
3122         "Counter": "2",
3123         "UMask": "0x1",
3124         "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
3125         "MSRIndex": "0x1A6",
3126         "SampleAfterValue": "100000",
3127         "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
3128         "Offcore": "1"
3129     },
3130     {
3131         "EventCode": "0xB7",
3132         "MSRValue": "0x170",
3133         "Counter": "2",
3134         "UMask": "0x1",
3135         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
3136         "MSRIndex": "0x1A6",
3137         "SampleAfterValue": "100000",
3138         "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
3139         "Offcore": "1"
3140     },
3141     {
3142         "EventCode": "0xB7",
3143         "MSRValue": "0x270",
3144         "Counter": "2",
3145         "UMask": "0x1",
3146         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
3147         "MSRIndex": "0x1A6",
3148         "SampleAfterValue": "100000",
3149         "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
3150         "Offcore": "1"
3151     },
3152     {
3153         "EventCode": "0xB7",
3154         "MSRValue": "0x470",
3155         "Counter": "2",
3156         "UMask": "0x1",
3157         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
3158         "MSRIndex": "0x1A6",
3159         "SampleAfterValue": "100000",
3160         "BriefDescription": "Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core",
3161         "Offcore": "1"
3162     },
3163     {
3164         "EventCode": "0xB7",
3165         "MSRValue": "0x770",
3166         "Counter": "2",
3167         "UMask": "0x1",
3168         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
3169         "MSRIndex": "0x1A6",
3170         "SampleAfterValue": "100000",
3171         "BriefDescription": "Offcore prefetch requests satisfied by the LLC",
3172         "Offcore": "1"
3173     },
3174     {
3175         "EventCode": "0xB7",
3176         "MSRValue": "0x4770",
3177         "Counter": "2",
3178         "UMask": "0x1",
3179         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
3180         "MSRIndex": "0x1A6",
3181         "SampleAfterValue": "100000",
3182         "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
3183         "Offcore": "1"
3184     },
3185     {
3186         "EventCode": "0xB7",
3187         "MSRValue": "0x1870",
3188         "Counter": "2",
3189         "UMask": "0x1",
3190         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
3191         "MSRIndex": "0x1A6",
3192         "SampleAfterValue": "100000",
3193         "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
3194         "Offcore": "1"
3195     },
3196     {
3197         "EventCode": "0xB7",
3198         "MSRValue": "0x3870",
3199         "Counter": "2",
3200         "UMask": "0x1",
3201         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
3202         "MSRIndex": "0x1A6",
3203         "SampleAfterValue": "100000",
3204         "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
3205         "Offcore": "1"
3206     },
3207     {
3208         "EventCode": "0xB7",
3209         "MSRValue": "0x1070",
3210         "Counter": "2",
3211         "UMask": "0x1",
3212         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
3213         "MSRIndex": "0x1A6",
3214         "SampleAfterValue": "100000",
3215         "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
3216         "Offcore": "1"
3217     },
3218     {
3219         "EventCode": "0xB7",
3220         "MSRValue": "0x870",
3221         "Counter": "2",
3222         "UMask": "0x1",
3223         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
3224         "MSRIndex": "0x1A6",
3225         "SampleAfterValue": "100000",
3226         "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
3227         "Offcore": "1"
3228     }
3229 ]