2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #include <sys/_types.h>
37 #define __fenv_static static
40 typedef __uint32_t fenv_t;
41 typedef __uint32_t fexcept_t;
44 #define FE_INEXACT 0x02000000
45 #define FE_DIVBYZERO 0x04000000
46 #define FE_UNDERFLOW 0x08000000
47 #define FE_OVERFLOW 0x10000000
48 #define FE_INVALID 0x20000000 /* all types of invalid FP ops */
51 * The PowerPC architecture has extra invalid flags that indicate the
52 * specific type of invalid operation occurred. These flags may be
53 * tested, set, and cleared---but not masked---separately. All of
54 * these bits are cleared when FE_INVALID is cleared, but only
55 * FE_VXSOFT is set when FE_INVALID is explicitly set in software.
57 #define FE_VXCVI 0x00000100 /* invalid integer convert */
58 #define FE_VXSQRT 0x00000200 /* square root of a negative */
59 #define FE_VXSOFT 0x00000400 /* software-requested exception */
60 #define FE_VXVC 0x00080000 /* ordered comparison involving NaN */
61 #define FE_VXIMZ 0x00100000 /* inf * 0 */
62 #define FE_VXZDZ 0x00200000 /* 0 / 0 */
63 #define FE_VXIDI 0x00400000 /* inf / inf */
64 #define FE_VXISI 0x00800000 /* inf - inf */
65 #define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */
66 #define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \
67 FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \
68 FE_VXSNAN | FE_INVALID)
69 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
70 FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
73 #define FE_TONEAREST 0x0000
74 #define FE_TOWARDZERO 0x0001
75 #define FE_UPWARD 0x0002
76 #define FE_DOWNWARD 0x0003
77 #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \
78 FE_UPWARD | FE_TOWARDZERO)
82 /* Default floating-point environment */
83 extern const fenv_t __fe_dfl_env;
84 #define FE_DFL_ENV (&__fe_dfl_env)
86 /* We need to be able to map status flag positions to mask flag positions */
87 #define _FPUSW_SHIFT 22
88 #define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \
89 FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT)
93 #define __mffs(__env) __asm __volatile("mfspr %0, 512" : "=r" (*(__env)))
94 #define __mtfsf(__env) __asm __volatile("mtspr 512,%0" : : "r" (__env))
96 #define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env)))
97 #define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env))
100 #define __mffs(__env)
101 #define __mtfsf(__env)
107 #if _BYTE_ORDER == _LITTLE_ENDIAN
117 __fenv_static inline int
118 feclearexcept(int __excepts)
122 if (__excepts & FE_INVALID)
123 __excepts |= FE_ALL_INVALID;
125 __r.__bits.__reg &= ~__excepts;
130 __fenv_static inline int
131 fegetexceptflag(fexcept_t *__flagp, int __excepts)
136 *__flagp = __r.__bits.__reg & __excepts;
140 __fenv_static inline int
141 fesetexceptflag(const fexcept_t *__flagp, int __excepts)
145 if (__excepts & FE_INVALID)
146 __excepts |= FE_ALL_EXCEPT;
148 __r.__bits.__reg &= ~__excepts;
149 __r.__bits.__reg |= *__flagp & __excepts;
154 __fenv_static inline int
155 feraiseexcept(int __excepts)
159 if (__excepts & FE_INVALID)
160 __excepts |= FE_VXSOFT;
162 __r.__bits.__reg |= __excepts;
167 __fenv_static inline int
168 fetestexcept(int __excepts)
173 return (__r.__bits.__reg & __excepts);
176 __fenv_static inline int
182 return (__r.__bits.__reg & _ROUND_MASK);
185 __fenv_static inline int
186 fesetround(int __round)
190 if (__round & ~_ROUND_MASK)
193 __r.__bits.__reg &= ~_ROUND_MASK;
194 __r.__bits.__reg |= __round;
199 __fenv_static inline int
200 fegetenv(fenv_t *__envp)
205 *__envp = __r.__bits.__reg;
209 __fenv_static inline int
210 feholdexcept(fenv_t *__envp)
216 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
221 __fenv_static inline int
222 fesetenv(const fenv_t *__envp)
226 __r.__bits.__reg = *__envp;
231 __fenv_static inline int
232 feupdateenv(const fenv_t *__envp)
237 __r.__bits.__reg &= FE_ALL_EXCEPT;
238 __r.__bits.__reg |= *__envp;
245 /* We currently provide no external definitions of the functions below. */
248 feenableexcept(int __mask)
254 __oldmask = __r.__bits.__reg;
255 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT;
257 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
261 fedisableexcept(int __mask)
267 __oldmask = __r.__bits.__reg;
268 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT);
270 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
279 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT);
282 #endif /* __BSD_VISIBLE */
286 #endif /* !_FENV_H_ */