2 /* Do not modify. This file is auto-generated from armv4cpuid.pl. */
6 #if defined(__thumb2__) && !defined(__APPLE__)
15 .globl OPENSSL_atomic_add
16 .type OPENSSL_atomic_add,%function
27 stmdb sp!,{r4,r5,r6,lr}
32 add r6,r3,r2 @ &spinlock
34 .Lspin: bl sched_yield
43 str r0,[r6] @ release spinlock
44 ldmia sp!,{r4,r5,r6,lr}
47 .word 0xe12fff1e @ bx lr
49 .size OPENSSL_atomic_add,.-OPENSSL_atomic_add
51 .globl OPENSSL_cleanse
52 .type OPENSSL_cleanse,%function
86 .word 0xe12fff1e @ bx lr
88 .size OPENSSL_cleanse,.-OPENSSL_cleanse
91 .type CRYPTO_memcmp,%function
116 .word 0xe12fff1e @ bx lr
118 .size CRYPTO_memcmp,.-CRYPTO_memcmp
120 #if __ARM_MAX_ARCH__>=7
125 .globl _armv7_neon_probe
126 .type _armv7_neon_probe,%function
130 .size _armv7_neon_probe,.-_armv7_neon_probe
133 .type _armv7_tick,%function
136 mrrc p15,0,r0,r1,c14 @ CNTPCT
138 mrrc p15,1,r0,r1,c14 @ CNTVCT
141 .size _armv7_tick,.-_armv7_tick
143 .globl _armv8_aes_probe
144 .type _armv8_aes_probe,%function
146 #if defined(__thumb2__) && !defined(__APPLE__)
147 .byte 0xb0,0xff,0x00,0x03 @ aese.8 q0,q0
149 .byte 0x00,0x03,0xb0,0xf3 @ aese.8 q0,q0
152 .size _armv8_aes_probe,.-_armv8_aes_probe
154 .globl _armv8_sha1_probe
155 .type _armv8_sha1_probe,%function
157 #if defined(__thumb2__) && !defined(__APPLE__)
158 .byte 0x00,0xef,0x40,0x0c @ sha1c.32 q0,q0,q0
160 .byte 0x40,0x0c,0x00,0xf2 @ sha1c.32 q0,q0,q0
163 .size _armv8_sha1_probe,.-_armv8_sha1_probe
165 .globl _armv8_sha256_probe
166 .type _armv8_sha256_probe,%function
168 #if defined(__thumb2__) && !defined(__APPLE__)
169 .byte 0x00,0xff,0x40,0x0c @ sha256h.32 q0,q0,q0
171 .byte 0x40,0x0c,0x00,0xf3 @ sha256h.32 q0,q0,q0
174 .size _armv8_sha256_probe,.-_armv8_sha256_probe
175 .globl _armv8_pmull_probe
176 .type _armv8_pmull_probe,%function
178 #if defined(__thumb2__) && !defined(__APPLE__)
179 .byte 0xa0,0xef,0x00,0x0e @ vmull.p64 q0,d0,d0
181 .byte 0x00,0x0e,0xa0,0xf2 @ vmull.p64 q0,d0,d0
184 .size _armv8_pmull_probe,.-_armv8_pmull_probe
187 .globl OPENSSL_wipe_cpu
188 .type OPENSSL_wipe_cpu,%function
190 #if __ARM_MAX_ARCH__>=7
191 ldr r0,.LOPENSSL_armcap
192 adr r1,.LOPENSSL_armcap
201 #if __ARM_MAX_ARCH__>=7
224 .word 0xe12fff1e @ bx lr
226 .size OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
228 .globl OPENSSL_instrument_bus
229 .type OPENSSL_instrument_bus,%function
230 OPENSSL_instrument_bus:
237 .word 0xe12fff1e @ bx lr
239 .size OPENSSL_instrument_bus,.-OPENSSL_instrument_bus
241 .globl OPENSSL_instrument_bus2
242 .type OPENSSL_instrument_bus2,%function
243 OPENSSL_instrument_bus2:
250 .word 0xe12fff1e @ bx lr
252 .size OPENSSL_instrument_bus2,.-OPENSSL_instrument_bus2
255 #if __ARM_MAX_ARCH__>=7
257 .word OPENSSL_armcap_P-.
263 .word atomic_add_spinlock-.Lspinlock
272 .comm OPENSSL_armcap_P,4,4
273 .hidden OPENSSL_armcap_P