2 /* Do not modify. This file is auto-generated from sha512-armv4.pl. */
7 # define WORD64(hi0,lo0,hi1,lo1) .word lo0,hi0, lo1,hi1
11 # define WORD64(hi0,lo0,hi1,lo1) .word hi0,lo0, hi1,lo1
19 WORD64(0x428a2f98,0xd728ae22, 0x71374491,0x23ef65cd)
20 WORD64(0xb5c0fbcf,0xec4d3b2f, 0xe9b5dba5,0x8189dbbc)
21 WORD64(0x3956c25b,0xf348b538, 0x59f111f1,0xb605d019)
22 WORD64(0x923f82a4,0xaf194f9b, 0xab1c5ed5,0xda6d8118)
23 WORD64(0xd807aa98,0xa3030242, 0x12835b01,0x45706fbe)
24 WORD64(0x243185be,0x4ee4b28c, 0x550c7dc3,0xd5ffb4e2)
25 WORD64(0x72be5d74,0xf27b896f, 0x80deb1fe,0x3b1696b1)
26 WORD64(0x9bdc06a7,0x25c71235, 0xc19bf174,0xcf692694)
27 WORD64(0xe49b69c1,0x9ef14ad2, 0xefbe4786,0x384f25e3)
28 WORD64(0x0fc19dc6,0x8b8cd5b5, 0x240ca1cc,0x77ac9c65)
29 WORD64(0x2de92c6f,0x592b0275, 0x4a7484aa,0x6ea6e483)
30 WORD64(0x5cb0a9dc,0xbd41fbd4, 0x76f988da,0x831153b5)
31 WORD64(0x983e5152,0xee66dfab, 0xa831c66d,0x2db43210)
32 WORD64(0xb00327c8,0x98fb213f, 0xbf597fc7,0xbeef0ee4)
33 WORD64(0xc6e00bf3,0x3da88fc2, 0xd5a79147,0x930aa725)
34 WORD64(0x06ca6351,0xe003826f, 0x14292967,0x0a0e6e70)
35 WORD64(0x27b70a85,0x46d22ffc, 0x2e1b2138,0x5c26c926)
36 WORD64(0x4d2c6dfc,0x5ac42aed, 0x53380d13,0x9d95b3df)
37 WORD64(0x650a7354,0x8baf63de, 0x766a0abb,0x3c77b2a8)
38 WORD64(0x81c2c92e,0x47edaee6, 0x92722c85,0x1482353b)
39 WORD64(0xa2bfe8a1,0x4cf10364, 0xa81a664b,0xbc423001)
40 WORD64(0xc24b8b70,0xd0f89791, 0xc76c51a3,0x0654be30)
41 WORD64(0xd192e819,0xd6ef5218, 0xd6990624,0x5565a910)
42 WORD64(0xf40e3585,0x5771202a, 0x106aa070,0x32bbd1b8)
43 WORD64(0x19a4c116,0xb8d2d0c8, 0x1e376c08,0x5141ab53)
44 WORD64(0x2748774c,0xdf8eeb99, 0x34b0bcb5,0xe19b48a8)
45 WORD64(0x391c0cb3,0xc5c95a63, 0x4ed8aa4a,0xe3418acb)
46 WORD64(0x5b9cca4f,0x7763e373, 0x682e6ff3,0xd6b2b8a3)
47 WORD64(0x748f82ee,0x5defb2fc, 0x78a5636f,0x43172f60)
48 WORD64(0x84c87814,0xa1f0ab72, 0x8cc70208,0x1a6439ec)
49 WORD64(0x90befffa,0x23631e28, 0xa4506ceb,0xde82bde9)
50 WORD64(0xbef9a3f7,0xb2c67915, 0xc67178f2,0xe372532b)
51 WORD64(0xca273ece,0xea26619c, 0xd186b8c7,0x21c0c207)
52 WORD64(0xeada7dd6,0xcde0eb1e, 0xf57d4f7f,0xee6ed178)
53 WORD64(0x06f067aa,0x72176fba, 0x0a637dc5,0xa2c898a6)
54 WORD64(0x113f9804,0xbef90dae, 0x1b710b35,0x131c471b)
55 WORD64(0x28db77f5,0x23047d84, 0x32caab7b,0x40c72493)
56 WORD64(0x3c9ebe0a,0x15c9bebc, 0x431d67c4,0x9c100d4c)
57 WORD64(0x4cc5d4be,0xcb3e42b6, 0x597f299c,0xfc657e2a)
58 WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817)
60 #if __ARM_MAX_ARCH__>=7
62 .word OPENSSL_armcap_P-sha512_block_data_order
68 .global sha512_block_data_order
69 .type sha512_block_data_order,%function
70 sha512_block_data_order:
71 sub r3,pc,#8 @ sha512_block_data_order
72 add r2,r1,r2,lsl#7 @ len to point at the end of inp
73 #if __ARM_MAX_ARCH__>=7
74 ldr r12,.LOPENSSL_armcap
75 ldr r12,[r3,r12] @ OPENSSL_armcap_P
80 sub r14,r3,#672 @ K512
137 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
138 @ LO lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23
139 @ HI hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23
145 ldr r11,[sp,#56+0] @ h.lo
146 eor r10,r10,r7,lsl#18
147 ldr r12,[sp,#56+4] @ h.hi
149 eor r10,r10,r8,lsr#18
151 eor r10,r10,r7,lsl#14
155 eor r10,r10,r8,lsl#23 @ Sigma1(e)
157 ldr r9,[sp,#40+0] @ f.lo
158 adc r4,r4,r10 @ T += Sigma1(e)
159 ldr r10,[sp,#40+4] @ f.hi
161 ldr r11,[sp,#48+0] @ g.lo
162 adc r4,r4,r12 @ T += h
163 ldr r12,[sp,#48+4] @ g.hi
174 ldr r11,[r14,#LO] @ K[i].lo
175 eor r10,r10,r12 @ Ch(e,f,g)
176 ldr r12,[r14,#HI] @ K[i].hi
179 ldr r7,[sp,#24+0] @ d.lo
180 adc r4,r4,r10 @ T += Ch(e,f,g)
181 ldr r8,[sp,#24+4] @ d.hi
184 adc r4,r4,r12 @ T += K[i]
186 ldr r11,[sp,#8+0] @ b.lo
187 adc r8,r8,r4 @ d += T
190 ldr r12,[sp,#16+0] @ c.lo
192 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
193 @ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25
194 @ HI hi>>28^lo<<4 ^ lo>>2^hi<<30 ^ lo>>7^hi<<25
202 eor r10,r10,r6,lsl#30
206 eor r10,r10,r6,lsl#25 @ Sigma0(a)
209 adc r4,r4,r10 @ T += Sigma0(a)
211 ldr r10,[sp,#8+4] @ b.hi
213 ldr r11,[sp,#16+4] @ c.hi
217 orr r5,r5,r9 @ Maj(a,b,c).lo
220 orr r6,r6,r12 @ Maj(a,b,c).hi
222 adc r6,r6,r4 @ h += T
231 @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7))
232 @ LO lo>>1^hi<<31 ^ lo>>8^hi<<24 ^ lo>>7^hi<<25
233 @ HI hi>>1^lo<<31 ^ hi>>8^lo<<24 ^ hi>>7
248 @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6))
249 @ LO lo>>19^hi<<13 ^ hi>>29^lo<<3 ^ lo>>6^hi<<26
250 @ HI hi>>19^lo<<13 ^ lo>>29^hi<<3 ^ hi>>6
254 eor r10,r10,r11,lsl#13
256 eor r10,r10,r11,lsr#29
258 eor r10,r10,r12,lsl#3
260 eor r10,r10,r12,lsr#6
274 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
275 @ LO lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23
276 @ HI hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23
282 ldr r11,[sp,#56+0] @ h.lo
283 eor r10,r10,r7,lsl#18
284 ldr r12,[sp,#56+4] @ h.hi
286 eor r10,r10,r8,lsr#18
288 eor r10,r10,r7,lsl#14
292 eor r10,r10,r8,lsl#23 @ Sigma1(e)
294 ldr r9,[sp,#40+0] @ f.lo
295 adc r4,r4,r10 @ T += Sigma1(e)
296 ldr r10,[sp,#40+4] @ f.hi
298 ldr r11,[sp,#48+0] @ g.lo
299 adc r4,r4,r12 @ T += h
300 ldr r12,[sp,#48+4] @ g.hi
311 ldr r11,[r14,#LO] @ K[i].lo
312 eor r10,r10,r12 @ Ch(e,f,g)
313 ldr r12,[r14,#HI] @ K[i].hi
316 ldr r7,[sp,#24+0] @ d.lo
317 adc r4,r4,r10 @ T += Ch(e,f,g)
318 ldr r8,[sp,#24+4] @ d.hi
321 adc r4,r4,r12 @ T += K[i]
323 ldr r11,[sp,#8+0] @ b.lo
324 adc r8,r8,r4 @ d += T
327 ldr r12,[sp,#16+0] @ c.lo
329 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
330 @ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25
331 @ HI hi>>28^lo<<4 ^ lo>>2^hi<<30 ^ lo>>7^hi<<25
339 eor r10,r10,r6,lsl#30
343 eor r10,r10,r6,lsl#25 @ Sigma0(a)
346 adc r4,r4,r10 @ T += Sigma0(a)
348 ldr r10,[sp,#8+4] @ b.hi
350 ldr r11,[sp,#16+4] @ c.hi
354 orr r5,r5,r9 @ Maj(a,b,c).lo
357 orr r6,r6,r12 @ Maj(a,b,c).hi
359 adc r6,r6,r4 @ h += T
363 ldreq r10,[sp,#184+4]
437 add sp,sp,#8*9 @ destroy frame
439 ldmia sp!,{r4-r12,pc}
441 ldmia sp!,{r4-r12,lr}
443 moveq pc,lr @ be binary compatible with V4, yet
444 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
446 #if __ARM_MAX_ARCH__>=7
452 dmb @ errata #451034 on early Cortex A8
453 vstmdb sp!,{d8-d15} @ ABI specification says so
454 sub r3,r3,#672 @ K512
455 vldmia r0,{d16-d23} @ load context
457 vshr.u64 d24,d20,#14 @ 0
459 vld1.64 {d0},[r1]! @ handles unaligned
463 vadd.i64 d16,d30 @ h+=Maj from the past
466 vld1.64 {d28},[r3,:64]! @ K[i++]
471 #if 0<16 && defined(__ARMEL__)
475 vbsl d29,d21,d22 @ Ch(e,f,g)
477 veor d26,d25 @ Sigma1(e)
489 vbsl d30,d18,d17 @ Maj(a,b,c)
490 veor d23,d26 @ Sigma0(a)
494 vshr.u64 d24,d19,#14 @ 1
496 vld1.64 {d1},[r1]! @ handles unaligned
500 vadd.i64 d23,d30 @ h+=Maj from the past
503 vld1.64 {d28},[r3,:64]! @ K[i++]
508 #if 1<16 && defined(__ARMEL__)
512 vbsl d29,d20,d21 @ Ch(e,f,g)
514 veor d26,d25 @ Sigma1(e)
526 vbsl d30,d17,d16 @ Maj(a,b,c)
527 veor d22,d26 @ Sigma0(a)
531 vshr.u64 d24,d18,#14 @ 2
533 vld1.64 {d2},[r1]! @ handles unaligned
537 vadd.i64 d22,d30 @ h+=Maj from the past
540 vld1.64 {d28},[r3,:64]! @ K[i++]
545 #if 2<16 && defined(__ARMEL__)
549 vbsl d29,d19,d20 @ Ch(e,f,g)
551 veor d26,d25 @ Sigma1(e)
563 vbsl d30,d16,d23 @ Maj(a,b,c)
564 veor d21,d26 @ Sigma0(a)
568 vshr.u64 d24,d17,#14 @ 3
570 vld1.64 {d3},[r1]! @ handles unaligned
574 vadd.i64 d21,d30 @ h+=Maj from the past
577 vld1.64 {d28},[r3,:64]! @ K[i++]
582 #if 3<16 && defined(__ARMEL__)
586 vbsl d29,d18,d19 @ Ch(e,f,g)
588 veor d26,d25 @ Sigma1(e)
600 vbsl d30,d23,d22 @ Maj(a,b,c)
601 veor d20,d26 @ Sigma0(a)
605 vshr.u64 d24,d16,#14 @ 4
607 vld1.64 {d4},[r1]! @ handles unaligned
611 vadd.i64 d20,d30 @ h+=Maj from the past
614 vld1.64 {d28},[r3,:64]! @ K[i++]
619 #if 4<16 && defined(__ARMEL__)
623 vbsl d29,d17,d18 @ Ch(e,f,g)
625 veor d26,d25 @ Sigma1(e)
637 vbsl d30,d22,d21 @ Maj(a,b,c)
638 veor d19,d26 @ Sigma0(a)
642 vshr.u64 d24,d23,#14 @ 5
644 vld1.64 {d5},[r1]! @ handles unaligned
648 vadd.i64 d19,d30 @ h+=Maj from the past
651 vld1.64 {d28},[r3,:64]! @ K[i++]
656 #if 5<16 && defined(__ARMEL__)
660 vbsl d29,d16,d17 @ Ch(e,f,g)
662 veor d26,d25 @ Sigma1(e)
674 vbsl d30,d21,d20 @ Maj(a,b,c)
675 veor d18,d26 @ Sigma0(a)
679 vshr.u64 d24,d22,#14 @ 6
681 vld1.64 {d6},[r1]! @ handles unaligned
685 vadd.i64 d18,d30 @ h+=Maj from the past
688 vld1.64 {d28},[r3,:64]! @ K[i++]
693 #if 6<16 && defined(__ARMEL__)
697 vbsl d29,d23,d16 @ Ch(e,f,g)
699 veor d26,d25 @ Sigma1(e)
711 vbsl d30,d20,d19 @ Maj(a,b,c)
712 veor d17,d26 @ Sigma0(a)
716 vshr.u64 d24,d21,#14 @ 7
718 vld1.64 {d7},[r1]! @ handles unaligned
722 vadd.i64 d17,d30 @ h+=Maj from the past
725 vld1.64 {d28},[r3,:64]! @ K[i++]
730 #if 7<16 && defined(__ARMEL__)
734 vbsl d29,d22,d23 @ Ch(e,f,g)
736 veor d26,d25 @ Sigma1(e)
748 vbsl d30,d19,d18 @ Maj(a,b,c)
749 veor d16,d26 @ Sigma0(a)
753 vshr.u64 d24,d20,#14 @ 8
755 vld1.64 {d8},[r1]! @ handles unaligned
759 vadd.i64 d16,d30 @ h+=Maj from the past
762 vld1.64 {d28},[r3,:64]! @ K[i++]
767 #if 8<16 && defined(__ARMEL__)
771 vbsl d29,d21,d22 @ Ch(e,f,g)
773 veor d26,d25 @ Sigma1(e)
785 vbsl d30,d18,d17 @ Maj(a,b,c)
786 veor d23,d26 @ Sigma0(a)
790 vshr.u64 d24,d19,#14 @ 9
792 vld1.64 {d9},[r1]! @ handles unaligned
796 vadd.i64 d23,d30 @ h+=Maj from the past
799 vld1.64 {d28},[r3,:64]! @ K[i++]
804 #if 9<16 && defined(__ARMEL__)
808 vbsl d29,d20,d21 @ Ch(e,f,g)
810 veor d26,d25 @ Sigma1(e)
822 vbsl d30,d17,d16 @ Maj(a,b,c)
823 veor d22,d26 @ Sigma0(a)
827 vshr.u64 d24,d18,#14 @ 10
829 vld1.64 {d10},[r1]! @ handles unaligned
833 vadd.i64 d22,d30 @ h+=Maj from the past
836 vld1.64 {d28},[r3,:64]! @ K[i++]
841 #if 10<16 && defined(__ARMEL__)
845 vbsl d29,d19,d20 @ Ch(e,f,g)
847 veor d26,d25 @ Sigma1(e)
859 vbsl d30,d16,d23 @ Maj(a,b,c)
860 veor d21,d26 @ Sigma0(a)
864 vshr.u64 d24,d17,#14 @ 11
866 vld1.64 {d11},[r1]! @ handles unaligned
870 vadd.i64 d21,d30 @ h+=Maj from the past
873 vld1.64 {d28},[r3,:64]! @ K[i++]
878 #if 11<16 && defined(__ARMEL__)
882 vbsl d29,d18,d19 @ Ch(e,f,g)
884 veor d26,d25 @ Sigma1(e)
896 vbsl d30,d23,d22 @ Maj(a,b,c)
897 veor d20,d26 @ Sigma0(a)
901 vshr.u64 d24,d16,#14 @ 12
903 vld1.64 {d12},[r1]! @ handles unaligned
907 vadd.i64 d20,d30 @ h+=Maj from the past
910 vld1.64 {d28},[r3,:64]! @ K[i++]
915 #if 12<16 && defined(__ARMEL__)
919 vbsl d29,d17,d18 @ Ch(e,f,g)
921 veor d26,d25 @ Sigma1(e)
933 vbsl d30,d22,d21 @ Maj(a,b,c)
934 veor d19,d26 @ Sigma0(a)
938 vshr.u64 d24,d23,#14 @ 13
940 vld1.64 {d13},[r1]! @ handles unaligned
944 vadd.i64 d19,d30 @ h+=Maj from the past
947 vld1.64 {d28},[r3,:64]! @ K[i++]
952 #if 13<16 && defined(__ARMEL__)
956 vbsl d29,d16,d17 @ Ch(e,f,g)
958 veor d26,d25 @ Sigma1(e)
970 vbsl d30,d21,d20 @ Maj(a,b,c)
971 veor d18,d26 @ Sigma0(a)
975 vshr.u64 d24,d22,#14 @ 14
977 vld1.64 {d14},[r1]! @ handles unaligned
981 vadd.i64 d18,d30 @ h+=Maj from the past
984 vld1.64 {d28},[r3,:64]! @ K[i++]
989 #if 14<16 && defined(__ARMEL__)
993 vbsl d29,d23,d16 @ Ch(e,f,g)
995 veor d26,d25 @ Sigma1(e)
1000 vshr.u64 d26,d18,#39
1007 vbsl d30,d20,d19 @ Maj(a,b,c)
1008 veor d17,d26 @ Sigma0(a)
1012 vshr.u64 d24,d21,#14 @ 15
1014 vld1.64 {d15},[r1]! @ handles unaligned
1016 vshr.u64 d25,d21,#18
1018 vadd.i64 d17,d30 @ h+=Maj from the past
1020 vshr.u64 d26,d21,#41
1021 vld1.64 {d28},[r3,:64]! @ K[i++]
1026 #if 15<16 && defined(__ARMEL__)
1030 vbsl d29,d22,d23 @ Ch(e,f,g)
1031 vshr.u64 d24,d17,#28
1032 veor d26,d25 @ Sigma1(e)
1033 vadd.i64 d27,d29,d16
1034 vshr.u64 d25,d17,#34
1037 vshr.u64 d26,d17,#39
1044 vbsl d30,d19,d18 @ Maj(a,b,c)
1045 veor d16,d26 @ Sigma0(a)
1054 vadd.i64 d16,d30 @ h+=Maj from the past
1057 vext.8 q14,q0,q1,#8 @ X[i+1]
1061 veor q15,q13 @ sigma1(X[i+14])
1067 vext.8 q14,q4,q5,#8 @ X[i+9]
1069 vshr.u64 d24,d20,#14 @ from NEON_00_15
1071 vshr.u64 d25,d20,#18 @ from NEON_00_15
1072 veor q15,q13 @ sigma0(X[i+1])
1073 vshr.u64 d26,d20,#41 @ from NEON_00_15
1075 vld1.64 {d28},[r3,:64]! @ K[i++]
1080 #if 16<16 && defined(__ARMEL__)
1084 vbsl d29,d21,d22 @ Ch(e,f,g)
1085 vshr.u64 d24,d16,#28
1086 veor d26,d25 @ Sigma1(e)
1087 vadd.i64 d27,d29,d23
1088 vshr.u64 d25,d16,#34
1091 vshr.u64 d26,d16,#39
1098 vbsl d30,d18,d17 @ Maj(a,b,c)
1099 veor d23,d26 @ Sigma0(a)
1103 vshr.u64 d24,d19,#14 @ 17
1105 vld1.64 {d1},[r1]! @ handles unaligned
1107 vshr.u64 d25,d19,#18
1109 vadd.i64 d23,d30 @ h+=Maj from the past
1111 vshr.u64 d26,d19,#41
1112 vld1.64 {d28},[r3,:64]! @ K[i++]
1117 #if 17<16 && defined(__ARMEL__)
1121 vbsl d29,d20,d21 @ Ch(e,f,g)
1122 vshr.u64 d24,d23,#28
1123 veor d26,d25 @ Sigma1(e)
1124 vadd.i64 d27,d29,d22
1125 vshr.u64 d25,d23,#34
1128 vshr.u64 d26,d23,#39
1135 vbsl d30,d17,d16 @ Maj(a,b,c)
1136 veor d22,d26 @ Sigma0(a)
1142 vadd.i64 d22,d30 @ h+=Maj from the past
1145 vext.8 q14,q1,q2,#8 @ X[i+1]
1149 veor q15,q13 @ sigma1(X[i+14])
1155 vext.8 q14,q5,q6,#8 @ X[i+9]
1157 vshr.u64 d24,d18,#14 @ from NEON_00_15
1159 vshr.u64 d25,d18,#18 @ from NEON_00_15
1160 veor q15,q13 @ sigma0(X[i+1])
1161 vshr.u64 d26,d18,#41 @ from NEON_00_15
1163 vld1.64 {d28},[r3,:64]! @ K[i++]
1168 #if 18<16 && defined(__ARMEL__)
1172 vbsl d29,d19,d20 @ Ch(e,f,g)
1173 vshr.u64 d24,d22,#28
1174 veor d26,d25 @ Sigma1(e)
1175 vadd.i64 d27,d29,d21
1176 vshr.u64 d25,d22,#34
1179 vshr.u64 d26,d22,#39
1186 vbsl d30,d16,d23 @ Maj(a,b,c)
1187 veor d21,d26 @ Sigma0(a)
1191 vshr.u64 d24,d17,#14 @ 19
1193 vld1.64 {d3},[r1]! @ handles unaligned
1195 vshr.u64 d25,d17,#18
1197 vadd.i64 d21,d30 @ h+=Maj from the past
1199 vshr.u64 d26,d17,#41
1200 vld1.64 {d28},[r3,:64]! @ K[i++]
1205 #if 19<16 && defined(__ARMEL__)
1209 vbsl d29,d18,d19 @ Ch(e,f,g)
1210 vshr.u64 d24,d21,#28
1211 veor d26,d25 @ Sigma1(e)
1212 vadd.i64 d27,d29,d20
1213 vshr.u64 d25,d21,#34
1216 vshr.u64 d26,d21,#39
1223 vbsl d30,d23,d22 @ Maj(a,b,c)
1224 veor d20,d26 @ Sigma0(a)
1230 vadd.i64 d20,d30 @ h+=Maj from the past
1233 vext.8 q14,q2,q3,#8 @ X[i+1]
1237 veor q15,q13 @ sigma1(X[i+14])
1243 vext.8 q14,q6,q7,#8 @ X[i+9]
1245 vshr.u64 d24,d16,#14 @ from NEON_00_15
1247 vshr.u64 d25,d16,#18 @ from NEON_00_15
1248 veor q15,q13 @ sigma0(X[i+1])
1249 vshr.u64 d26,d16,#41 @ from NEON_00_15
1251 vld1.64 {d28},[r3,:64]! @ K[i++]
1256 #if 20<16 && defined(__ARMEL__)
1260 vbsl d29,d17,d18 @ Ch(e,f,g)
1261 vshr.u64 d24,d20,#28
1262 veor d26,d25 @ Sigma1(e)
1263 vadd.i64 d27,d29,d19
1264 vshr.u64 d25,d20,#34
1267 vshr.u64 d26,d20,#39
1274 vbsl d30,d22,d21 @ Maj(a,b,c)
1275 veor d19,d26 @ Sigma0(a)
1279 vshr.u64 d24,d23,#14 @ 21
1281 vld1.64 {d5},[r1]! @ handles unaligned
1283 vshr.u64 d25,d23,#18
1285 vadd.i64 d19,d30 @ h+=Maj from the past
1287 vshr.u64 d26,d23,#41
1288 vld1.64 {d28},[r3,:64]! @ K[i++]
1293 #if 21<16 && defined(__ARMEL__)
1297 vbsl d29,d16,d17 @ Ch(e,f,g)
1298 vshr.u64 d24,d19,#28
1299 veor d26,d25 @ Sigma1(e)
1300 vadd.i64 d27,d29,d18
1301 vshr.u64 d25,d19,#34
1304 vshr.u64 d26,d19,#39
1311 vbsl d30,d21,d20 @ Maj(a,b,c)
1312 veor d18,d26 @ Sigma0(a)
1318 vadd.i64 d18,d30 @ h+=Maj from the past
1321 vext.8 q14,q3,q4,#8 @ X[i+1]
1325 veor q15,q13 @ sigma1(X[i+14])
1331 vext.8 q14,q7,q0,#8 @ X[i+9]
1333 vshr.u64 d24,d22,#14 @ from NEON_00_15
1335 vshr.u64 d25,d22,#18 @ from NEON_00_15
1336 veor q15,q13 @ sigma0(X[i+1])
1337 vshr.u64 d26,d22,#41 @ from NEON_00_15
1339 vld1.64 {d28},[r3,:64]! @ K[i++]
1344 #if 22<16 && defined(__ARMEL__)
1348 vbsl d29,d23,d16 @ Ch(e,f,g)
1349 vshr.u64 d24,d18,#28
1350 veor d26,d25 @ Sigma1(e)
1351 vadd.i64 d27,d29,d17
1352 vshr.u64 d25,d18,#34
1355 vshr.u64 d26,d18,#39
1362 vbsl d30,d20,d19 @ Maj(a,b,c)
1363 veor d17,d26 @ Sigma0(a)
1367 vshr.u64 d24,d21,#14 @ 23
1369 vld1.64 {d7},[r1]! @ handles unaligned
1371 vshr.u64 d25,d21,#18
1373 vadd.i64 d17,d30 @ h+=Maj from the past
1375 vshr.u64 d26,d21,#41
1376 vld1.64 {d28},[r3,:64]! @ K[i++]
1381 #if 23<16 && defined(__ARMEL__)
1385 vbsl d29,d22,d23 @ Ch(e,f,g)
1386 vshr.u64 d24,d17,#28
1387 veor d26,d25 @ Sigma1(e)
1388 vadd.i64 d27,d29,d16
1389 vshr.u64 d25,d17,#34
1392 vshr.u64 d26,d17,#39
1399 vbsl d30,d19,d18 @ Maj(a,b,c)
1400 veor d16,d26 @ Sigma0(a)
1406 vadd.i64 d16,d30 @ h+=Maj from the past
1409 vext.8 q14,q4,q5,#8 @ X[i+1]
1413 veor q15,q13 @ sigma1(X[i+14])
1419 vext.8 q14,q0,q1,#8 @ X[i+9]
1421 vshr.u64 d24,d20,#14 @ from NEON_00_15
1423 vshr.u64 d25,d20,#18 @ from NEON_00_15
1424 veor q15,q13 @ sigma0(X[i+1])
1425 vshr.u64 d26,d20,#41 @ from NEON_00_15
1427 vld1.64 {d28},[r3,:64]! @ K[i++]
1432 #if 24<16 && defined(__ARMEL__)
1436 vbsl d29,d21,d22 @ Ch(e,f,g)
1437 vshr.u64 d24,d16,#28
1438 veor d26,d25 @ Sigma1(e)
1439 vadd.i64 d27,d29,d23
1440 vshr.u64 d25,d16,#34
1443 vshr.u64 d26,d16,#39
1450 vbsl d30,d18,d17 @ Maj(a,b,c)
1451 veor d23,d26 @ Sigma0(a)
1455 vshr.u64 d24,d19,#14 @ 25
1457 vld1.64 {d9},[r1]! @ handles unaligned
1459 vshr.u64 d25,d19,#18
1461 vadd.i64 d23,d30 @ h+=Maj from the past
1463 vshr.u64 d26,d19,#41
1464 vld1.64 {d28},[r3,:64]! @ K[i++]
1469 #if 25<16 && defined(__ARMEL__)
1473 vbsl d29,d20,d21 @ Ch(e,f,g)
1474 vshr.u64 d24,d23,#28
1475 veor d26,d25 @ Sigma1(e)
1476 vadd.i64 d27,d29,d22
1477 vshr.u64 d25,d23,#34
1480 vshr.u64 d26,d23,#39
1487 vbsl d30,d17,d16 @ Maj(a,b,c)
1488 veor d22,d26 @ Sigma0(a)
1494 vadd.i64 d22,d30 @ h+=Maj from the past
1497 vext.8 q14,q5,q6,#8 @ X[i+1]
1501 veor q15,q13 @ sigma1(X[i+14])
1507 vext.8 q14,q1,q2,#8 @ X[i+9]
1509 vshr.u64 d24,d18,#14 @ from NEON_00_15
1511 vshr.u64 d25,d18,#18 @ from NEON_00_15
1512 veor q15,q13 @ sigma0(X[i+1])
1513 vshr.u64 d26,d18,#41 @ from NEON_00_15
1515 vld1.64 {d28},[r3,:64]! @ K[i++]
1520 #if 26<16 && defined(__ARMEL__)
1524 vbsl d29,d19,d20 @ Ch(e,f,g)
1525 vshr.u64 d24,d22,#28
1526 veor d26,d25 @ Sigma1(e)
1527 vadd.i64 d27,d29,d21
1528 vshr.u64 d25,d22,#34
1531 vshr.u64 d26,d22,#39
1538 vbsl d30,d16,d23 @ Maj(a,b,c)
1539 veor d21,d26 @ Sigma0(a)
1543 vshr.u64 d24,d17,#14 @ 27
1545 vld1.64 {d11},[r1]! @ handles unaligned
1547 vshr.u64 d25,d17,#18
1549 vadd.i64 d21,d30 @ h+=Maj from the past
1551 vshr.u64 d26,d17,#41
1552 vld1.64 {d28},[r3,:64]! @ K[i++]
1557 #if 27<16 && defined(__ARMEL__)
1561 vbsl d29,d18,d19 @ Ch(e,f,g)
1562 vshr.u64 d24,d21,#28
1563 veor d26,d25 @ Sigma1(e)
1564 vadd.i64 d27,d29,d20
1565 vshr.u64 d25,d21,#34
1568 vshr.u64 d26,d21,#39
1575 vbsl d30,d23,d22 @ Maj(a,b,c)
1576 veor d20,d26 @ Sigma0(a)
1582 vadd.i64 d20,d30 @ h+=Maj from the past
1585 vext.8 q14,q6,q7,#8 @ X[i+1]
1589 veor q15,q13 @ sigma1(X[i+14])
1595 vext.8 q14,q2,q3,#8 @ X[i+9]
1597 vshr.u64 d24,d16,#14 @ from NEON_00_15
1599 vshr.u64 d25,d16,#18 @ from NEON_00_15
1600 veor q15,q13 @ sigma0(X[i+1])
1601 vshr.u64 d26,d16,#41 @ from NEON_00_15
1603 vld1.64 {d28},[r3,:64]! @ K[i++]
1608 #if 28<16 && defined(__ARMEL__)
1612 vbsl d29,d17,d18 @ Ch(e,f,g)
1613 vshr.u64 d24,d20,#28
1614 veor d26,d25 @ Sigma1(e)
1615 vadd.i64 d27,d29,d19
1616 vshr.u64 d25,d20,#34
1619 vshr.u64 d26,d20,#39
1626 vbsl d30,d22,d21 @ Maj(a,b,c)
1627 veor d19,d26 @ Sigma0(a)
1631 vshr.u64 d24,d23,#14 @ 29
1633 vld1.64 {d13},[r1]! @ handles unaligned
1635 vshr.u64 d25,d23,#18
1637 vadd.i64 d19,d30 @ h+=Maj from the past
1639 vshr.u64 d26,d23,#41
1640 vld1.64 {d28},[r3,:64]! @ K[i++]
1645 #if 29<16 && defined(__ARMEL__)
1649 vbsl d29,d16,d17 @ Ch(e,f,g)
1650 vshr.u64 d24,d19,#28
1651 veor d26,d25 @ Sigma1(e)
1652 vadd.i64 d27,d29,d18
1653 vshr.u64 d25,d19,#34
1656 vshr.u64 d26,d19,#39
1663 vbsl d30,d21,d20 @ Maj(a,b,c)
1664 veor d18,d26 @ Sigma0(a)
1670 vadd.i64 d18,d30 @ h+=Maj from the past
1673 vext.8 q14,q7,q0,#8 @ X[i+1]
1677 veor q15,q13 @ sigma1(X[i+14])
1683 vext.8 q14,q3,q4,#8 @ X[i+9]
1685 vshr.u64 d24,d22,#14 @ from NEON_00_15
1687 vshr.u64 d25,d22,#18 @ from NEON_00_15
1688 veor q15,q13 @ sigma0(X[i+1])
1689 vshr.u64 d26,d22,#41 @ from NEON_00_15
1691 vld1.64 {d28},[r3,:64]! @ K[i++]
1696 #if 30<16 && defined(__ARMEL__)
1700 vbsl d29,d23,d16 @ Ch(e,f,g)
1701 vshr.u64 d24,d18,#28
1702 veor d26,d25 @ Sigma1(e)
1703 vadd.i64 d27,d29,d17
1704 vshr.u64 d25,d18,#34
1707 vshr.u64 d26,d18,#39
1714 vbsl d30,d20,d19 @ Maj(a,b,c)
1715 veor d17,d26 @ Sigma0(a)
1719 vshr.u64 d24,d21,#14 @ 31
1721 vld1.64 {d15},[r1]! @ handles unaligned
1723 vshr.u64 d25,d21,#18
1725 vadd.i64 d17,d30 @ h+=Maj from the past
1727 vshr.u64 d26,d21,#41
1728 vld1.64 {d28},[r3,:64]! @ K[i++]
1733 #if 31<16 && defined(__ARMEL__)
1737 vbsl d29,d22,d23 @ Ch(e,f,g)
1738 vshr.u64 d24,d17,#28
1739 veor d26,d25 @ Sigma1(e)
1740 vadd.i64 d27,d29,d16
1741 vshr.u64 d25,d17,#34
1744 vshr.u64 d26,d17,#39
1751 vbsl d30,d19,d18 @ Maj(a,b,c)
1752 veor d16,d26 @ Sigma0(a)
1758 vadd.i64 d16,d30 @ h+=Maj from the past
1759 vldmia r0,{d24-d31} @ load context to temp
1760 vadd.i64 q8,q12 @ vectorized accumulate
1764 vstmia r0,{d16-d23} @ save context
1766 sub r3,#640 @ rewind K512
1769 vldmia sp!,{d8-d15} @ epilogue
1770 bx lr @ .word 0xe12fff1e
1772 .size sha512_block_data_order,.-sha512_block_data_order
1773 .asciz "SHA512 block transform for ARMv4/NEON, CRYPTOGAMS by <appro@openssl.org>"
1775 #if __ARM_MAX_ARCH__>=7
1776 .comm OPENSSL_armcap_P,4,4