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3 .\" Justin T. Gibbs. All rights reserved.
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34 .Nd Adaptec VL/EISA/PCI SCSI host adapter driver
36 For one or more VL/EISA cards:
40 For one or more PCI cards:
44 To allow PCI adapters to use memory mapped I/O if enabled:
45 .Cd options AHC_ALLOW_MEMIO
47 For one or more SCSI busses:
48 .Cd controller scbus0 at ahc0
50 This driver provides access to the
52 bus(es) connected to Adaptec
65 These chips are found on many motherboards as well as the following
66 Adaptec SCSI controller cards:
91 Driver features include support for twin and wide busses,
92 fast, ultra and ultra2 synchronous transfers depending on controller type,
96 Memory mapped I/O can be enabled for PCI devices with the
97 .Dq Dv AHC_ALLOW_MEMIO
99 Memory mapped I/O is more efficient than the alternative, programmed I/O.
100 Most PCI BIOSes will map devices so that either technique for communicating
101 with the card is available.
103 usually when the PCI device is sitting behind a PCI->PCI bridge,
104 the BIOS fails to properly initialize the chip for memory mapped I/O.
105 The symptom of this problem is usually a system hang if memory mapped I/O
107 Most modern motherboards perform the initialization correctly and work fine
108 with this option enabled.
110 Per target configuration performed in the
112 menu, accessible at boot
118 configuration utility for
121 is honored by this driver with the stipulation that the
125 adaptors. This includes synchronous/asynchronous transfers,
126 maximum synchronous negotiation rate,
128 the host adapter's SCSI ID,
132 Twin Channel controllers,
133 the primary channel selection.
135 Note that I/O addresses are determined automatically by the probe routines,
136 but care should be taken when using a 284x
137 .Pq Tn VESA No local bus controller
140 system. Ensure that the jumpers setting the I/O area for the 284x match the
142 slot into which the card is inserted to prevent conflicts with other
146 Performance and feature sets vary throughout the aic7xxx product line.
147 The following table provides a comparison of the different chips supported
150 driver. Note that wide and twin channel features, although always supported
151 by a particular chip, may be disabled in a particular motherboard or card
154 .Bd -filled -offset indent
155 .Bl -column "aic7770 " "10 " "EISA/VL " "10MHz " "16bit " "SCBs " Features
156 .Em "Chip MIPS Bus MaxSync MaxWidth SCBs Features"
157 aic7770 10 EISA/VL 10MHz 16Bit 4 1
158 aic7850 10 PCI/32 10MHz 8Bit 3
159 aic7860 10 PCI/32 20MHz 8Bit 3
160 aic7870 10 PCI/32 10MHz 16Bit 16
161 aic7880 10 PCI/32 20MHz 16Bit 16
162 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7
163 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7
164 aic7895 15 PCI/32 20MHz 16Bit 16 2 3 4 5
165 aic7896 20 PCI/32 40MHz 16Bit 16 2 3 4 5 6 7
166 aic7897 20 PCI/64 40MHz 16Bit 16 2 3 4 5 6 7
171 Multiplexed Twin Channel Device - One controller servicing two busses.
173 Multi-function Twin Channel Device - Two controllers on one chip.
175 Command Channel Secondary DMA Engine - Allows scatter gather list and
178 64 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA.
180 Block Move Instruction Support - Doubles the speed of certain sequencer
184 style Scatter Gather Engine - Improves S/G prefetch performance.
186 Queuing Registers - Allows queuing of new transactions without pausing the
192 .Sh SCSI CONTROL BLOCKS (SCBs)
193 Every transaction sent to a device on the SCSI bus is assigned a
194 .Sq SCSI Control Block
195 (SCB). The SCB contains all of the information required by the
196 controller to process a transaction. The chip feature table lists
197 the number of SCBs that can be stored in on chip memory. All chips
198 with model numbers greater than or equal to 7870 allow for the on chip
199 SCB space to be augmented with external SRAM up to a maximum of 255 SCBs.
200 Very few Adaptec controller have external SRAM.
202 If external SRAM is not available, SCBs are a limited resource and
203 using them in a straight forward manner would only allow us to
204 keep as many transactions as there are SCBs outstanding at a time.
205 This would not allow enough concurrency to fully utilize the SCSI
206 bus and it's devices. The solution to this problem is
208 a concept similar to memory paging. SCB paging takes advantage of
209 the fact that devices usually disconnect from the SCSI bus for long
210 periods of time without talking to the controller. The SCBs
211 for disconnected transactions are only of use to the controller
212 when the transfer is resumed. When the host queues another transaction
213 for the controller to execute, the controller firmware will use a
214 free SCB if one is available. Otherwise, the state of the most recently
215 disconnected (and therefor most likely to stay disconnected) SCB is
216 saved, via dma, to host memory, and the local SCB reused to start
217 the new transaction. This allows the controller to queue up to
218 255 transactions regardless of the amount of SCB space. Since the
219 local SCB space serves as a cache for disconnected transactions, the
220 more SCB space available, the less host bus traffic consumed saving
221 and restoring SCB data.
223 Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an
225 Rev B in synchronous mode at 10MHz. Controllers with this problem have a
226 42 MHz clock crystal on them and run slightly above 10MHz. This confuses
227 the drive and hangs the bus. Setting a maximum synchronous negotiation rate
231 will allow normal operation.
244 sequencer-code assembler,
245 and the firmware running on the aic7xxx chips was written by
246 .An Justin T. Gibbs .