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34 .Nd Adaptec VL/ISA/PCI SCSI host adapter driver
36 To compile this driver into the kernel,
37 place the following lines in your
38 kernel configuration file:
39 .Bd -ragged -offset indent
43 For one or more PCI cards:
46 To allow PCI adapters to use memory mapped I/O if enabled:
47 .Cd options AHC_ALLOW_MEMIO
49 To configure one or more controllers to assume the target role:
50 .Cd options AHC_TMODE_ENABLE <bitmask of units>
53 Alternatively, to load the driver as a
54 module at boot time, place the following lines in
56 .Bd -literal -offset indent
62 This driver provides access to the
64 bus(es) connected to the Adaptec AIC77xx and AIC78xx
67 Driver features include support for twin and wide busses,
68 fast, ultra or ultra2 synchronous transfers depending on controller type,
69 tagged queueing, SCB paging, and target mode.
71 Memory mapped I/O can be enabled for PCI devices with the
72 .Dq Dv AHC_ALLOW_MEMIO
74 Memory mapped I/O is more efficient than the alternative, programmed I/O.
75 Most PCI BIOSes will map devices so that either technique for communicating
76 with the card is available.
78 usually when the PCI device is sitting behind a PCI->PCI bridge,
79 the BIOS may fail to properly initialize the chip for memory mapped I/O.
80 The typical symptom of this problem is a system hang if memory mapped I/O
82 Most modern motherboards perform the initialization correctly and work fine
83 with this option enabled.
85 Individual controllers may be configured to operate in the target role
87 .Dq Dv AHC_TMODE_ENABLE
89 The value assigned to this option should be a bitmap
90 of all units where target mode is desired.
91 For example, a value of 0x25, would enable target mode on units 0, 2, and 5.
92 A value of 0x8a enables it for units 1, 3, and 7.
94 Per target configuration performed in the
96 menu, accessible at boot
97 is honored by this driver.
98 This includes synchronous/asynchronous transfers,
99 maximum synchronous negotiation rate,
102 the host adapter's SCSI ID.
103 For systems that store non-volatile settings in a system specific manner
104 rather than a serial eeprom directly connected to the aic7xxx controller,
107 must be enabled for the driver to access this information.
108 This restriction applies to
109 many chip-down motherboard configurations.
111 Performance and feature sets vary throughout the aic7xxx product line.
112 The following table provides a comparison of the different chips supported
116 Note that wide and twin channel features, although always supported
117 by a particular chip, may be disabled in a particular motherboard or card
119 .Bd -ragged -offset indent
120 .Bl -column "aic7895CX" "MIPSX" "PCI/64X" "MaxSyncX" "MaxWidthX" "SCBsX" "2 3 4 5 6 7 8X"
121 .It Em "Chip" Ta "MIPS" Ta "Bus" Ta "MaxSync" Ta "MaxWidth" Ta "SCBs" Ta "Features"
122 .It "aic7770" Ta "10" Ta "VL" Ta "10MHz" Ta "16Bit" Ta "4" Ta "1"
123 .It "aic7850" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "8Bit" Ta "3" Ta ""
124 .It "aic7860" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "8Bit" Ta "3" Ta ""
125 .It "aic7870" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "16Bit" Ta "16" Ta ""
126 .It "aic7880" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta ""
127 .It "aic7890" Ta "20" Ta "PCI/32" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
128 .It "aic7891" Ta "20" Ta "PCI/64" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
129 .It "aic7892" Ta "20" Ta "PCI/64" Ta "80MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
130 .It "aic7895" Ta "15" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5"
131 .It "aic7895C" Ta "15" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 8"
132 .It "aic7896" Ta "20" Ta "PCI/32" Ta "40MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 6 7 8"
133 .It "aic7897" Ta "20" Ta "PCI/64" Ta "40MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 6 7 8"
134 .It "aic7899" Ta "20" Ta "PCI/64" Ta "80MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 6 7 8"
139 Multiplexed Twin Channel Device - One controller servicing two busses.
141 Multi-function Twin Channel Device - Two controllers on one chip.
143 Command Channel Secondary DMA Engine - Allows scatter gather list and
146 64 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA.
148 Block Move Instruction Support - Doubles the speed of certain sequencer
152 style Scatter Gather Engine - Improves S/G prefetch performance.
154 Queuing Registers - Allows queueing of new transactions without pausing the
157 Multiple Target IDs - Allows the controller to respond to selection as a
158 target on multiple SCSI IDs.
164 driver supports the following
166 host adapter chips and
319 Many motherboards with on-board
323 .Sh SCSI CONTROL BLOCKS (SCBs)
324 Every transaction sent to a device on the SCSI bus is assigned a
325 .Sq SCSI Control Block
327 The SCB contains all of the information required by the
328 controller to process a transaction.
329 The chip feature table lists
330 the number of SCBs that can be stored in on-chip memory.
332 with model numbers greater than or equal to 7870 allow for the on chip
333 SCB space to be augmented with external SRAM up to a maximum of 255 SCBs.
334 Very few Adaptec controller configurations have external SRAM.
336 If external SRAM is not available, SCBs are a limited resource.
337 Using the SCBs in a straight forward manner would only allow the driver to
338 handle as many concurrent transactions as there are physical SCBs.
339 To fully utilize the SCSI bus and the devices on it,
340 requires much more concurrency.
341 The solution to this problem is
343 a concept similar to memory paging.
344 SCB paging takes advantage of
345 the fact that devices usually disconnect from the SCSI bus for long
346 periods of time without talking to the controller.
347 The SCBs for disconnected transactions are only of use to the controller
348 when the transfer is resumed.
349 When the host queues another transaction
350 for the controller to execute, the controller firmware will use a
351 free SCB if one is available.
352 Otherwise, the state of the most recently
353 disconnected (and therefore most likely to stay disconnected) SCB is
354 saved, via dma, to host memory, and the local SCB reused to start
356 This allows the controller to queue up to
357 255 transactions regardless of the amount of SCB space.
359 local SCB space serves as a cache for disconnected transactions, the
360 more SCB space available, the less host bus traffic consumed saving
361 and restoring SCB data.
378 sequencer-code assembler,
379 and the firmware running on the aic7xxx chips was written by
380 .An Justin T. Gibbs .
382 Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an
384 Rev B in synchronous mode at 10MHz.
385 Controllers with this problem have a
386 42 MHz clock crystal on them and run slightly above 10MHz.
387 This confuses the drive and hangs the bus.
388 Setting a maximum synchronous negotiation rate of 8MHz in the
390 utility will allow normal operation.
392 Although the Ultra2 and Ultra160 products have sufficient instruction
393 ram space to support both the initiator and target roles concurrently,
394 this configuration is disabled in favor of allowing the target role
395 to respond on multiple target ids.
396 A method for configuring dual role mode should be provided.
398 Tagged Queuing is not supported in target mode.
400 Reselection in target mode fails to function correctly on all high
401 voltage differential boards as shipped by Adaptec.
403 how to modify HVD board to work correctly in target mode is available