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34 .Nd Adaptec VL/EISA/PCI SCSI host adapter driver
36 For one or more VL/EISA cards:
40 For one or more PCI cards:
44 To allow PCI adapters to use memory mapped I/O if enabled:
45 .Cd options AHC_ALLOW_MEMIO
47 To configure one or more controllers to assume the target role:
48 .Cd options AHC_TMODE_ENABLE <bitmask of units>
50 For one or more SCSI busses:
53 This driver provides access to the
55 bus(es) connected to the Adaptec AIC77xx and AIC78xx
58 Driver features include support for twin and wide busses,
59 fast, ultra or ultra2 synchronous transfers depending on controller type,
60 tagged queueing, SCB paging, and target mode.
62 Memory mapped I/O can be enabled for PCI devices with the
63 .Dq Dv AHC_ALLOW_MEMIO
65 Memory mapped I/O is more efficient than the alternative, programmed I/O.
66 Most PCI BIOSes will map devices so that either technique for communicating
67 with the card is available.
69 usually when the PCI device is sitting behind a PCI->PCI bridge,
70 the BIOS may fail to properly initialize the chip for memory mapped I/O.
71 The typical symptom of this problem is a system hang if memory mapped I/O
73 Most modern motherboards perform the initialization correctly and work fine
74 with this option enabled.
76 Individual controllers may be configured to operate in the target role
78 .Dq Dv AHC_TMODE_ENABLE
80 The value assigned to this option should be a bitmap
81 of all units where target mode is desired.
82 For example, a value of 0x25, would enable target mode on units 0, 2, and 5.
83 A value of 0x8a enables it for units 1, 3, and 7.
85 Per target configuration performed in the
87 menu, accessible at boot
93 configuration utility for
96 is honored by this driver.
97 This includes synchronous/asynchronous transfers,
98 maximum synchronous negotiation rate,
101 the host adapter's SCSI ID,
105 Twin Channel controllers,
106 the primary channel selection.
107 For systems that store non-volatile settings in a system specific manner
108 rather than a serial eeprom directly connected to the aic7xxx controller,
111 must be enabled for the driver to access this information.
112 This restriction applies to all
114 and many motherboard configurations.
116 Note that I/O addresses are determined automatically by the probe routines,
117 but care should be taken when using a 284x
118 .Pq Tn VESA No local bus controller
122 The jumpers setting the I/O area for the 284x should match the
124 slot into which the card is inserted to prevent conflicts with other
128 Performance and feature sets vary throughout the aic7xxx product line.
129 The following table provides a comparison of the different chips supported
133 Note that wide and twin channel features, although always supported
134 by a particular chip, may be disabled in a particular motherboard or card
137 .Bd -ragged -offset indent
138 .Bl -column "aic7770 " "10 " "EISA/VL " "10MHz " "16bit " "SCBs " Features
139 .Em "Chip MIPS Bus MaxSync MaxWidth SCBs Features"
140 aic7770 10 EISA/VL 10MHz 16Bit 4 1
141 aic7850 10 PCI/32 10MHz 8Bit 3
142 aic7860 10 PCI/32 20MHz 8Bit 3
143 aic7870 10 PCI/32 10MHz 16Bit 16
144 aic7880 10 PCI/32 20MHz 16Bit 16
145 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
146 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
147 aic7892 20 PCI/64 80MHz 16Bit 16 3 4 5 6 7 8
148 aic7895 15 PCI/32 20MHz 16Bit 16 2 3 4 5
149 aic7895C 15 PCI/32 20MHz 16Bit 16 2 3 4 5 8
150 aic7896 20 PCI/32 40MHz 16Bit 16 2 3 4 5 6 7 8
151 aic7897 20 PCI/64 40MHz 16Bit 16 2 3 4 5 6 7 8
152 aic7899 20 PCI/64 80MHz 16Bit 16 2 3 4 5 6 7 8
157 Multiplexed Twin Channel Device - One controller servicing two busses.
159 Multi-function Twin Channel Device - Two controllers on one chip.
161 Command Channel Secondary DMA Engine - Allows scatter gather list and
164 64 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA.
166 Block Move Instruction Support - Doubles the speed of certain sequencer
170 style Scatter Gather Engine - Improves S/G prefetch performance.
172 Queuing Registers - Allows queueing of new transactions without pausing the
175 Multiple Target IDs - Allows the controller to respond to selection as a
176 target on multiple SCSI IDs.
182 driver supports the following
184 host adapter chips and
340 NEC PC-9821Xt13 (PC-98)
344 NEC PC-9821X-B02L/B09 (PC-98)
346 NEC SV-98/2-B03 (PC-98)
348 Many motherboards with on-board
352 .Sh SCSI CONTROL BLOCKS (SCBs)
353 Every transaction sent to a device on the SCSI bus is assigned a
354 .Sq SCSI Control Block
356 The SCB contains all of the information required by the
357 controller to process a transaction.
358 The chip feature table lists
359 the number of SCBs that can be stored in on-chip memory.
361 with model numbers greater than or equal to 7870 allow for the on chip
362 SCB space to be augmented with external SRAM up to a maximum of 255 SCBs.
363 Very few Adaptec controller configurations have external SRAM.
365 If external SRAM is not available, SCBs are a limited resource.
366 Using the SCBs in a straight forward manner would only allow the driver to
367 handle as many concurrent transactions as there are physical SCBs.
368 To fully utilize the SCSI bus and the devices on it,
369 requires much more concurrency.
370 The solution to this problem is
372 a concept similar to memory paging.
373 SCB paging takes advantage of
374 the fact that devices usually disconnect from the SCSI bus for long
375 periods of time without talking to the controller.
376 The SCBs for disconnected transactions are only of use to the controller
377 when the transfer is resumed.
378 When the host queues another transaction
379 for the controller to execute, the controller firmware will use a
380 free SCB if one is available.
381 Otherwise, the state of the most recently
382 disconnected (and therefore most likely to stay disconnected) SCB is
383 saved, via dma, to host memory, and the local SCB reused to start
385 This allows the controller to queue up to
386 255 transactions regardless of the amount of SCB space.
388 local SCB space serves as a cache for disconnected transactions, the
389 more SCB space available, the less host bus traffic consumed saving
390 and restoring SCB data.
392 Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an
394 Rev B in synchronous mode at 10MHz.
395 Controllers with this problem have a
396 42 MHz clock crystal on them and run slightly above 10MHz.
397 This confuses the drive and hangs the bus.
398 Setting a maximum synchronous negotiation rate of 8MHz in the
400 utility will allow normal operation.
402 Although the Ultra2 and Ultra160 products have sufficient instruction
403 ram space to support both the initiator and target roles concurrently,
404 this configuration is disabled in favor of allowing the target role
405 to respond on multiple target ids.
406 A method for configuring dual role mode should be provided.
408 Tagged Queuing is not supported in target mode.
410 Reselection in target mode fails to function correctly on all high
411 voltage differential boards as shipped by Adaptec.
413 how to modify HVD board to work correctly in target mode is available
427 sequencer-code assembler,
428 and the firmware running on the aic7xxx chips was written by
429 .An Justin T. Gibbs .