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32 .Nd Adaptec VL/ISA/PCI SCSI host adapter driver
34 To compile this driver into the kernel,
35 place the following lines in your
36 kernel configuration file:
37 .Bd -ragged -offset indent
41 For one or more PCI cards:
44 To allow PCI adapters to use memory mapped I/O if enabled:
45 .Cd options AHC_ALLOW_MEMIO
47 To configure one or more controllers to assume the target role:
48 .Cd options AHC_TMODE_ENABLE <bitmask of units>
51 Alternatively, to load the driver as a
52 module at boot time, place the following lines in
54 .Bd -literal -offset indent
60 This driver provides access to the
62 bus(es) connected to the Adaptec AIC77xx and AIC78xx
65 Driver features include support for twin and wide busses,
66 fast, ultra or ultra2 synchronous transfers depending on controller type,
67 tagged queueing, SCB paging, and target mode.
69 Memory mapped I/O can be enabled for PCI devices with the
70 .Dq Dv AHC_ALLOW_MEMIO
72 Memory mapped I/O is more efficient than the alternative, programmed I/O.
73 Most PCI BIOSes will map devices so that either technique for communicating
74 with the card is available.
76 usually when the PCI device is sitting behind a PCI->PCI bridge,
77 the BIOS may fail to properly initialize the chip for memory mapped I/O.
78 The typical symptom of this problem is a system hang if memory mapped I/O
80 Most modern motherboards perform the initialization correctly and work fine
81 with this option enabled.
83 Individual controllers may be configured to operate in the target role
85 .Dq Dv AHC_TMODE_ENABLE
87 The value assigned to this option should be a bitmap
88 of all units where target mode is desired.
89 For example, a value of 0x25, would enable target mode on units 0, 2, and 5.
90 A value of 0x8a enables it for units 1, 3, and 7.
92 Per target configuration performed in the
94 menu, accessible at boot
95 is honored by this driver.
96 This includes synchronous/asynchronous transfers,
97 maximum synchronous negotiation rate,
100 the host adapter's SCSI ID.
101 For systems that store non-volatile settings in a system specific manner
102 rather than a serial eeprom directly connected to the aic7xxx controller,
105 must be enabled for the driver to access this information.
106 This restriction applies to
107 many chip-down motherboard configurations.
109 Performance and feature sets vary throughout the aic7xxx product line.
110 The following table provides a comparison of the different chips supported
114 Note that wide and twin channel features, although always supported
115 by a particular chip, may be disabled in a particular motherboard or card
117 .Bd -ragged -offset indent
118 .Bl -column "aic7895CX" "MIPSX" "PCI/64X" "MaxSyncX" "MaxWidthX" "SCBsX" "2 3 4 5 6 7 8X"
119 .It Em "Chip" Ta "MIPS" Ta "Bus" Ta "MaxSync" Ta "MaxWidth" Ta "SCBs" Ta "Features"
120 .It "aic7770" Ta "10" Ta "VL" Ta "10MHz" Ta "16Bit" Ta "4" Ta "1"
121 .It "aic7850" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "8Bit" Ta "3" Ta ""
122 .It "aic7860" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "8Bit" Ta "3" Ta ""
123 .It "aic7870" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "16Bit" Ta "16" Ta ""
124 .It "aic7880" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta ""
125 .It "aic7890" Ta "20" Ta "PCI/32" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
126 .It "aic7891" Ta "20" Ta "PCI/64" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
127 .It "aic7892" Ta "20" Ta "PCI/64" Ta "80MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
128 .It "aic7895" Ta "15" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5"
129 .It "aic7895C" Ta "15" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 8"
130 .It "aic7896" Ta "20" Ta "PCI/32" Ta "40MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 6 7 8"
131 .It "aic7897" Ta "20" Ta "PCI/64" Ta "40MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 6 7 8"
132 .It "aic7899" Ta "20" Ta "PCI/64" Ta "80MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 6 7 8"
137 Multiplexed Twin Channel Device - One controller servicing two busses.
139 Multi-function Twin Channel Device - Two controllers on one chip.
141 Command Channel Secondary DMA Engine - Allows scatter gather list and
144 64 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA.
146 Block Move Instruction Support - Doubles the speed of certain sequencer
150 style Scatter Gather Engine - Improves S/G prefetch performance.
152 Queuing Registers - Allows queueing of new transactions without pausing the
155 Multiple Target IDs - Allows the controller to respond to selection as a
156 target on multiple SCSI IDs.
162 driver supports the following
164 host adapter chips and
317 Many motherboards with on-board
321 .Sh SCSI CONTROL BLOCKS (SCBs)
322 Every transaction sent to a device on the SCSI bus is assigned a
323 .Sq SCSI Control Block
325 The SCB contains all of the information required by the
326 controller to process a transaction.
327 The chip feature table lists
328 the number of SCBs that can be stored in on-chip memory.
330 with model numbers greater than or equal to 7870 allow for the on chip
331 SCB space to be augmented with external SRAM up to a maximum of 255 SCBs.
332 Very few Adaptec controller configurations have external SRAM.
334 If external SRAM is not available, SCBs are a limited resource.
335 Using the SCBs in a straight forward manner would only allow the driver to
336 handle as many concurrent transactions as there are physical SCBs.
337 To fully utilize the SCSI bus and the devices on it,
338 requires much more concurrency.
339 The solution to this problem is
341 a concept similar to memory paging.
342 SCB paging takes advantage of
343 the fact that devices usually disconnect from the SCSI bus for long
344 periods of time without talking to the controller.
345 The SCBs for disconnected transactions are only of use to the controller
346 when the transfer is resumed.
347 When the host queues another transaction
348 for the controller to execute, the controller firmware will use a
349 free SCB if one is available.
350 Otherwise, the state of the most recently
351 disconnected (and therefore most likely to stay disconnected) SCB is
352 saved, via dma, to host memory, and the local SCB reused to start
354 This allows the controller to queue up to
355 255 transactions regardless of the amount of SCB space.
357 local SCB space serves as a cache for disconnected transactions, the
358 more SCB space available, the less host bus traffic consumed saving
359 and restoring SCB data.
376 sequencer-code assembler,
377 and the firmware running on the aic7xxx chips was written by
378 .An Justin T. Gibbs .
380 Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an
382 Rev B in synchronous mode at 10MHz.
383 Controllers with this problem have a
384 42 MHz clock crystal on them and run slightly above 10MHz.
385 This confuses the drive and hangs the bus.
386 Setting a maximum synchronous negotiation rate of 8MHz in the
388 utility will allow normal operation.
390 Although the Ultra2 and Ultra160 products have sufficient instruction
391 ram space to support both the initiator and target roles concurrently,
392 this configuration is disabled in favor of allowing the target role
393 to respond on multiple target ids.
394 A method for configuring dual role mode should be provided.
396 Tagged Queuing is not supported in target mode.
398 Reselection in target mode fails to function correctly on all high
399 voltage differential boards as shipped by Adaptec.
401 how to modify HVD board to work correctly in target mode is available