2 .\" Copyright (c) 2012 Robert N. M. Watson
3 .\" All rights reserved.
5 .\" This software was developed by SRI International and the University of
6 .\" Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 .\" ("CTSRD"), as part of the DARPA CRASH research programme.
9 .\" Redistribution and use in source and binary forms, with or without
10 .\" modification, are permitted provided that the following conditions
12 .\" 1. Redistributions of source code must retain the above copyright
13 .\" notice, this list of conditions and the following disclaimer.
14 .\" 2. Redistributions in binary form must reproduce the above copyright
15 .\" notice, this list of conditions and the following disclaimer in the
16 .\" documentation and/or other materials provided with the distribution.
18 .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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20 .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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35 .Nd driver for the Altera University Program Secure Data Card IP Core
37 .Cd "device altera_sdcard"
40 .Pa /boot/device.hints :
41 .Cd hint.altera_sdcardc.0.at="nexus0"
42 .Cd hint.altera_sdcardc.0.maddr=0x7f008000
43 .Cd hint.altera_sdcardc.0.msize=0x400
47 device driver provides support for the Altera University Program Secure Data
48 Card (SD Card) IP Core device.
51 will be attached during boot.
52 Inserted disks are presented as
56 corresponding to the controller number.
58 The current version of the
60 driver supports the SD Card IP core as described in the August 2011 version of
61 Altera's documentation.
62 The core supports only cards up to 2G (CSD 0); larger cards, or cards using
63 newer CSD versions, will not be detected.
64 The IP core has two key limitations: a lack of interrupt support, requiring
65 timer-driven polling to detect I/O completion, and support for only single
66 512-byte block read and write operations at a time.
67 The combined effect of those two limits is that the system clock rate,
69 must be set to at least 200 in order to accomplish the maximum 100KB/s data
70 rate supported by the IP core.
74 .%T Altera University Program Secure Data Card IP Core
76 .%I Altera Corporation - University Program
77 .%U ftp://ftp.altera.com/up/pub/Altera_Material/11.0/University_Program_IP_Cores/Memory/SD_Card_Interface_for_SoPC_Builder.pdf
82 device driver first appeared in
87 device driver and this manual page were
88 developed by SRI International and the University of Cambridge Computer
89 Laboratory under DARPA/AFRL contract
92 as part of the DARPA CRASH research programme.
93 This device driver was written by
94 .An Robert N. M. Watson .
97 contains a number of work-arounds for IP core bugs.
98 Perhaps most critically,
100 ignores the CRC error bit returned in the RR1 register, which appears to be
101 unexpectedly set by the IP core.
104 uses fixed polling intervals are used for card insertion/removal and
105 I/O completion detection; an adaptive strategy might improve performance by
106 reducing the latency to detecting completed I/O.
107 However, in our experiments, using polling rates greater than 200 times a
108 second did not improve performance.
113 bus attachment, which is appropriate for system-on-chip busses such as
115 If the IP core is configured off of another bus type, then additional bus
116 attachments will be required.