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39 .Nd "Chelsio T4 10Gb and 1Gb Ethernet adapter driver"
41 To compile this driver into the kernel,
42 place the following lines in your
43 kernel configuration file:
44 .Bd -ragged -offset indent
48 To load the driver as a
49 module at boot time, place the following line in
51 .Bd -literal -offset indent
57 driver provides support for PCI Express Ethernet adapters based on
58 the Chelsio Terminator 4 (T4) ASIC.
59 The driver supports Jumbo Frames, Transmit/Receive checksum offload,
60 TCP segmentation offload (TSO), Large Receive Offload (LRO), VLAN
61 tag insertion/extraction, VLAN checksum offload, VLAN TSO, and
62 Receive Side Steering (RSS).
63 For further hardware information and questions related to hardware
65 .Pa http://www.chelsio.com/ .
67 For more information on configuring this device, see
72 driver supports 10Gb and 1Gb Ethernet adapters based on the T4 ASIC:
97 Tunables can be set at the
99 prompt before booting the kernel or stored in
101 .Bl -tag -width indent
102 .It Va hw.cxgbe.ntxq10g
103 The number of tx queues to use for a 10Gb port. The default is 16 or the number
104 of CPU cores in the system, whichever is less.
105 .It Va hw.cxgbe.nrxq10g
106 The number of rx queues to use for a 10Gb port. The default is 8 or the number
107 of CPU cores in the system, whichever is less.
108 .It Va hw.cxgbe.ntxq1g
109 The number of tx queues to use for a 1Gb port. The default is 4 or the number
110 of CPU cores in the system, whichever is less.
111 .It Va hw.cxgbe.nrxq1g
112 The number of rx queues to use for a 1Gb port. The default is 2 or the number
113 of CPU cores in the system, whichever is less.
114 .It Va hw.cxgbe.nofldtxq10g
115 The number of TOE tx queues to use for a 10Gb port. The default is 8 or the
116 number of CPU cores in the system, whichever is less.
117 .It Va hw.cxgbe.nofldrxq10g
118 The number of TOE rx queues to use for a 10Gb port. The default is 2 or the
119 number of CPU cores in the system, whichever is less.
120 .It Va hw.cxgbe.nofldtxq1g
121 The number of TOE tx queues to use for a 1Gb port. The default is 2 or the
122 number of CPU cores in the system, whichever is less.
123 .It Va hw.cxgbe.nofldrxq1g
124 The number of TOE rx queues to use for a 1Gb port. The default is 1.
125 .It Va hw.cxgbe.holdoff_timer_idx_10G
126 .It Va hw.cxgbe.holdoff_timer_idx_1G
127 The timer index value to use to delay interrupts.
128 The holdoff timer list has the values 1, 5, 10, 50, 100, and 200
129 by default (all values are in microseconds) and the index selects a
130 value from this list.
131 The default value is 1 for both 10Gb and 1Gb ports, which means the
133 Different cxgbe interfaces can be assigned different values at any time via the
134 dev.cxgbe.X.holdoff_tmr_idx sysctl.
135 .It Va hw.cxgbe.holdoff_pktc_idx_10G
136 .It Va hw.cxgbe.holdoff_pktc_idx_1G
137 The packet-count index value to use to delay interrupts.
138 The packet-count list has the values 1, 8, 16, and 32 by default
139 and the index selects a value from this list.
140 The default value is 2 for both 10Gb and 1Gb ports, which means 16
141 packets (or the holdoff timer going off) before an interrupt is
143 -1 disables packet counting.
144 Different cxgbe interfaces can be assigned different values via the
145 dev.cxgbe.X.holdoff_pktc_idx sysctl.
146 This sysctl works only when the interface has never been marked up (as done by
148 .It Va hw.cxgbe.qsize_txq
149 The size, in number of entries, of the descriptor ring used for a tx
151 A buf_ring of the same size is also allocated for additional
152 software queuing. See
154 The default value is 1024.
155 Different cxgbe interfaces can be assigned different values via the
156 dev.cxgbe.X.qsize_txq sysctl.
157 This sysctl works only when the interface has never been marked up (as done by
159 .It Va hw.cxgbe.qsize_rxq
160 The size, in number of entries, of the descriptor ring used for an
162 The default value is 1024.
163 Different cxgbe interfaces can be assigned different values via the
164 dev.cxgbe.X.qsize_rxq sysctl.
165 This sysctl works only when the interface has never been marked up (as done by
167 .It Va hw.cxgbe.interrupt_types
168 The interrupt types that the driver is allowed to use.
169 Bit 0 represents INTx (line interrupts), bit 1 MSI, bit 2 MSI-X.
170 The default is 7 (all allowed).
171 The driver will select the best possible type out of the allowed types by
173 .It Va hw.cxgbe.config_file
174 Select a pre-packaged device configuration file.
175 A configuration file contains a recipe for partitioning and configuring the
176 hardware resources on the card.
177 This tunable is for specialized applications only and should not be used in
179 The configuration profile currently in use is available in the dev.t4nex.X.cf
180 and dev.t4nex.X.cfcsum sysctls.
181 .It Va hw.cxgbe.linkcaps_allowed
182 .It Va hw.cxgbe.niccaps_allowed
183 .It Va hw.cxgbe.toecaps_allowed
184 .It Va hw.cxgbe.rdmacaps_allowed
185 .It Va hw.cxgbe.iscsicaps_allowed
186 .It Va hw.cxgbe.fcoecaps_allowed
187 Disallowing capabilities provides a hint to the driver and firmware to not
188 reserve hardware resources for that feature.
189 Each of these is a bit field with a bit for each sub-capability within the
191 This tunable is for specialized applications only and should not be used in
193 The capabilities for which hardware resources have been reserved are listed in
194 dev.t4nex.X.*caps sysctls.
197 For general information and support,
198 go to the Chelsio support website at:
199 .Pa http://www.chelsio.com/ .
201 If an issue is identified with this driver with a supported adapter,
202 email all the specific information related to the issue to
203 .Aq support@chelsio.com .
214 device driver first appeared in
220 driver was written by
221 .An Navdeep Parhar Aq np@FreeBSD.org .