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32 .Nd Intel I/O Acceleration Technology
34 To compile this driver into your kernel,
35 place the following line in your kernel configuration file:
36 .Bd -ragged -offset indent
40 Or, to load the driver as a module at boot, place the following line in
42 .Bd -literal -offset indent
49 .Cd hw.ioat.force_legacy_interrupts=0
55 .Cd hw.ioat.enable_ioat_test=0
56 .Cd hw.ioat.debug_level=0
57 (only critical errors; maximum of 3)
60 .Fn (*bus_dmaengine_callback_t) "void *arg" "int error"
63 .Fn ioat_get_dmaengine "uint32_t channel_index"
65 .Fn ioat_put_dmaengine "bus_dmaengine_t dmaengine"
67 .Fn ioat_get_hwversion "bus_dmaengine_t dmaengine"
69 .Fn ioat_get_max_io_size "bus_dmaengine_t dmaengine"
71 .Fn ioat_set_interrupt_coalesce "bus_dmaengine_t dmaengine" "uint16_t delay"
73 .Fn ioat_get_max_coalesce_period "bus_dmaengine_t dmaengine"
75 .Fn ioat_acquire "bus_dmaengine_t dmaengine"
77 .Fn ioat_acquire_reserve "bus_dmaengine_t dmaengine" "uint32_t n" "int mflags"
79 .Fn ioat_release "bus_dmaengine_t dmaengine"
80 .Ft struct bus_dmadesc *
82 .Fa "bus_dmaengine_t dmaengine"
86 .Fa "bus_dmaengine_callback_t callback_fn"
87 .Fa "void *callback_arg"
90 .Ft struct bus_dmadesc *
91 .Fo ioat_copy_8k_aligned
92 .Fa "bus_dmaengine_t dmaengine"
97 .Fa "bus_dmaengine_callback_t callback_fn"
98 .Fa "void *callback_arg"
101 .Ft struct bus_dmadesc *
103 .Fa "bus_dmaengine_t dmaengine"
105 .Fa "uint64_t fillpattern"
107 .Fa "bus_dmaengine_callback_t callback_fn"
108 .Fa "void *callback_arg"
111 .Ft struct bus_dmadesc *
113 .Fa "bus_dmaengine_t dmaengine"
114 .Fa "bus_dmaengine_callback_t callback_fn"
115 .Fa "void *callback_arg"
121 driver provides a kernel API to a variety of DMA engines on some Intel server
124 There is a number of DMA channels per CPU package.
126 Each may be used independently.
127 Operations on a single channel proceed sequentially.
129 Blockfill operations can be used to write a 64-bit pattern to memory.
131 Copy operations can be used to offload memory copies to the DMA engines.
133 Null operations do nothing, but may be used to test the interrupt and callback
136 All operations can optionally trigger an interrupt at completion with the
139 For example, a user might submit multiple operations to the same channel and
140 only enable an interrupt and callback for the last operation.
142 The hardware can delay and coalesce interrupts on a given channel for a
143 configurable period of time, in microseconds.
144 This may be desired to reduce the processing and interrupt overhead per
145 descriptor, especially for workflows consisting of many small operations.
146 Software can control this on a per-channel basis with the
147 .Fn ioat_set_interrupt_coalesce
150 .Fn ioat_get_max_coalesce_period
151 API can be used to determine the maximum coalescing period supported by the
152 hardware, in microseconds.
153 Current platforms support up to a 16.383 millisecond coalescing period.
154 Optimal configuration will vary by workflow and desired operation latency.
156 All operations are safe to use in a non-blocking context with the
159 (Of course, allocations may fail and operations requested with
163 All operations, as well as
164 .Fn ioat_get_dmaengine ,
165 can return NULL in special circumstances.
168 driver is being unloaded, or the administrator has induced a hardware reset, or
169 a usage error has resulted in a hardware error state that needs to be recovered
172 It is invalid to attempt to submit new DMA operations in a
173 .Fa bus_dmaengine_callback_t
176 A typical user will lookup the DMA engine object for a given channel with
177 .Fn ioat_get_dmaengine .
178 When the user wants to offload a copy, they will first
182 object for exclusive access to enqueue operations on that channel.
183 Optionally, the user can reserve space by using
184 .Fn ioat_acquire_reserve
187 .Fn ioat_acquire_reserve
188 succeeds, there is guaranteed to be room for
190 new operations in the internal ring buffer.
191 Then, they will submit one or more operations using
196 After queuing one or more individual DMA operations, they will
200 to drop their exclusive access to the channel.
201 The routine they provided for the
203 argument will be invoked with the provided
205 when the operation is complete.
206 When they are finished with the
207 .Ar bus_dmaengine_t ,
209 .Fn ioat_put_dmaengine .
211 Users MUST NOT block between
215 Users SHOULD NOT hold
217 references for a very long time to enable fault recovery and kernel module
220 For an example of usage, see
221 .Pa src/sys/dev/ioat/ioat_test.c .
224 .It Pa /dev/ioat_test
233 driver first appeared in
238 driver was developed by
239 .An \&Jim Harris Aq Mt jimharris@FreeBSD.org ,
240 .An \&Carl Delsey Aq Mt carl.r.delsey@intel.com ,
242 .An \&Conrad Meyer Aq Mt cem@FreeBSD.org .
243 This manual page was written by
244 .An \&Conrad Meyer Aq Mt cem@FreeBSD.org .
246 Copy operation takes bus addresses as parameters, not virtual addresses.
248 Buffers for individual copy operations must be physically contiguous.
250 Copies larger than max transfer size (1MB, but may vary by hardware) are not
252 Future versions will likely support this by breaking up the transfer into
257 driver only supports blockfill, copy, and null operations at this time.
258 The driver does not yet support advanced DMA modes, such as XOR, that some
259 I/OAT devices support.