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32 .Nd Zynq PL device config interface
38 can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000.
40 On the first write to the character device at file offset 0, the
43 asserts the top-level PL reset signals, disables the PS-PL level shifters,
44 and clears the PL configuration.
45 Write data is sent to the PCAP (processor configuration access port).
46 When the PL asserts the DONE signal, the devcfg driver will enable the level
47 shifters and release the top-level PL reset signals.
49 The PL (FPGA) can be configured by writing the bitstream to the character
51 .Bd -literal -offset indent
52 cat design.bit.bin > /dev/devcfg
55 The file should not be confused with the .bit file output by the FPGA
57 It is the binary form of the configuration bitstream.
60 tool can do the conversion:
61 .Bd -literal -offset indent
62 promgen -b -w -p bin -data_width 32 -u 0 design.bit -o design.bit.bin
67 driver provides the following
71 .It Va hw.fpga.pl_done
73 This variable always reflects the status of the PL's DONE signal.
74 A 1 means the PL section has been properly programmed.
75 .It Va hw.fpga.en_level_shifters
77 This variable controls if the PS-PL level shifters are enabled after the
78 PL section has been reconfigured.
79 This variable is 1 by default but setting it to 0 allows the PL section to be
80 programmed with configurations that do not interface to the PS section of the
82 Changing this value has no effect on the level shifters until the next device
88 Character device for the
93 Zynq-7000 SoC Technical Reference Manual (Xilinx doc UG585)