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32 .Nd Parallel Port Bus system
46 system provides a uniform, modular and architecture-independent
47 system for the implementation of drivers to control various parallel devices,
48 and to utilize different parallel port chipsets.
50 In order to write new drivers or port existing drivers, the ppbus system
51 provides the following facilities:
52 .Bl -bullet -offset indent
54 architecture-independent macros or functions to access parallel ports
56 mechanism to allow various devices to share the same parallel port
58 a user interface named
60 that allows parallel port access from outside the kernel without conflicting
61 with kernel-in drivers.
63 .Ss Developing new drivers
65 The ppbus system has been designed to support the development of standard
66 and non-standard software:
68 .Bl -column "Driver" -compact
69 .It Em Driver Ta Em Description
70 .It Sy vpo Ta "VPI0 parallel to Adaptec AIC-7110 SCSI controller driver" .
71 It uses standard and non-standard parallel port accesses.
72 .It Sy ppi Ta "Parallel port interface for general I/O"
73 .It Sy pps Ta "Pulse per second Timing Interface"
74 .It Sy lpbb Ta "Philips official parallel port I2C bit-banging interface"
76 .Ss Porting existing drivers
78 Another approach to the ppbus system is to port existing drivers.
79 Various drivers have already been ported:
81 .Bl -column "Driver" -compact
82 .It Em Driver Ta Em Description
83 .It Sy lpt Ta "lpt printer driver"
84 .It Sy plip Ta "lp parallel network interface driver"
87 ppbus should let you port any other software even from other operating systems
88 that provide similar services.
89 .Sh PARALLEL PORT CHIPSETS
90 Parallel port chipset support is provided by
93 The ppbus system provides functions and macros to allocate a new
94 parallel port bus, then initialize it and upper peripheral device drivers.
96 ppc makes chipset detection and initialization and then calls ppbus attach
97 functions to initialize the ppbus system.
98 .Sh PARALLEL PORT MODEL
99 The logical parallel port model chosen for the ppbus system is the PC's
101 Consequently, for the i386 implementation of ppbus,
102 most of the services provided by ppc are macros for inb()
104 But, for an other architecture, accesses to one of our logical
105 registers (data, status, control...) may require more than one I/O access.
107 The parallel port may operate in the following modes:
108 .Bl -bullet -offset indent
110 compatible mode, also called Centronics mode
112 bidirectional 8/4-bits mode, also called NIBBLE mode
114 byte mode, also called PS/2 mode
116 Extended Capability Port mode, ECP
118 Enhanced Parallel Port mode, EPP
120 mixed ECP+EPP or ECP+PS/2 modes
123 This mode defines the protocol used by most PCs to transfer data to a printer.
124 In this mode, data is placed on the port's data lines, the printer status is
125 checked for no errors and that it is not busy, and then a data Strobe is
126 generated by the software to clock the data to the printer.
128 Many I/O controllers have implemented a mode that uses a FIFO buffer to
129 transfer data with the Compatibility mode protocol.
130 This mode is referred to as
131 "Fast Centronics" or "Parallel Port FIFO mode".
132 .Ss Bidirectional mode
133 The NIBBLE mode is the most common way to get reverse channel data from a
134 printer or peripheral.
135 Combined with the standard host to printer mode, it
136 provides a complete bidirectional channel.
138 In this mode, outputs are 8-bits long.
139 Inputs are accomplished by reading
140 4 of the 8 bits of the status register.
142 In this mode, the data register is used either for outputs and inputs.
144 any transfer is 8-bits long.
145 .Ss Extended Capability Port mode
146 The ECP protocol was proposed as an advanced mode for communication with
147 printer and scanner type peripherals.
148 Like the EPP protocol, ECP mode provides
149 for a high performance bidirectional communication path between the host
150 adapter and the peripheral.
152 ECP protocol features include:
153 .Bl -item -offset indent
155 Run_Length_Encoding (RLE) data compression for host adapters
157 FIFOs for both the forward and reverse channels
159 DMA as well as programmed I/O for the host register interface.
161 .Ss Enhanced Parallel Port mode
162 The EPP protocol was originally developed as a means to provide a high
163 performance parallel port link that would still be compatible with the
164 standard parallel port.
166 The EPP mode has two types of cycle: address and data.
168 difference at hardware level is the strobe of the byte placed on the data
170 Data are strobed with nAutofeed, addresses are strobed with
173 A particularity of the ISA implementation of the EPP protocol is that an
174 EPP cycle fits in an ISA cycle.
175 In this fashion, parallel port peripherals can
176 operate at close to the same performance levels as an equivalent ISA plug-in
179 At software level, you may implement the protocol you wish, using data and
180 address cycles as you want.
181 This is for the IEEE1284 compatible part.
183 peripheral vendors may implement protocol handshake with the following
184 status lines: PError, nFault and Select.
185 Try to know how these lines toggle
186 with your peripheral, allowing the peripheral to request more data, stop the
189 At any time, the peripheral may interrupt the host with the nAck signal without
190 disturbing the current transfer.
192 Some manufacturers, like SMC, have implemented chipsets that support mixed
194 With such chipsets, mode switching is available at any time by
195 accessing the extended control register.
196 .Sh IEEE1284-1994 Standard
198 This standard is also named "IEEE Standard Signaling Method for a
199 Bidirectional Parallel Peripheral Interface for Personal Computers".
201 defines a signaling method for asynchronous, fully interlocked, bidirectional
202 parallel communications between hosts and printers or other peripherals.
204 also specifies a format for a peripheral identification string and a method of
205 returning this string to the host outside of the bidirectional data stream.
207 This standard is architecture independent and only specifies dialog handshake
209 One should refer to architecture specific documentation in
210 order to manipulate machine dependent registers, mapped memory or other
211 methods to control these signals.
213 The IEEE1284 protocol is fully oriented with all supported parallel port
215 The computer acts as master and the peripheral as slave.
217 Any transfer is defined as a finite state automaton.
218 It allows software to
219 properly manage the fully interlocked scheme of the signaling method.
220 The compatible mode is supported "as is" without any negotiation because it
222 Any other mode must be firstly negotiated by the host to check
223 it is supported by the peripheral, then to enter one of the forward idle
226 At any time, the slave may want to send data to the host.
228 possible from forward idle states (nibble, byte, ecp...).
230 host must have previously negotiated to permit the peripheral to
232 Interrupt lines may be dedicated to the requesting signals
233 to prevent time consuming polling methods.
235 But peripheral requests are only a hint to the master host.
237 accepts the transfer, it must firstly negotiate the reverse mode and then
239 At any time during reverse transfer, the host may
240 terminate the transfer or the slave may drive wires to signal that no more
243 IEEE1284 Standard support has been implemented at the top of the ppbus system
244 as a set of procedures that perform high level functions like negotiation,
245 termination, transfer in any mode without bothering you with low level
246 characteristics of the standard.
248 IEEE1284 interacts with the ppbus system as little as possible.
250 you still have to request the ppbus when you want to access it, the negotiate
251 function doesn't do it for you.
252 And of course, release it later.
254 .Ss adapter, ppbus and device layers
257 layer, the lowest of the ppbus system.
259 chipset abstraction throw a set of low level functions that maps the logical
260 model to the underlying hardware.
262 Secondly, there is the
264 layer that provides functions to:
265 .Bl -enum -offset indent
267 share the parallel port bus among the daisy-chain like connected devices
269 manage devices linked to ppbus
271 propose an arch-independent interface to access the hardware layer.
276 layer gathers the parallel peripheral device drivers.
278 .Ss Parallel modes management
279 We have to differentiate operating modes at various ppbus system layers.
280 Actually, ppbus and adapter operating modes on one hands and for each
281 one, current and available modes are separated.
283 With this level of abstraction a particular chipset may commute from any
284 native mode the any other mode emulated with extended modes without
285 disturbing upper layers.
286 For example, most chipsets support NIBBLE mode as
287 native and emulated with ECP and/or EPP.
289 This architecture should support IEEE1284-1994 modes.
292 The boot process starts with the probe stage of the
294 driver during ISA bus (PC architecture) initialization.
296 the ppc driver, a new ppbus structure is allocated, then probe and attachment
297 for this new bus node are called.
299 ppbus attachment tries to detect any PnP parallel peripheral (according to
300 .%T "Plug and Play Parallel Port Devices"
301 draft from (c)1993-4 Microsoft Corporation)
302 then probes and attaches known device drivers.
304 During probe, device drivers are supposed to request the ppbus and try to
305 set their operating mode.
306 This mode will be saved in the context structure and
307 returned each time the driver requests the ppbus.
308 .Ss Bus allocation and interrupts
309 ppbus allocation is mandatory not to corrupt I/O of other devices.
311 usage of ppbus allocation is to reserve the port and receive incoming
314 High level interrupt handlers are connected to the ppbus system thanks to the
318 .Fn BUS_TEARDOWN_INTR
320 But, in order to attach a handler, drivers must
322 Consequently, a ppbus request is mandatory in order to call the above
323 functions (see existing drivers for more info).
324 Note that the interrupt handler
325 is automatically released when the ppbus is released.
328 is a general purpose mechanism to allow fast low-level
329 manipulation of the parallel port.
330 Microsequences may be used to do either
331 standard (in IEEE1284 modes) or non-standard transfers.
333 microsequences is to avoid the overhead of the ppbus layer and do most of
334 the job at adapter level.
336 A microsequence is an array of opcodes and parameters.
338 operation (opcodes are described in
340 Standard I/O operations are implemented at ppbus level whereas basic I/O
341 operations and microseq language are coded at adapter level for efficiency.
345 driver uses microsequences to implement:
346 .Bl -bullet -offset indent
348 a modified version of the NIBBLE transfer mode
350 various I/O sequences to initialize, select and allocate the peripheral
361 manual page first appeared in
365 manual page was written by