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4 .\" Copyright (c) 2020 Denis Salopek
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34 .Nd "NetFPGA SUME 4x10Gb Ethernet driver"
36 To compile this driver into the kernel, place the following lines
37 in your kernel configuration file:
38 .Bd -ragged -offset indent
42 Alternatively, to load the driver as a module at boot time, place
45 .Bd -literal -offset indent
51 driver provides support for NetFPGA SUME Virtex-7 FPGA Development Board
52 with the reference NIC bitstream loaded onto it.
53 The HDL design for the reference NIC project uses the RIFFA based DMA
54 engine to communicate with the host machine over PCIe.
55 Every packet is transmitted to / from the board via a single DMA
56 transaction, taking up to two or three interrupts per one transaction
57 which yields low performance.
59 There is no support for Jumbo frames as the hardware is capable of
60 dealing only with frames with maximum size of 1514 bytes.
61 The hardware does not support multicast filtering, provides no checksums,
62 and offers no other offloading.
73 driver was originally written by
77 .Fx version and this manual page were written by
80 More information about the project can be found here:
81 .Pa https://wiki.freebsd.org/SummerOfCode2020Projects/NetFPGA_SUME_Driver
83 The reference NIC hardware design provides no mechanism for quiescing
84 inbound traffic from interfaces configured as DOWN.
85 All packets from administratively disabled interfaces are transferred to
86 main memory, leaving the driver with the task of dropping such packets,
87 thus consuming PCI bandwidth, interrupts and CPU cycles in vain.
89 Pre-built FPGA bitstream from the NetFPGA project may not work correctly.
90 At higher RX packet rates, the newly incoming packets can overwrite the
91 ones in an internal FIFO so the packets would arrive in main memory
92 corrupted, until a physical reset of the board.
94 Occasionally, the driver can get stuck in a non-IDLE TX state due to
96 The driver includes a watchdog function which monitors for such a
97 condition and resets the board automatically.
98 For more details, visit the NetFPGA SUME project site.