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34 .Nd Architecture-specific details
36 Differences between CPU architectures and platforms supported by
39 This document is a quick reference of key ABI details of
42 For full details consult the processor-specific ABI supplement
45 If not explicitly mentioned, sizes are in bytes.
46 The architecture details in this document apply to
48 and later, unless otherwise noted.
51 uses a flat address space.
57 and pointers all have the same representation.
59 In order to maximize compatibility with future pointer integrity mechanisms,
60 manipulations of pointers as integers should be performed via
71 On some architectures, e.g.,
75 the kernel uses a separate address space.
76 On other architectures, kernel and a user mode process share a
78 The kernel is located at the highest addresses.
80 On each architecture, the main user mode thread's stack starts near
81 the highest user address and grows down.
84 architecture support varies by release.
85 This table shows the first
87 release to support each architecture, and, for discontinued
88 architectures, the final release.
90 .Bl -column -offset indent "Sy Architecture" "Sy Initial Release" "Sy Final Release"
91 .It Sy Architecture Ta Sy Initial Release Ta Sy Final Release
93 .It alpha Ta 3.2 Ta 6.4
95 .It arm Ta 6.0 Ta 12.x
96 .It armeb Ta 8.0 Ta 11.x
99 .It ia64 Ta 5.0 Ta 10.4
108 .It mips64elhf Ta 12.0
110 .It pc98 Ta 2.2 Ta 11.x
112 .It powerpcspe Ta 12.0
115 .It riscv64sf Ta 12.0
116 .It sparc64 Ta 5.0 Ta 12.x
121 architectures use some variant of the ELF (see
123 .Sy Application Binary Interface
124 (ABI) for the machine processor.
125 All supported ABIs can be divided into two groups:
126 .Bl -tag -width "Dv ILP32"
131 types machine representations all have 4-byte size.
134 type machine representation uses 4 bytes,
142 Some machines support more than one
145 Typically these are 64-bit machines, where the
148 execution environment is accompanied by the
151 environment, which was the historical 32-bit predecessor for 64-bit evolution.
153 .Bl -column -offset indent "Dv powerpc64" "Sy ILP32 counterpart"
154 .It Sy LP64 Ta Sy ILP32 counterpart
155 .It Dv amd64 Ta Dv i386
156 .It Dv powerpc64 Ta Dv powerpc
157 .It Dv mips64* Ta Dv mips*
158 .It Dv aarch64 Ta Dv armv6/armv7
162 will support execution of
166 binaries if the CPU implements
168 execution state, however
170 binaries aren't supported.
172 On all supported architectures:
173 .Bl -column -offset -indent "long long" "Size"
174 .It Sy Type Ta Sy Size
177 .It long Ta sizeof(void*)
183 Integers are represented in two's complement.
184 Alignment of integer and pointer types is natural, that is,
185 the address of the variable must be congruent to zero modulo the type size.
186 Most ILP32 ABIs, except
188 require only 4-byte alignment for 64-bit integers.
190 Machine-dependent type sizes:
191 .Bl -column -offset indent "Sy Architecture" "Sy void *" "Sy long double" "Sy time_t"
192 .It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t
193 .It aarch64 Ta 8 Ta 16 Ta 8
194 .It amd64 Ta 8 Ta 16 Ta 8
195 .It armv6 Ta 4 Ta 8 Ta 8
196 .It armv7 Ta 4 Ta 8 Ta 8
197 .It i386 Ta 4 Ta 12 Ta 4
198 .It mips Ta 4 Ta 8 Ta 8
199 .It mipsel Ta 4 Ta 8 Ta 8
200 .It mipselhf Ta 4 Ta 8 Ta 8
201 .It mipshf Ta 4 Ta 8 Ta 8
202 .It mipsn32 Ta 4 Ta 8 Ta 8
203 .It mips64 Ta 8 Ta 8 Ta 8
204 .It mips64el Ta 8 Ta 8 Ta 8
205 .It mips64elhf Ta 8 Ta 8 Ta 8
206 .It mips64hf Ta 8 Ta 8 Ta 8
207 .It powerpc Ta 4 Ta 8 Ta 8
208 .It powerpcspe Ta 4 Ta 8 Ta 8
209 .It powerpc64 Ta 8 Ta 8 Ta 8
210 .It riscv64 Ta 8 Ta 16 Ta 8
211 .It riscv64sf Ta 8 Ta 16 Ta 8
215 is 8 bytes on all supported architectures except i386.
216 .Ss Endianness and Char Signedness
217 .Bl -column -offset indent "Sy Architecture" "Sy Endianness" "Sy char Signedness"
218 .It Sy Architecture Ta Sy Endianness Ta Sy char Signedness
219 .It aarch64 Ta little Ta unsigned
220 .It amd64 Ta little Ta signed
221 .It armv6 Ta little Ta unsigned
222 .It armv7 Ta little Ta unsigned
223 .It i386 Ta little Ta signed
224 .It mips Ta big Ta signed
225 .It mipsel Ta little Ta signed
226 .It mipselhf Ta little Ta signed
227 .It mipshf Ta big Ta signed
228 .It mipsn32 Ta big Ta signed
229 .It mips64 Ta big Ta signed
230 .It mips64el Ta little Ta signed
231 .It mips64elhf Ta little Ta signed
232 .It mips64hf Ta big Ta signed
233 .It powerpc Ta big Ta unsigned
234 .It powerpcspe Ta big Ta unsigned
235 .It powerpc64 Ta big Ta unsigned
236 .It riscv64 Ta little Ta signed
237 .It riscv64sf Ta little Ta signed
240 .Bl -column -offset indent "Sy Architecture" "Sy Page Sizes"
241 .It Sy Architecture Ta Sy Page Sizes
242 .It aarch64 Ta 4K, 2M, 1G
243 .It amd64 Ta 4K, 2M, 1G
246 .It i386 Ta 4K, 2M (PAE), 4M
263 .Bl -column -offset indent "Sy Architecture" "Sy float, double" "Sy long double"
264 .It Sy Architecture Ta Sy float, double Ta Sy long double
265 .It aarch64 Ta hard Ta soft, quad precision
266 .It amd64 Ta hard Ta hard, 80 bit
267 .It armv6 Ta hard Ta hard, double precision
268 .It armv7 Ta hard Ta hard, double precision
269 .It i386 Ta hard Ta hard, 80 bit
270 .It mips Ta soft Ta identical to double
271 .It mipsel Ta soft Ta identical to double
272 .It mipselhf Ta hard Ta identical to double
273 .It mipshf Ta hard Ta identical to double
274 .It mipsn32 Ta soft Ta identical to double
275 .It mips64 Ta soft Ta identical to double
276 .It mips64el Ta soft Ta identical to double
277 .It mips64elhf Ta hard Ta identical to double
278 .It mips64hf Ta hard Ta identical to double
279 .It powerpc Ta hard Ta hard, double precision
280 .It powerpcspe Ta hard Ta hard, double precision
281 .It powerpc64 Ta hard Ta hard, double precision
282 .It riscv64 Ta hard Ta hard, double precision
283 .It riscv64sf Ta soft Ta soft, double precision
285 .Ss Default Tool Chain
286 .Fx uses a variety of tool chain components for the supported CPU
291 provided by the base system,
296 or an external toolchain compiler and linker provided by a port or package.
297 This table shows the default tool chain for each architecture.
298 .Bl -column -offset indent "Sy Architecture" "Sy Compiler" "Sy Linker"
299 .It Sy Architecture Ta Sy Compiler Ta Sy Linker
300 .It aarch64 Ta Clang Ta lld
301 .It amd64 Ta Clang Ta lld
302 .It armv6 Ta Clang Ta lld
303 .It armv7 Ta Clang Ta lld
304 .It i386 Ta Clang Ta lld
305 .It mips Ta GCC(1) Ta GNU ld(1)
306 .It mipsel Ta GCC(1) Ta GNU ld(1)
307 .It mipselhf Ta GCC(1) Ta GNU ld(1)
308 .It mipshf Ta GCC(1) Ta GNU ld(1)
309 .It mipsn32 Ta GCC(1) Ta GNU ld(1)
310 .It mips64 Ta GCC(1) Ta GNU ld(1)
311 .It mips64el Ta GCC(1) Ta GNU ld(1)
312 .It mips64elhf Ta GCC(1) Ta GNU ld(1)
313 .It mips64hf Ta GCC(1) Ta GNU ld(1)
314 .It powerpc Ta Clang Ta GNU ld 2.17.50
315 .It powerpcspe Ta Clang Ta GNU ld 2.17.50
316 .It powerpc64 Ta Clang Ta lld
317 .It riscv64 Ta Clang Ta lld
318 .It riscv64sf Ta Clang Ta lld
321 (1) External toolchain provided by ports/packages.
323 Note that GCC 4.2.1 is deprecated, and scheduled for removal on 2020-03-31.
324 Any CPU architectures not migrated by then
325 (to either base system Clang or external toolchain)
326 may be removed from the tree after that date.
327 make universe will not build mips
328 architectures unless the xtoolchain binaries have been installed for
330 .Ss MACHINE_ARCH vs MACHINE_CPUARCH vs MACHINE
332 should be preferred in Makefiles when the generic
333 architecture is being tested.
335 should be preferred when there is something specific to a particular type of
336 architecture where there is a choice of many, or could be a choice of many.
339 when referring to the kernel, interfaces dependent on a specific type of kernel
340 or similar things like boot sequences.
341 .Bl -column -offset indent "Dv MACHINE" "Dv MACHINE_CPUARCH" "Dv MACHINE_ARCH"
342 .It Dv MACHINE Ta Dv MACHINE_CPUARCH Ta Dv MACHINE_ARCH
343 .It arm64 Ta aarch64 Ta aarch64
344 .It amd64 Ta amd64 Ta amd64
345 .It arm Ta arm Ta armv6, armv7
346 .It i386 Ta i386 Ta i386
347 .It mips Ta mips Ta mips, mipsel, mips64, mips64el, mipshf, mipselhf, mips64elhf, mipsn32
348 .It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64
349 .It riscv Ta riscv Ta riscv64, riscv64sf
351 .Ss Predefined Macros
352 The compiler provides a number of predefined macros.
353 Some of these provide architecture-specific details and are explained below.
354 Other macros, including those required by the language standard, are not
357 The full set of predefined macros can be obtained with this command:
358 .Bd -literal -offset indent
359 cc -x c -dM -E /dev/null
362 Common type size and endianness macros:
363 .Bl -column -offset indent "BYTE_ORDER" "Sy Meaning"
364 .It Sy Macro Ta Sy Meaning
365 .It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int
366 .It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer
367 .It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN .
373 Architecture-specific macros:
374 .Bl -column -offset indent "Sy Architecture" "Sy Predefined macros"
375 .It Sy Architecture Ta Sy Predefined macros
376 .It aarch64 Ta Dv __aarch64__
377 .It amd64 Ta Dv __amd64__, Dv __x86_64__
378 .It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6
379 .It armv7 Ta Dv __arm__, Dv __ARM_ARCH >= 7
380 .It i386 Ta Dv __i386__
381 .It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32
382 .It mipsel Ta Dv __mips__, Dv __mips_o32
383 .It mipselhf Ta Dv __mips__, Dv __mips_o32
384 .It mipshf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32
385 .It mipsn32 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n32
386 .It mips64 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64
387 .It mips64el Ta Dv __mips__, Dv __mips_n64
388 .It mips64elhf Ta Dv __mips__, Dv __mips_n64
389 .It mips64hf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64
390 .It powerpc Ta Dv __powerpc__
391 .It powerpcspe Ta Dv __powerpc__, Dv __SPE__
392 .It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__
393 .It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64
394 .It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64
397 Compilers may define additional variants of architecture-specific macros.
398 The macros above are preferred for use in
400 .Ss Important Xr make 1 variables
401 Most of the externally settable variables are defined in the
404 These variables are not otherwise documented and are used extensively
406 .Bl -tag -width "MACHINE_CPUARCH"
408 Represents the hardware platform.
409 This is the same as the native platform's
413 It defines both the userland / kernel interface, as well as the
414 bootloader / kernel interface.
415 It should only be used in these contexts.
416 Each CPU architecture may have multiple hardware platforms it supports
420 It is used to collect together all the files from
423 It is often the same as
425 just as one CPU architecture can be implemented by many different
426 hardware platforms, one hardware platform may support multiple CPU
427 architecture family members, though with different binaries.
430 of i386 supported the IBM-AT hardware platform while the
432 of pc98 supported the Japanese company NEC's PC-9801 and PC-9821
434 Both of these hardware platforms supported only the
436 of i386 where they shared a common ABI, except for certain kernel /
437 userland interfaces relating to underlying hardware platform
438 differences in bus architecture, device enumeration and boot interface.
441 should only be used in src/sys and src/stand or in system imagers or
444 Represents the CPU processor architecture.
445 This is the same as the native platforms
449 It defines the CPU instruction family supported.
450 It may also encode a variation in the byte ordering of multi-byte
452 It may also encode a variation in the size of the integer or pointer.
453 It may also encode a ISA revision.
454 It may also encode hard versus soft floating point ABI and usage.
455 It may also encode a variant ABI when the other factors do not
456 uniquely define the ABI (e.g., MIPS' n32 ABI).
459 defines the ABI used by the system.
460 For example, the MIPS CPU processor family supports 9 different
461 combinations encoding pointer size, endian and hard versus soft float (for
462 8 combinations) as well as N32 (which only ever had one variation of
464 Generally, the plain CPU name specifies the most common (or at least
465 first) variant of the CPU.
466 This is why mips and mips64 imply 'big endian' while 'armv6' and 'armv7'
468 If we ever were to support the so-called x32 ABI (using 32-bit
469 pointers on the amd64 architecture), it would most likely be encoded
471 It is unfortunate that amd64 specifies the 64-bit evolution of the x86
472 platform (it matches the 'first rule') as everybody else uses x86_64.
473 There is no standard name for the processor: each OS selects its own
475 .It Dv MACHINE_CPUARCH
476 Represents the source location for a given
478 It is generally the common prefix for all the MACHINE_ARCH that
479 share the same implementation, though 'riscv' breaks this rule.
482 is defined to be mips for all the flavors of mips that we support
483 since we support them all with a shared set of sources.
484 While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86
486 The FreeBSD source base supports amd64 and i386 with two
487 distinct source bases living in subdirectories named amd64 and i386
488 (though behind the scenes there's some sharing that fits into this
494 It is used to optimize the build for a specific CPU / core that the
496 Generally, this does not change the ABI, though it can be a fine line
497 between optimization for specific cases.
501 in the top level Makefile for cross building.
502 Unused outside of that scope.
503 It is not passed down to the rest of the build.
504 Makefiles outside of the top level should not use it at all (though
505 some have their own private copy for hysterical raisons).
509 by the top level Makefile for cross building.
512 it is unused outside of that scope.
520 manual page appeared in