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34 .Nd Architecture-specific details
36 Differences between CPU architectures and platforms supported by
39 This document is a quick reference of key ABI details of
42 For full details consult the processor-specific ABI supplement
45 If not explicitly mentioned, sizes are in bytes.
46 The architecture details in this document apply to
48 and later, unless otherwise noted.
51 uses a flat address space.
57 and pointers all have the same representation.
59 In order to maximize compatibility with future pointer integrity mechanisms,
60 manipulations of pointers as integers should be performed via
71 On some architectures, e.g.,
75 the kernel uses a separate address space.
76 On other architectures, kernel and a user mode process share a
78 The kernel is located at the highest addresses.
80 On each architecture, the main user mode thread's stack starts near
81 the highest user address and grows down.
84 architecture support varies by release.
85 This table shows the first
87 release to support each architecture, and, for discontinued
88 architectures, the final release.
90 .Bl -column -offset indent "Architecture" "Initial Release" "Final Release"
91 .It Sy Architecture Ta Sy Initial Release Ta Sy Final Release
93 .It alpha Ta 3.2 Ta 6.4
95 .It arm Ta 6.0 Ta 12.x
96 .It armeb Ta 8.0 Ta 11.x
99 .It ia64 Ta 5.0 Ta 10.4
108 .It mips64elhf Ta 12.0
110 .It pc98 Ta 2.2 Ta 11.x
112 .It powerpcspe Ta 12.0
115 .It riscv64sf Ta 12.0
116 .It sparc64 Ta 5.0 Ta 12.x
121 architectures use some variant of the ELF (see
123 .Sy Application Binary Interface
124 (ABI) for the machine processor.
125 All supported ABIs can be divided into two groups:
126 .Bl -tag -width "Dv ILP32"
131 types machine representations all have 4-byte size.
134 type machine representation uses 4 bytes,
142 Some machines support more than one
145 Typically these are 64-bit machines, where the
148 execution environment is accompanied by the
151 environment, which was the historical 32-bit predecessor for 64-bit evolution.
153 .Bl -column -offset indent "powerpc64" "ILP32 counterpart"
154 .It Sy LP64 Ta Sy ILP32 counterpart
155 .It Dv amd64 Ta Dv i386
156 .It Dv powerpc64 Ta Dv powerpc
157 .It Dv mips64* Ta Dv mips*
158 .It Dv aarch64 Ta Dv armv6/armv7
162 will support execution of
166 binaries if the CPU implements
168 execution state, however
170 binaries aren't supported.
172 On all supported architectures:
173 .Bl -column -offset -indent "long long" "Size"
174 .It Sy Type Ta Sy Size
177 .It long Ta sizeof(void*)
183 Integers are represented in two's complement.
184 Alignment of integer and pointer types is natural, that is,
185 the address of the variable must be congruent to zero modulo the type size.
186 Most ILP32 ABIs, except
188 require only 4-byte alignment for 64-bit integers.
190 Machine-dependent type sizes:
191 .Bl -column -offset indent "Architecture" "void *" "long double" "time_t"
192 .It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t
193 .It aarch64 Ta 8 Ta 16 Ta 8
194 .It amd64 Ta 8 Ta 16 Ta 8
195 .It armv6 Ta 4 Ta 8 Ta 8
196 .It armv7 Ta 4 Ta 8 Ta 8
197 .It i386 Ta 4 Ta 12 Ta 4
198 .It mips Ta 4 Ta 8 Ta 8
199 .It mipsel Ta 4 Ta 8 Ta 8
200 .It mipselhf Ta 4 Ta 8 Ta 8
201 .It mipshf Ta 4 Ta 8 Ta 8
202 .It mipsn32 Ta 4 Ta 8 Ta 8
203 .It mips64 Ta 8 Ta 8 Ta 8
204 .It mips64el Ta 8 Ta 8 Ta 8
205 .It mips64elhf Ta 8 Ta 8 Ta 8
206 .It mips64hf Ta 8 Ta 8 Ta 8
207 .It powerpc Ta 4 Ta 8 Ta 8
208 .It powerpcspe Ta 4 Ta 8 Ta 8
209 .It powerpc64 Ta 8 Ta 8 Ta 8
210 .It riscv64 Ta 8 Ta 16 Ta 8
211 .It riscv64sf Ta 8 Ta 16 Ta 8
215 is 8 bytes on all supported architectures except i386.
216 .Ss Endianness and Char Signedness
217 .Bl -column -offset indent "Architecture" "Endianness" "char Signedness"
218 .It Sy Architecture Ta Sy Endianness Ta Sy char Signedness
219 .It aarch64 Ta little Ta unsigned
220 .It amd64 Ta little Ta signed
221 .It armv6 Ta little Ta unsigned
222 .It armv7 Ta little Ta unsigned
223 .It i386 Ta little Ta signed
224 .It mips Ta big Ta signed
225 .It mipsel Ta little Ta signed
226 .It mipselhf Ta little Ta signed
227 .It mipshf Ta big Ta signed
228 .It mipsn32 Ta big Ta signed
229 .It mips64 Ta big Ta signed
230 .It mips64el Ta little Ta signed
231 .It mips64elhf Ta little Ta signed
232 .It mips64hf Ta big Ta signed
233 .It powerpc Ta big Ta unsigned
234 .It powerpcspe Ta big Ta unsigned
235 .It powerpc64 Ta big Ta unsigned
236 .It riscv64 Ta little Ta signed
237 .It riscv64sf Ta little Ta signed
240 .Bl -column -offset indent "Architecture" "Page Sizes"
241 .It Sy Architecture Ta Sy Page Sizes
242 .It aarch64 Ta 4K, 2M, 1G
243 .It amd64 Ta 4K, 2M, 1G
246 .It i386 Ta 4K, 2M (PAE), 4M
263 .Bl -column -offset indent "Architecture" "float, double" "long double"
264 .It Sy Architecture Ta Sy float, double Ta Sy long double
265 .It aarch64 Ta hard Ta soft, quad precision
266 .It amd64 Ta hard Ta hard, 80 bit
267 .It armv6 Ta hard Ta hard, double precision
268 .It armv7 Ta hard Ta hard, double precision
269 .It i386 Ta hard Ta hard, 80 bit
270 .It mips Ta soft Ta identical to double
271 .It mipsel Ta soft Ta identical to double
272 .It mipselhf Ta hard Ta identical to double
273 .It mipshf Ta hard Ta identical to double
274 .It mipsn32 Ta soft Ta identical to double
275 .It mips64 Ta soft Ta identical to double
276 .It mips64el Ta soft Ta identical to double
277 .It mips64elhf Ta hard Ta identical to double
278 .It mips64hf Ta hard Ta identical to double
279 .It powerpc Ta hard Ta hard, double precision
280 .It powerpcspe Ta hard Ta hard, double precision
281 .It powerpc64 Ta hard Ta hard, double precision
282 .It riscv64 Ta hard Ta hard, double precision
283 .It riscv64sf Ta soft Ta soft, double precision
285 .Ss Default Tool Chain
289 as the default compiler on all supported CPU architectures,
290 as well as ELF Tool Chain binary utilities such as
294 Most supported CPU architectures also use LLVM's
297 This table shows the default tool chain for each architecture.
298 .Bl -column -offset indent "Architecture" "Compiler" "Linker"
299 .It Sy Architecture Ta Sy Compiler Ta Sy Linker
300 .It aarch64 Ta Clang Ta lld
301 .It amd64 Ta Clang Ta lld
302 .It armv6 Ta Clang Ta lld
303 .It armv7 Ta Clang Ta lld
304 .It i386 Ta Clang Ta lld
305 .It mips Ta Clang Ta lld
306 .It mipsel Ta Clang Ta lld
307 .It mipselhf Ta Clang Ta lld
308 .It mipshf Ta Clang Ta lld
309 .It mipsn32 Ta Clang Ta lld
310 .It mips64 Ta Clang Ta lld
311 .It mips64el Ta Clang Ta lld
312 .It mips64elhf Ta Clang Ta lld
313 .It mips64hf Ta Clang Ta lld
314 .It powerpc Ta Clang Ta lld
315 .It powerpcspe Ta Clang Ta lld
316 .It powerpc64 Ta Clang Ta lld
317 .It riscv64 Ta Clang Ta lld
318 .It riscv64sf Ta Clang Ta lld
320 .Ss MACHINE_ARCH vs MACHINE_CPUARCH vs MACHINE
322 should be preferred in Makefiles when the generic
323 architecture is being tested.
325 should be preferred when there is something specific to a particular type of
326 architecture where there is a choice of many, or could be a choice of many.
329 when referring to the kernel, interfaces dependent on a specific type of kernel
330 or similar things like boot sequences.
331 .Bl -column -offset indent "Dv MACHINE" "Dv MACHINE_CPUARCH" "Dv MACHINE_ARCH"
332 .It Dv MACHINE Ta Dv MACHINE_CPUARCH Ta Dv MACHINE_ARCH
333 .It arm64 Ta aarch64 Ta aarch64
334 .It amd64 Ta amd64 Ta amd64
335 .It arm Ta arm Ta armv6, armv7
336 .It i386 Ta i386 Ta i386
337 .It mips Ta mips Ta mips, mipsel, mips64, mips64el, mipshf, mipselhf, mips64elhf, mipsn32
338 .It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64
339 .It riscv Ta riscv Ta riscv64, riscv64sf
341 .Ss Predefined Macros
342 The compiler provides a number of predefined macros.
343 Some of these provide architecture-specific details and are explained below.
344 Other macros, including those required by the language standard, are not
347 The full set of predefined macros can be obtained with this command:
348 .Bd -literal -offset indent
349 cc -x c -dM -E /dev/null
352 Common type size and endianness macros:
353 .Bl -column -offset indent "BYTE_ORDER" "Meaning"
354 .It Sy Macro Ta Sy Meaning
355 .It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int
356 .It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer
357 .It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN .
363 Architecture-specific macros:
364 .Bl -column -offset indent "Architecture" "Predefined macros"
365 .It Sy Architecture Ta Sy Predefined macros
366 .It aarch64 Ta Dv __aarch64__
367 .It amd64 Ta Dv __amd64__, Dv __x86_64__
368 .It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6
369 .It armv7 Ta Dv __arm__, Dv __ARM_ARCH >= 7
370 .It i386 Ta Dv __i386__
371 .It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32
372 .It mipsel Ta Dv __mips__, Dv __mips_o32
373 .It mipselhf Ta Dv __mips__, Dv __mips_o32
374 .It mipshf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32
375 .It mipsn32 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n32
376 .It mips64 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64
377 .It mips64el Ta Dv __mips__, Dv __mips_n64
378 .It mips64elhf Ta Dv __mips__, Dv __mips_n64
379 .It mips64hf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64
380 .It powerpc Ta Dv __powerpc__
381 .It powerpcspe Ta Dv __powerpc__, Dv __SPE__
382 .It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__
383 .It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64
384 .It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64
387 Compilers may define additional variants of architecture-specific macros.
388 The macros above are preferred for use in
390 .Ss Important Xr make 1 variables
391 Most of the externally settable variables are defined in the
394 These variables are not otherwise documented and are used extensively
396 .Bl -tag -width "MACHINE_CPUARCH"
398 Represents the hardware platform.
399 This is the same as the native platform's
403 It defines both the userland / kernel interface, as well as the
404 bootloader / kernel interface.
405 It should only be used in these contexts.
406 Each CPU architecture may have multiple hardware platforms it supports
410 It is used to collect together all the files from
413 It is often the same as
415 just as one CPU architecture can be implemented by many different
416 hardware platforms, one hardware platform may support multiple CPU
417 architecture family members, though with different binaries.
420 of i386 supported the IBM-AT hardware platform while the
422 of pc98 supported the Japanese company NEC's PC-9801 and PC-9821
424 Both of these hardware platforms supported only the
426 of i386 where they shared a common ABI, except for certain kernel /
427 userland interfaces relating to underlying hardware platform
428 differences in bus architecture, device enumeration and boot interface.
431 should only be used in src/sys and src/stand or in system imagers or
434 Represents the CPU processor architecture.
435 This is the same as the native platforms
439 It defines the CPU instruction family supported.
440 It may also encode a variation in the byte ordering of multi-byte
442 It may also encode a variation in the size of the integer or pointer.
443 It may also encode a ISA revision.
444 It may also encode hard versus soft floating point ABI and usage.
445 It may also encode a variant ABI when the other factors do not
446 uniquely define the ABI (e.g., MIPS' n32 ABI).
449 defines the ABI used by the system.
450 For example, the MIPS CPU processor family supports 9 different
451 combinations encoding pointer size, endian and hard versus soft float (for
452 8 combinations) as well as N32 (which only ever had one variation of
454 Generally, the plain CPU name specifies the most common (or at least
455 first) variant of the CPU.
456 This is why mips and mips64 imply 'big endian' while 'armv6' and 'armv7'
458 If we ever were to support the so-called x32 ABI (using 32-bit
459 pointers on the amd64 architecture), it would most likely be encoded
461 It is unfortunate that amd64 specifies the 64-bit evolution of the x86
462 platform (it matches the 'first rule') as everybody else uses x86_64.
463 There is no standard name for the processor: each OS selects its own
465 .It Dv MACHINE_CPUARCH
466 Represents the source location for a given
468 It is generally the common prefix for all the MACHINE_ARCH that
469 share the same implementation, though 'riscv' breaks this rule.
472 is defined to be mips for all the flavors of mips that we support
473 since we support them all with a shared set of sources.
474 While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86
476 The FreeBSD source base supports amd64 and i386 with two
477 distinct source bases living in subdirectories named amd64 and i386
478 (though behind the scenes there's some sharing that fits into this
484 It is used to optimize the build for a specific CPU / core that the
486 Generally, this does not change the ABI, though it can be a fine line
487 between optimization for specific cases.
491 in the top level Makefile for cross building.
492 Unused outside of that scope.
493 It is not passed down to the rest of the build.
494 Makefiles outside of the top level should not use it at all (though
495 some have their own private copy for hysterical raisons).
499 by the top level Makefile for cross building.
502 it is unused outside of that scope.
510 manual page appeared in