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34 .Nd Architecture-specific details
36 Differences between CPU architectures and platforms supported by
39 This document is a quick reference of key ABI details of
42 For full details consult the processor-specific ABI supplement
45 If not explicitly mentioned, sizes are in bytes.
46 The architecture details in this document apply to
48 and later, unless otherwise noted.
51 uses a flat address space.
57 and pointers all have the same representation.
59 In order to maximize compatibility with future pointer integrity mechanisms,
60 manipulations of pointers as integers should be performed via
71 On some architectures, e.g.
76 the kernel uses a separate address space.
77 On other architectures, kernel and a user mode process share a
79 The kernel is located at the highest addresses.
81 On each architecture, the main user mode thread's stack starts near
82 the highest user address and grows down.
85 architecture support varies by release.
86 This table shows the first
88 release to support each architecture, and, for discontinued
89 architectures, the final release.
91 .Bl -column -offset indent "Sy Architecture" "Sy Initial Release" "Sy Final Release"
92 .It Sy Architecture Ta Sy Initial Release Ta Sy Final Release
93 .It alpha Ta 3.2 Ta 6.4
99 .It ia64 Ta 5.0 Ta 10.x
108 .It mips64elhf Ta 12.0
110 .It pc98 Ta 2.2 Ta 11.x
112 .It powerpcspe Ta 12.0
115 .It riscv64sf Ta 12.0
121 architectures use some variant of the ELF (see
123 .Sy Application Binary Interface
124 (ABI) for the machine processor.
125 All supported ABIs can be divided into two groups:
126 .Bl -tag -width "Dv ILP32"
131 types machine representations all have 4-byte size.
134 type machine representation uses 4 bytes,
143 symbol when compiling for an
147 Some machines support more that one
150 Typically these are 64-bit machines, where the
153 execution environment is accompanied by the
156 environment, which was historical 32-bit predecessor for 64-bit evolution.
158 .Bl -column -offset indent "Dv powerpc64" "Sy ILP32 counterpart"
159 .It Sy LP64 Ta Sy ILP32 counterpart
160 .It Dv amd64 Ta Dv i386
161 .It Dv powerpc64 Ta Dv powerpc
162 .It Dv mips64* Ta Dv mips*
165 currently does not support execution of
167 binaries, even if the CPU implements
171 On all supported architectures:
172 .Bl -column -offset -indent "long long" "Size"
173 .It Sy Type Ta Sy Size
176 .It long Ta sizeof(void*)
181 Integers are represented in two's complement.
182 Alignment of integer and pointer types is natural, that is,
183 the address of the variable must be congruent to zero modulo the type size.
184 Most ILP32 ABIs, except
186 require only 4-byte alignment for 64-bit integers.
188 Machine-dependent type sizes:
189 .Bl -column -offset indent "Sy Architecture" "Sy void *" "Sy long double" "Sy time_t"
190 .It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t
191 .It amd64 Ta 8 Ta 16 Ta 8
192 .It arm Ta 4 Ta 8 Ta 8
193 .It armeb Ta 4 Ta 8 Ta 8
194 .It armv6 Ta 4 Ta 8 Ta 8
195 .It arm64 Ta 8 Ta 16 Ta 8
196 .It i386 Ta 4 Ta 12 Ta 4
197 .It mips Ta 4 Ta 8 Ta 8
198 .It mipsel Ta 4 Ta 8 Ta 8
199 .It mipselhf Ta 4 Ta 8 Ta 8
200 .It mipshf Ta 4 Ta 8 Ta 8
201 .It mipsn32 Ta 4 Ta 8 Ta 8
202 .It mips64 Ta 8 Ta 8 Ta 8
203 .It mips64el Ta 8 Ta 8 Ta 8
204 .It mips64elhf Ta 8 Ta 8 Ta 8
205 .It mips64hf Ta 8 Ta 8 Ta 8
206 .It powerpc Ta 4 Ta 8 Ta 8
207 .It powerpcspe Ta 4 Ta 8 Ta 8
208 .It powerpc64 Ta 8 Ta 8 Ta 8
209 .It riscv64 Ta 8 Ta 16 Ta 8
210 .It riscv64sf Ta 8 Ta 16 Ta 8
211 .It sparc64 Ta 8 Ta 16 Ta 8
215 is 8 bytes on all supported architectures except i386 and 32-bit
217 .Ss Endianness and Char Signedness
218 .Bl -column -offset indent "Sy Architecture" "Sy Endianness" "Sy char Signedness"
219 .It Sy Architecture Ta Sy Endianness Ta Sy char Signedness
220 .It amd64 Ta little Ta signed
221 .It arm Ta little Ta unsigned
222 .It armeb Ta big Ta unsigned
223 .It armv6 Ta little Ta unsigned
224 .It arm64 Ta little Ta unsigned
225 .It i386 Ta little Ta signed
226 .It mips Ta big Ta signed
227 .It mipsel Ta little Ta signed
228 .It mipselhf Ta little Ta signed
229 .It mipshf Ta big Ta signed
230 .It mipsn32 Ta big Ta signed
231 .It mips64 Ta big Ta signed
232 .It mips64el Ta little Ta signed
233 .It mips64elhf Ta little Ta signed
234 .It mips64hf Ta big Ta signed
235 .It powerpc Ta big Ta unsigned
236 .It powerpcspe Ta big Ta unsigned
237 .It powerpc64 Ta big Ta unsigned
238 .It riscv64 Ta little Ta signed
239 .It riscv64sf Ta little Ta signed
240 .It sparc64 Ta big Ta signed
243 .Bl -column -offset indent "Sy Architecture" "Sy Page Sizes"
244 .It Sy Architecture Ta Sy Page Sizes
245 .It amd64 Ta 4K, 2M, 1G
249 .It arm64 Ta 4K, 2M, 1G
250 .It i386 Ta 4K, 2M (PAE), 4M
268 .Bl -column -offset indent "Sy Architecture" "Sy float, double" "Sy long double"
269 .It Sy Architecture Ta Sy float, double Ta Sy long double
270 .It amd64 Ta hard Ta hard, 80 bit
271 .It arm Ta soft Ta soft, double precision
272 .It armeb Ta soft Ta soft, double precision
273 .It armv6 Ta hard(1) Ta hard, double precision
274 .It arm64 Ta hard Ta soft, quad precision
275 .It i386 Ta hard Ta hard, 80 bit
276 .It mips Ta soft Ta identical to double
277 .It mipsel Ta soft Ta identical to double
278 .It mipselhf Ta hard Ta identical to double
279 .It mipshf Ta hard Ta identical to double
280 .It mipsn32 Ta soft Ta identical to double
281 .It mips64 Ta soft Ta identical to double
282 .It mips64el Ta soft Ta identical to double
283 .It mips64elhf Ta hard Ta identical to double
284 .It mips64hf Ta hard Ta identical to double
285 .It powerpc Ta hard Ta hard, double precision
286 .It powerpcspe Ta hard Ta hard, double precision
287 .It powerpc64 Ta hard Ta hard, double precision
288 .It riscv64 Ta hard Ta hard, double precision
289 .It riscv64sf Ta soft Ta soft, double precision
290 .It sparc64 Ta hard Ta hard, quad precision
295 armv6 used the softfp ABI even though it supported only processors
296 with a floating point unit.
297 .Ss Predefined Macros
298 The compiler provides a number of predefined macros.
299 Some of these provide architecture-specific details and are explained below.
300 Other macros, including those required by the language standard, are not
303 The full set of predefined macros can be obtained with this command:
304 .Bd -literal -offset indent
305 cc -x c -dM -E /dev/null
308 Common type size and endianness macros:
309 .Bl -column -offset indent "BYTE_ORDER" "Sy Meaning"
310 .It Sy Macro Ta Sy Meaning
311 .It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int
312 .It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer
313 .It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN .
319 Architecture-specific macros:
320 .Bl -column -offset indent "Sy Architecture" "Sy Predefined macros"
321 .It Sy Architecture Ta Sy Predefined macros
322 .It amd64 Ta Dv __amd64__, Dv __x86_64__
323 .It arm Ta Dv __arm__
324 .It armeb Ta Dv __arm__
325 .It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6
326 .It arm64 Ta Dv __aarch64__
327 .It i386 Ta Dv __i386__
328 .It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32
329 .It mipsel Ta Dv __mips__, Dv __mips_o32
330 .It mipselhf Ta Dv __mips__, Dv __mips_o32
331 .It mipshf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32
332 .It mipsn32 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n32
333 .It mips64 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64
334 .It mips64el Ta Dv __mips__, Dv __mips_n64
335 .It mips64elhf Ta Dv __mips__, Dv __mips_n64
336 .It mips64hf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64
337 .It powerpc Ta Dv __powerpc__
338 .It powerpcspe Ta Dv __powerpc__, Dv __SPE__
339 .It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__
340 .It riscv64 Ta Dv __riscv__, Dv __riscv64
341 .It riscv64sf Ta Dv __riscv__, Dv __riscv64
342 .It sparc64 Ta Dv __sparc64__
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