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34 .Nd Architecture-specific details
36 Differences between CPU architectures and platforms supported by
39 This document is a quick reference of key ABI details of
42 For full details consult the processor-specific ABI supplement
45 If not explicitly mentioned, sizes are in bytes.
46 The architecture details in this document apply to
48 and later, unless otherwise noted.
51 uses a flat address space.
57 and pointers all have the same representation.
59 In order to maximize compatibility with future pointer integrity mechanisms,
60 manipulations of pointers as integers should be performed via
71 On some architectures, e.g.,
76 the kernel uses a separate address space.
77 On other architectures, kernel and a user mode process share a
79 The kernel is located at the highest addresses.
81 On each architecture, the main user mode thread's stack starts near
82 the highest user address and grows down.
85 architecture support varies by release.
86 This table shows the first
88 release to support each architecture, and, for discontinued
89 architectures, the final release.
91 .Bl -column -offset indent "Sy Architecture" "Sy Initial Release" "Sy Final Release"
92 .It Sy Architecture Ta Sy Initial Release Ta Sy Final Release
94 .It alpha Ta 3.2 Ta 6.4
96 .It arm Ta 6.0 Ta 12.x
97 .It armeb Ta 8.0 Ta 11.x
100 .It ia64 Ta 5.0 Ta 10.4
109 .It mips64elhf Ta 12.0
111 .It pc98 Ta 2.2 Ta 11.x
113 .It powerpcspe Ta 12.0
116 .It riscv64sf Ta 12.0
117 .It sparc64 Ta 5.0 Ta 12.x
122 architectures use some variant of the ELF (see
124 .Sy Application Binary Interface
125 (ABI) for the machine processor.
126 All supported ABIs can be divided into two groups:
127 .Bl -tag -width "Dv ILP32"
132 types machine representations all have 4-byte size.
135 type machine representation uses 4 bytes,
143 Some machines support more than one
146 Typically these are 64-bit machines, where the
149 execution environment is accompanied by the
152 environment, which was the historical 32-bit predecessor for 64-bit evolution.
154 .Bl -column -offset indent "Dv powerpc64" "Sy ILP32 counterpart"
155 .It Sy LP64 Ta Sy ILP32 counterpart
156 .It Dv amd64 Ta Dv i386
157 .It Dv powerpc64 Ta Dv powerpc
158 .It Dv mips64* Ta Dv mips*
159 .It Dv aarch64 Ta Dv armv6/armv7
163 will support execution of
167 binaries if the CPU implements
169 execution state, however
171 binaries aren't supported.
173 On all supported architectures:
174 .Bl -column -offset -indent "long long" "Size"
175 .It Sy Type Ta Sy Size
178 .It long Ta sizeof(void*)
184 Integers are represented in two's complement.
185 Alignment of integer and pointer types is natural, that is,
186 the address of the variable must be congruent to zero modulo the type size.
187 Most ILP32 ABIs, except
189 require only 4-byte alignment for 64-bit integers.
191 Machine-dependent type sizes:
192 .Bl -column -offset indent "Sy Architecture" "Sy void *" "Sy long double" "Sy time_t"
193 .It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t
194 .It aarch64 Ta 8 Ta 16 Ta 8
195 .It amd64 Ta 8 Ta 16 Ta 8
196 .It armv6 Ta 4 Ta 8 Ta 8
197 .It armv7 Ta 4 Ta 8 Ta 8
198 .It i386 Ta 4 Ta 12 Ta 4
199 .It mips Ta 4 Ta 8 Ta 8
200 .It mipsel Ta 4 Ta 8 Ta 8
201 .It mipselhf Ta 4 Ta 8 Ta 8
202 .It mipshf Ta 4 Ta 8 Ta 8
203 .It mipsn32 Ta 4 Ta 8 Ta 8
204 .It mips64 Ta 8 Ta 8 Ta 8
205 .It mips64el Ta 8 Ta 8 Ta 8
206 .It mips64elhf Ta 8 Ta 8 Ta 8
207 .It mips64hf Ta 8 Ta 8 Ta 8
208 .It powerpc Ta 4 Ta 8 Ta 8
209 .It powerpcspe Ta 4 Ta 8 Ta 8
210 .It powerpc64 Ta 8 Ta 8 Ta 8
211 .It riscv64 Ta 8 Ta 16 Ta 8
212 .It riscv64sf Ta 8 Ta 16 Ta 8
213 .It sparc64 Ta 8 Ta 16 Ta 8
217 is 8 bytes on all supported architectures except i386.
218 .Ss Endianness and Char Signedness
219 .Bl -column -offset indent "Sy Architecture" "Sy Endianness" "Sy char Signedness"
220 .It Sy Architecture Ta Sy Endianness Ta Sy char Signedness
221 .It aarch64 Ta little Ta unsigned
222 .It amd64 Ta little Ta signed
223 .It armv6 Ta little Ta unsigned
224 .It armv7 Ta little Ta unsigned
225 .It i386 Ta little Ta signed
226 .It mips Ta big Ta signed
227 .It mipsel Ta little Ta signed
228 .It mipselhf Ta little Ta signed
229 .It mipshf Ta big Ta signed
230 .It mipsn32 Ta big Ta signed
231 .It mips64 Ta big Ta signed
232 .It mips64el Ta little Ta signed
233 .It mips64elhf Ta little Ta signed
234 .It mips64hf Ta big Ta signed
235 .It powerpc Ta big Ta unsigned
236 .It powerpcspe Ta big Ta unsigned
237 .It powerpc64 Ta big Ta unsigned
238 .It riscv64 Ta little Ta signed
239 .It riscv64sf Ta little Ta signed
240 .It sparc64 Ta big Ta signed
243 .Bl -column -offset indent "Sy Architecture" "Sy Page Sizes"
244 .It Sy Architecture Ta Sy Page Sizes
245 .It aarch64 Ta 4K, 2M, 1G
246 .It amd64 Ta 4K, 2M, 1G
249 .It i386 Ta 4K, 2M (PAE), 4M
267 .Bl -column -offset indent "Sy Architecture" "Sy float, double" "Sy long double"
268 .It Sy Architecture Ta Sy float, double Ta Sy long double
269 .It aarch64 Ta hard Ta soft, quad precision
270 .It amd64 Ta hard Ta hard, 80 bit
271 .It armv6 Ta hard Ta hard, double precision
272 .It armv7 Ta hard Ta hard, double precision
273 .It i386 Ta hard Ta hard, 80 bit
274 .It mips Ta soft Ta identical to double
275 .It mipsel Ta soft Ta identical to double
276 .It mipselhf Ta hard Ta identical to double
277 .It mipshf Ta hard Ta identical to double
278 .It mipsn32 Ta soft Ta identical to double
279 .It mips64 Ta soft Ta identical to double
280 .It mips64el Ta soft Ta identical to double
281 .It mips64elhf Ta hard Ta identical to double
282 .It mips64hf Ta hard Ta identical to double
283 .It powerpc Ta hard Ta hard, double precision
284 .It powerpcspe Ta hard Ta hard, double precision
285 .It powerpc64 Ta hard Ta hard, double precision
286 .It riscv64 Ta hard Ta hard, double precision
287 .It riscv64sf Ta soft Ta soft, double precision
288 .It sparc64 Ta hard Ta hard, quad precision
290 .Ss Default Tool Chain
291 .Fx uses a variety of tool chain components for the supported CPU
296 provided by the base system,
301 or an external toolchain compiler and linker provided by a port or package.
302 This table shows the default tool chain for each architecture.
303 .Bl -column -offset indent "Sy Architecture" "Sy Compiler" "Sy Linker"
304 .It Sy Architecture Ta Sy Compiler Ta Sy Linker
305 .It aarch64 Ta Clang Ta lld
306 .It amd64 Ta Clang Ta lld
307 .It armv6 Ta Clang Ta lld
308 .It armv7 Ta Clang Ta lld
309 .It i386 Ta Clang Ta lld
310 .It mips Ta GCC(1) Ta GNU ld(1)
311 .It mipsel Ta GCC(1) Ta GNU ld(1)
312 .It mipselhf Ta GCC(1) Ta GNU ld(1)
313 .It mipshf Ta GCC(1) Ta GNU ld(1)
314 .It mipsn32 Ta GCC(1) Ta GNU ld(1)
315 .It mips64 Ta GCC(1) Ta GNU ld(1)
316 .It mips64el Ta GCC(1) Ta GNU ld(1)
317 .It mips64elhf Ta GCC(1) Ta GNU ld(1)
318 .It mips64hf Ta GCC(1) Ta GNU ld(1)
319 .It powerpc Ta Clang Ta GNU ld 2.17.50
320 .It powerpcspe Ta Clang Ta GNU ld 2.17.50
321 .It powerpc64 Ta Clang Ta lld
322 .It riscv64 Ta GCC(1) Ta GNU ld(1)
323 .It riscv64sf Ta GCC(1) Ta GNU ld(1)
324 .It sparc64 Ta GCC(1) Ta GNU ld(1)
327 (1) External toolchain provided by ports/packages.
329 Note that GCC 4.2.1 is deprecated, and scheduled for removal on 2020-03-31.
330 Any CPU architectures not migrated by then
331 (to either base system Clang or external toolchain)
332 may be removed from the tree after that date.
333 Unless the make variable
334 .Dv MAKE_OBSOLETE_GCC
335 is defined, make universe will not build mips or sparc64
336 architectures unless the xtoolchain binaries have been installed for
338 .Ss MACHINE_ARCH vs MACHINE_CPUARCH vs MACHINE
340 should be preferred in Makefiles when the generic
341 architecture is being tested.
343 should be preferred when there is something specific to a particular type of
344 architecture where there is a choice of many, or could be a choice of many.
347 when referring to the kernel, interfaces dependent on a specific type of kernel
348 or similar things like boot sequences.
349 .Bl -column -offset indent "Dv MACHINE" "Dv MACHINE_CPUARCH" "Dv MACHINE_ARCH"
350 .It Dv MACHINE Ta Dv MACHINE_CPUARCH Ta Dv MACHINE_ARCH
351 .It arm64 Ta aarch64 Ta aarch64
352 .It amd64 Ta amd64 Ta amd64
353 .It arm Ta arm Ta armv6, armv7
354 .It i386 Ta i386 Ta i386
355 .It mips Ta mips Ta mips, mipsel, mips64, mips64el, mipshf, mipselhf, mips64elhf, mipsn32
356 .It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64
357 .It riscv Ta riscv Ta riscv64, riscv64sf
358 .It sparc64 Ta sparc64 Ta sparc64
360 .Ss Predefined Macros
361 The compiler provides a number of predefined macros.
362 Some of these provide architecture-specific details and are explained below.
363 Other macros, including those required by the language standard, are not
366 The full set of predefined macros can be obtained with this command:
367 .Bd -literal -offset indent
368 cc -x c -dM -E /dev/null
371 Common type size and endianness macros:
372 .Bl -column -offset indent "BYTE_ORDER" "Sy Meaning"
373 .It Sy Macro Ta Sy Meaning
374 .It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int
375 .It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer
376 .It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN .
382 Architecture-specific macros:
383 .Bl -column -offset indent "Sy Architecture" "Sy Predefined macros"
384 .It Sy Architecture Ta Sy Predefined macros
385 .It aarch64 Ta Dv __aarch64__
386 .It amd64 Ta Dv __amd64__, Dv __x86_64__
387 .It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6
388 .It armv7 Ta Dv __arm__, Dv __ARM_ARCH >= 7
389 .It i386 Ta Dv __i386__
390 .It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32
391 .It mipsel Ta Dv __mips__, Dv __mips_o32
392 .It mipselhf Ta Dv __mips__, Dv __mips_o32
393 .It mipshf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32
394 .It mipsn32 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n32
395 .It mips64 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64
396 .It mips64el Ta Dv __mips__, Dv __mips_n64
397 .It mips64elhf Ta Dv __mips__, Dv __mips_n64
398 .It mips64hf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64
399 .It powerpc Ta Dv __powerpc__
400 .It powerpcspe Ta Dv __powerpc__, Dv __SPE__
401 .It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__
402 .It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64
403 .It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64
404 .It sparc64 Ta Dv __sparc64__
407 Compilers may define additional variants of architecture-specific macros.
408 The macros above are preferred for use in
410 .Ss Important Xr make 1 variables
411 Most of the externally settable variables are defined in the
414 These variables are not otherwise documented and are used extensively
416 .Bl -tag -width "MACHINE_CPUARCH"
418 Represents the hardware platform.
419 This is the same as the native platform's
423 It defines both the userland / kernel interface, as well as the
424 bootloader / kernel interface.
425 It should only be used in these contexts.
426 Each CPU architecture may have multiple hardware platforms it supports
430 It is used to collect together all the files from
433 It is often the same as
435 just as one CPU architecture can be implemented by many different
436 hardware platforms, one hardware platform may support multiple CPU
437 architecture family members, though with different binaries.
440 of i386 supported the IBM-AT hardware platform while the
442 of pc98 supported the Japanese company NEC's PC-9801 and PC-9821
444 Both of these hardware platforms supported only the
446 of i386 where they shared a common ABI, except for certain kernel /
447 userland interfaces relating to underlying hardware platform
448 differences in bus architecture, device enumeration and boot interface.
451 should only be used in src/sys and src/stand or in system imagers or
454 Represents the CPU processor architecture.
455 This is the same as the native platforms
459 It defines the CPU instruction family supported.
460 It may also encode a variation in the byte ordering of multi-byte
462 It may also encode a variation in the size of the integer or pointer.
463 It may also encode a ISA revision.
464 It may also encode hard versus soft floating point ABI and usage.
465 It may also encode a variant ABI when the other factors do not
466 uniquely define the ABI (e.g., MIPS' n32 ABI).
469 defines the ABI used by the system.
470 For example, the MIPS CPU processor family supports 9 different
471 combinations encoding pointer size, endian and hard versus soft float (for
472 8 combinations) as well as N32 (which only ever had one variation of
474 Generally, the plain CPU name specifies the most common (or at least
475 first) variant of the CPU.
476 This is why mips and mips64 imply 'big endian' while 'armv6' and 'armv7'
478 If we ever were to support the so-called x32 ABI (using 32-bit
479 pointers on the amd64 architecture), it would most likely be encoded
481 It is unfortunate that amd64 specifies the 64-bit evolution of the x86
482 platform (it matches the 'first rule') as everybody else uses x86_64.
483 There is no standard name for the processor: each OS selects its own
485 .It Dv MACHINE_CPUARCH
486 Represents the source location for a given
488 It is generally the common prefix for all the MACHINE_ARCH that
489 share the same implementation, though 'riscv' breaks this rule.
492 is defined to be mips for all the flavors of mips that we support
493 since we support them all with a shared set of sources.
494 While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86
496 The FreeBSD source base supports amd64 and i386 with two
497 distinct source bases living in subdirectories named amd64 and i386
498 (though behind the scenes there's some sharing that fits into this
504 It is used to optimize the build for a specific CPU / core that the
506 Generally, this does not change the ABI, though it can be a fine line
507 between optimization for specific cases.
511 in the top level Makefile for cross building.
512 Unused outside of that scope.
513 It is not passed down to the rest of the build.
514 Makefiles outside of the top level should not use it at all (though
515 some have their own private copy for hysterical raisons).
519 by the top level Makefile for cross building.
522 it is unused outside of that scope.
530 manual page appeared in