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34 .Nd Architecture-specific details
36 Differences between CPU architectures and platforms supported by
39 This document is a quick reference of key ABI details of
42 For full details consult the processor-specific ABI supplement
45 If not explicitly mentioned, sizes are in bytes.
46 The architecture details in this document apply to
48 and later, unless otherwise noted.
51 uses a flat address space.
57 and pointers all have the same representation.
59 In order to maximize compatibility with future pointer integrity mechanisms,
60 manipulations of pointers as integers should be performed via
71 On some architectures, e.g.,
76 the kernel uses a separate address space.
77 On other architectures, kernel and a user mode process share a
79 The kernel is located at the highest addresses.
81 On each architecture, the main user mode thread's stack starts near
82 the highest user address and grows down.
85 architecture support varies by release.
86 This table shows the first
88 release to support each architecture, and, for discontinued
89 architectures, the final release.
91 .Bl -column -offset indent "Sy Architecture" "Sy Initial Release" "Sy Final Release"
92 .It Sy Architecture Ta Sy Initial Release Ta Sy Final Release
93 .It alpha Ta 3.2 Ta 6.4
100 .It ia64 Ta 5.0 Ta 10.x
109 .It mips64elhf Ta 12.0
111 .It pc98 Ta 2.2 Ta 11.x
113 .It powerpcspe Ta 12.0
116 .It riscv64sf Ta 12.0
122 architectures use some variant of the ELF (see
124 .Sy Application Binary Interface
125 (ABI) for the machine processor.
126 All supported ABIs can be divided into two groups:
127 .Bl -tag -width "Dv ILP32"
132 types machine representations all have 4-byte size.
135 type machine representation uses 4 bytes,
144 symbol when compiling for an
148 Some machines support more that one
151 Typically these are 64-bit machines, where the
154 execution environment is accompanied by the
157 environment, which was historical 32-bit predecessor for 64-bit evolution.
159 .Bl -column -offset indent "Dv powerpc64" "Sy ILP32 counterpart"
160 .It Sy LP64 Ta Sy ILP32 counterpart
161 .It Dv amd64 Ta Dv i386
162 .It Dv powerpc64 Ta Dv powerpc
163 .It Dv mips64* Ta Dv mips*
166 currently does not support execution of
170 binaries, even if the CPU implements
174 On all supported architectures:
175 .Bl -column -offset -indent "long long" "Size"
176 .It Sy Type Ta Sy Size
179 .It long Ta sizeof(void*)
184 Integers are represented in two's complement.
185 Alignment of integer and pointer types is natural, that is,
186 the address of the variable must be congruent to zero modulo the type size.
187 Most ILP32 ABIs, except
189 require only 4-byte alignment for 64-bit integers.
191 Machine-dependent type sizes:
192 .Bl -column -offset indent "Sy Architecture" "Sy void *" "Sy long double" "Sy time_t"
193 .It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t
194 .It amd64 Ta 8 Ta 16 Ta 8
195 .It arm Ta 4 Ta 8 Ta 8
196 .It armeb Ta 4 Ta 8 Ta 8
197 .It armv6 Ta 4 Ta 8 Ta 8
198 .It arm64 Ta 8 Ta 16 Ta 8
199 .It i386 Ta 4 Ta 12 Ta 4
200 .It mips Ta 4 Ta 8 Ta 8
201 .It mipsel Ta 4 Ta 8 Ta 8
202 .It mipselhf Ta 4 Ta 8 Ta 8
203 .It mipshf Ta 4 Ta 8 Ta 8
204 .It mipsn32 Ta 4 Ta 8 Ta 8
205 .It mips64 Ta 8 Ta 8 Ta 8
206 .It mips64el Ta 8 Ta 8 Ta 8
207 .It mips64elhf Ta 8 Ta 8 Ta 8
208 .It mips64hf Ta 8 Ta 8 Ta 8
209 .It powerpc Ta 4 Ta 8 Ta 8
210 .It powerpcspe Ta 4 Ta 8 Ta 8
211 .It powerpc64 Ta 8 Ta 8 Ta 8
212 .It riscv64 Ta 8 Ta 16 Ta 8
213 .It riscv64sf Ta 8 Ta 16 Ta 8
214 .It sparc64 Ta 8 Ta 16 Ta 8
218 is 8 bytes on all supported architectures except i386.
219 .Ss Endianness and Char Signedness
220 .Bl -column -offset indent "Sy Architecture" "Sy Endianness" "Sy char Signedness"
221 .It Sy Architecture Ta Sy Endianness Ta Sy char Signedness
222 .It amd64 Ta little Ta signed
223 .It arm Ta little Ta unsigned
224 .It armeb Ta big Ta unsigned
225 .It armv6 Ta little Ta unsigned
226 .It armv7 Ta little Ta unsigned
227 .It arm64 Ta little Ta unsigned
228 .It i386 Ta little Ta signed
229 .It mips Ta big Ta signed
230 .It mipsel Ta little Ta signed
231 .It mipselhf Ta little Ta signed
232 .It mipshf Ta big Ta signed
233 .It mipsn32 Ta big Ta signed
234 .It mips64 Ta big Ta signed
235 .It mips64el Ta little Ta signed
236 .It mips64elhf Ta little Ta signed
237 .It mips64hf Ta big Ta signed
238 .It powerpc Ta big Ta unsigned
239 .It powerpcspe Ta big Ta unsigned
240 .It powerpc64 Ta big Ta unsigned
241 .It riscv64 Ta little Ta signed
242 .It riscv64sf Ta little Ta signed
243 .It sparc64 Ta big Ta signed
246 .Bl -column -offset indent "Sy Architecture" "Sy Page Sizes"
247 .It Sy Architecture Ta Sy Page Sizes
248 .It amd64 Ta 4K, 2M, 1G
253 .It arm64 Ta 4K, 2M, 1G
254 .It i386 Ta 4K, 2M (PAE), 4M
272 .Bl -column -offset indent "Sy Architecture" "Sy float, double" "Sy long double"
273 .It Sy Architecture Ta Sy float, double Ta Sy long double
274 .It amd64 Ta hard Ta hard, 80 bit
275 .It arm Ta soft Ta soft, double precision
276 .It armeb Ta soft Ta soft, double precision
277 .It armv6 Ta hard(1) Ta hard, double precision
278 .It armv7 Ta hard(1) Ta hard, double precision
279 .It arm64 Ta hard Ta soft, quad precision
280 .It i386 Ta hard Ta hard, 80 bit
281 .It mips Ta soft Ta identical to double
282 .It mipsel Ta soft Ta identical to double
283 .It mipselhf Ta hard Ta identical to double
284 .It mipshf Ta hard Ta identical to double
285 .It mipsn32 Ta soft Ta identical to double
286 .It mips64 Ta soft Ta identical to double
287 .It mips64el Ta soft Ta identical to double
288 .It mips64elhf Ta hard Ta identical to double
289 .It mips64hf Ta hard Ta identical to double
290 .It powerpc Ta hard Ta hard, double precision
291 .It powerpcspe Ta hard Ta hard, double precision
292 .It powerpc64 Ta hard Ta hard, double precision
293 .It riscv64 Ta hard Ta hard, double precision
294 .It riscv64sf Ta soft Ta soft, double precision
295 .It sparc64 Ta hard Ta hard, quad precision
300 armv6 used the softfp ABI even though it supported only processors
301 with a floating point unit.
302 .Ss Predefined Macros
303 The compiler provides a number of predefined macros.
304 Some of these provide architecture-specific details and are explained below.
305 Other macros, including those required by the language standard, are not
308 The full set of predefined macros can be obtained with this command:
309 .Bd -literal -offset indent
310 cc -x c -dM -E /dev/null
313 Common type size and endianness macros:
314 .Bl -column -offset indent "BYTE_ORDER" "Sy Meaning"
315 .It Sy Macro Ta Sy Meaning
316 .It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int
317 .It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer
318 .It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN .
324 Architecture-specific macros:
325 .Bl -column -offset indent "Sy Architecture" "Sy Predefined macros"
326 .It Sy Architecture Ta Sy Predefined macros
327 .It amd64 Ta Dv __amd64__, Dv __x86_64__
328 .It arm Ta Dv __arm__
329 .It armeb Ta Dv __arm__
330 .It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6
331 .It armv7 Ta Dv __arm__, Dv __ARM_ARCH >= 7
332 .It arm64 Ta Dv __aarch64__
333 .It i386 Ta Dv __i386__
334 .It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32
335 .It mipsel Ta Dv __mips__, Dv __mips_o32
336 .It mipselhf Ta Dv __mips__, Dv __mips_o32
337 .It mipshf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32
338 .It mipsn32 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n32
339 .It mips64 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64
340 .It mips64el Ta Dv __mips__, Dv __mips_n64
341 .It mips64elhf Ta Dv __mips__, Dv __mips_n64
342 .It mips64hf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64
343 .It powerpc Ta Dv __powerpc__
344 .It powerpcspe Ta Dv __powerpc__, Dv __SPE__
345 .It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__
346 .It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64
347 .It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64
348 .It sparc64 Ta Dv __sparc64__
350 .Ss Important Xr make 1 variables
351 Most of the externally settable variables are defined in the
354 These variables are not otherwise documented and are used extensively
356 .Bl -column -offset indent "Sy Variable" "Sy Meaning and usage"
357 .It Dv MACHINE Represent the hardware platform.
358 This is the same as the native platform's
362 It defines both the userland / kernel interface, as well as the
363 bootloader / kernel interface.
364 It should only be used in these contexts.
365 Each CPU architecture may have multiple hardware platforms it supports
369 It is used to collect together all the files from
372 It is often the same as
374 just as one CPU architecture can be implemented by many different
375 hardware platforms, one hardware platform may support multiple CPU
376 architecture family members, though with different binaries.
379 of i386 supported the IBM-AT hardware platform while the
381 of pc98 supported the Japanese company NEC's PC-9801 and PC-9821
383 Both of these hardware platforms supported only the
385 of i386 where they shared a common ABI, except for certain kernel /
386 userland interfaces relating to underlying hardware platform
387 differences in bus architecture, device enumeration and boot interface.
390 should only be used in src/sys and src/stand or in system imagers or
392 .It Dv MACHINE_ARCH Represents the CPU processor architecture.
393 This is the same as the native platforms
397 It defines the CPU instruction family supported.
398 It may also encode a variation in the byte ordering of multi-byte
400 It may also encode a variation in the size of the integer or pointer.
401 It may also encode a ISA revision.
402 It may also encode hard versus soft floating point ABI and usage.
403 It may also encode a variant ABI when the other factors do not
404 uniquely define the ABI (e.g., MIPS' n32 ABI).
407 defines the ABI used by the system.
408 For example, the MIPS CPU processor family supports 9 different
409 combinations encoding pointer size, endian and hard versus soft float (for
410 8 combinations) as well as N32 (which only ever had one variation of
412 Generally, the plain CPU name specifies the most common (or at least
413 first) variant of the CPU.
414 This is why mips and mips64 imply 'big endian' while 'arm' and 'armv7'
416 If we ever were to support the so-called x32 ABI (using 32-bit
417 pointers on the amd64 architecture), it would most likely be encoded
419 It is unfortunate that amd64 specifies the 64-bit evolution of the x86
420 platform (it matches the 'first rule') as everybody else uses x86_64.
421 There is no standard name for the processor: each OS selects its own
423 .It Dv MACHINE_CPUARCH Represents the source location for a given
427 is defined to be mips for all the flavors of mips that we support
428 since we support them all with a shared set of sources.
429 While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86
431 The FreeBSD source base supports amd64 and i386 with two
432 distinct source bases living in subdirectories named amd64 and i386
433 (though behind the scenes there's some sharing that fits into this
435 .It Dv CPUTYPE Sets the flavor of
438 It is used to optimize the build for a specific CPU / core that the
440 Generally, this does not change the ABI, though it can be a fine line
441 between optimization for specific cases.
442 .It Dv TARGET Used to set
444 in the top level Makefile for cross building.
445 Unused outside of that scope.
446 It is not passed down to the rest of the build.
447 Makefiles outside of the top level should not use it at all (though
448 some have their own private copy for hysterical raisons).
449 .It Dv TARGET_ARCH Used to set
451 by the top level Makefile for cross building.
453 .Dv TARGET , it is unused outside of that scope.
461 manual page appeared in