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33 .Nd "SMP-friendly kernel counter implementation"
39 .Fn counter_u64_alloc "int wait"
41 .Fn counter_u64_free "counter_u64_t c"
43 .Fn counter_u64_add "counter_u64_t c" "int64_t v"
49 .Fn counter_u64_add_protected "counter_u64_t c" "int64_t v"
51 .Fn counter_u64_fetch "counter_u64_t c"
53 .Fn counter_u64_zero "counter_u64_t c"
55 .Fn counter_ratecheck "struct counter_rate *cr" "int64_t limit"
57 .Fn SYSCTL_COUNTER_U64 parent nbr name access ptr descr
58 .Fn SYSCTL_ADD_COUNTER_U64 ctx parent nbr name access ptr descr
59 .Fn SYSCTL_COUNTER_U64_ARRAY parent nbr name access ptr len descr
60 .Fn SYSCTL_ADD_COUNTER_U64_ARRAY ctx parent nbr name access ptr len descr
63 is a generic facility to create counters
64 that can be utilized for any purpose (such as collecting statistical
68 is guaranteed to be lossless when several kernel threads do simultaneous
72 does not block the calling thread,
75 operations are used for the update, therefore the counters
76 can be used in any non-interrupt context.
79 has special optimisations for SMP environments, making
81 update faster than simple arithmetic on the global variable.
84 is considered suitable for accounting in the performance-critical
86 .Bl -tag -width indent
87 .It Fn counter_u64_alloc wait
88 Allocate a new 64-bit unsigned counter.
93 wait flag, should be either
99 is specified the operation may fail.
100 .It Fn counter_u64_free c
101 Free the previously allocated counter
103 .It Fn counter_u64_add c v
108 The KPI does not guarantee any protection from wraparound.
110 Enter mode that would allow the safe update of several counters via
111 .Fn counter_u64_add_protected .
112 On some machines this expands to
114 section, while on other is a nop.
116 .Sx IMPLEMENTATION DETAILS .
118 Exit mode for updating several counters.
119 .It Fn counter_u64_add_protected c v
121 .Fn counter_u64_add ,
122 but should be preceded by
124 .It Fn counter_u64_fetch c
125 Take a snapshot of counter
127 The data obtained is not guaranteed to reflect the real cumulative
128 value for any moment.
129 .It Fn counter_u64_zero c
133 .It Fn counter_ratecheck cr limit
134 The function is a multiprocessor-friendly version of
139 Returns non-negative value if the rate is not yet reached during the current
140 second, and a negative value otherwise.
141 If the limit was reached on previous second, but was just reset back to zero,
143 .Fn counter_ratecheck
144 returns number of events since previous reset.
145 .It Fn SYSCTL_COUNTER_U64 parent nbr name access ptr descr
148 oid that would represent a
152 argument should be a pointer to allocated
154 A read of the oid returns value obtained through
155 .Fn counter_u64_fetch .
156 Any write to the oid zeroes it.
157 .It Fn SYSCTL_ADD_COUNTER_U64 ctx parent nbr name access ptr descr
160 oid that would represent a
164 argument should be a pointer to allocated
166 A read of the oid returns value obtained through
167 .Fn counter_u64_fetch .
168 Any write to the oid zeroes it.
169 .It Fn SYSCTL_COUNTER_U64_ARRAY parent nbr name access ptr len descr
172 oid that would represent an array of
176 argument should be a pointer to allocated array of
177 .Vt counter_u64_t's .
180 argument should specify number of elements in the array.
181 A read of the oid returns len-sized array of
183 values obtained through
184 .Fn counter_u64_fetch .
185 Any write to the oid zeroes all array elements.
186 .It Fn SYSCTL_ADD_COUNTER_U64_ARRAY ctx parent nbr name access ptr len descr
189 oid that would represent an array of
193 argument should be a pointer to allocated array of
194 .Vt counter_u64_t's .
197 argument should specify number of elements in the array.
198 A read of the oid returns len-sized array of
200 values obtained through
201 .Fn counter_u64_fetch .
202 Any write to the oid zeroes all array elements.
204 .Sh IMPLEMENTATION DETAILS
207 is implemented using per-CPU data fields that are specially aligned
208 in memory, to avoid inter-CPU bus traffic due to shared use
209 of the variables between CPUs.
210 These are allocated using
214 The update operation only touches the field that is private to current CPU.
215 Fetch operation loops through all per-CPU fields and obtains a snapshot
220 update is implemented as a single instruction without lock semantics,
221 operating on the private data for the current CPU,
222 which is safe against preemption and interrupts.
224 On i386 architecture, when machine supports the cmpxchg8 instruction,
225 this instruction is used.
226 The multi-instruction sequence provides the same guarantees as the
227 amd64 single-instruction implementation.
229 On some architectures updating a counter require a
233 The following example creates a static counter array exported to
234 userspace through a sysctl:
235 .Bd -literal -offset indent
237 static counter_u64_t array[MY_SIZE];
238 SYSCTL_COUNTER_U64_ARRAY(_debug, OID_AUTO, counter_array, CTLFLAG_RW,
239 &array[0], MY_SIZE, "Test counter array");
251 facility first appeared in
257 facility was written by
260 .An Konstantin Belousov .