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33 .Nd "SMP-friendly kernel counter implementation"
39 .Fn counter_u64_alloc "int wait"
41 .Fn counter_u64_free "counter_u64_t c"
43 .Fn counter_u64_add "counter_u64_t c" "int64_t v"
49 .Fn counter_u64_add_protected "counter_u64_t c" "int64_t v"
51 .Fn counter_u64_fetch "counter_u64_t c"
53 .Fn counter_u64_zero "counter_u64_t c"
55 .Fn SYSCTL_COUNTER_U64 parent nbr name access ptr descr
56 .Fn SYSCTL_ADD_COUNTER_U64 ctx parent nbr name access ptr descr
57 .Fn SYSCTL_COUNTER_U64_ARRAY parent nbr name access ptr len descr
58 .Fn SYSCTL_ADD_COUNTER_U64_ARRAY ctx parent nbr name access ptr len descr
61 is a generic facility to create counters
62 that can be utilized for any purpose (such as collecting statistical
66 is guaranteed to be lossless when several kernel threads do simultaneous
70 does not block the calling thread,
73 operations are used for the update, therefore the counters
74 can be used in any non-interrupt context.
77 has special optimisations for SMP environments, making
79 update faster than simple arithmetic on the global variable.
82 is considered suitable for accounting in the performance-critical
84 .Bl -tag -width indent
85 .It Fn counter_u64_alloc wait
86 Allocate a new 64-bit unsigned counter.
91 wait flag, should be either
97 is specified the operation may fail.
98 .It Fn counter_u64_free c
99 Free the previously allocated counter
101 .It Fn counter_u64_add c v
106 The KPI does not guarantee any protection from wraparound.
108 Enter mode that would allow to safely update several counters via
109 .Fn counter_u64_add_protected .
110 On some machines this expands to
112 section, while on other is a nop.
114 .Sx IMPLEMENTATION DETAILS .
116 Exit mode for updating several counters.
117 .It Fn counter_u64_add_protected c v
119 .Fn counter_u64_add ,
120 but should be preceded by
122 .It Fn counter_u64_fetch c
123 Take a snapshot of counter
125 The data obtained is not guaranteed to reflect the real cumulative
126 value for any moment.
127 .It Fn counter_u64_zero c
131 .It Fn SYSCTL_COUNTER_U64 parent nbr name access ptr descr
134 oid that would represent a
138 argument should be a pointer to allocated
140 A read of the oid returns value obtained through
141 .Fn counter_u64_fetch .
142 Any write to the oid zeroes it.
143 .It Fn SYSCTL_ADD_COUNTER_U64 ctx parent nbr name access ptr descr
146 oid that would represent a
150 argument should be a pointer to allocated
152 A read of the oid returns value obtained through
153 .Fn counter_u64_fetch .
154 Any write to the oid zeroes it.
155 .It Fn SYSCTL_COUNTER_U64_ARRAY parent nbr name access ptr len descr
158 oid that would represent an array of
162 argument should be a pointer to allocated array of
163 .Vt counter_u64_t's .
166 argument should specify number of elements in the array.
167 A read of the oid returns len-sized array of
169 values obtained through
170 .Fn counter_u64_fetch .
171 Any write to the oid zeroes all array elements.
172 .It Fn SYSCTL_ADD_COUNTER_U64_ARRAY ctx parent nbr name access ptr len descr
175 oid that would represent an array of
179 argument should be a pointer to allocated array of
180 .Vt counter_u64_t's .
183 argument should specify number of elements in the array.
184 A read of the oid returns len-sized array of
186 values obtained through
187 .Fn counter_u64_fetch .
188 Any write to the oid zeroes all array elements.
190 .Sh IMPLEMENTATION DETAILS
193 is implemented using per-CPU data fields that are specially aligned
194 in memory, to avoid inter-CPU bus traffic due to shared use
195 of the variables between CPUs.
196 These are allocated using
200 The update operation only touches the field that is private to current CPU.
201 Fetch operation loops through all per-CPU fields and obtains a snapshot
206 update is implemented as a single instruction without lock semantics,
207 operating on the private data for the current CPU,
208 which is safe against preemption and interrupts.
210 On i386 architecture, when machine supports the cmpxchg8 instruction,
211 this instruction is used.
212 The multi-instruction sequence provides the same guarantees as the
213 amd64 single-instruction implementation.
215 On some architectures updating a counter require a
219 The following example creates a static counter array exported to
220 userspace through a sysctl:
221 .Bd -literal -offset indent
223 static counter_u64_t array[MY_SIZE];
224 SYSCTL_COUNTER_U64_ARRAY(_debug, OID_AUTO, counter_array, CTLFLAG_RW,
225 &array[0], MY_SIZE, "Test counter array");
238 facility first appeared in
244 facility was written by
247 .An Konstantin Belousov .