1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "lldb/Core/ArchSpec.h"
18 // Other libraries and framework includes
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Support/COFF.h"
21 #include "llvm/Support/ELF.h"
22 #include "llvm/Support/Host.h"
25 #include "lldb/Core/RegularExpression.h"
26 #include "lldb/Core/StringList.h"
27 #include "lldb/Host/Endian.h"
28 #include "lldb/Host/HostInfo.h"
29 #include "lldb/Target/Platform.h"
30 #include "lldb/Target/Process.h"
31 #include "lldb/Target/RegisterContext.h"
32 #include "lldb/Target/Thread.h"
33 #include "lldb/Utility/NameMatches.h"
34 #include "lldb/Utility/SafeMachO.h"
35 #include "Plugins/Process/Utility/ARMDefines.h"
36 #include "Plugins/Process/Utility/InstructionUtils.h"
39 using namespace lldb_private;
41 static bool cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match);
43 namespace lldb_private {
47 ByteOrder default_byte_order;
48 uint32_t addr_byte_size;
49 uint32_t min_opcode_byte_size;
50 uint32_t max_opcode_byte_size;
51 llvm::Triple::ArchType machine;
53 const char * const name;
56 } // namespace lldb_private
58 // This core information can be looked using the ArchSpec::Core as the index
59 static const CoreDefinition g_core_definitions[] =
61 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_generic , "arm" },
62 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4 , "armv4" },
63 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4t , "armv4t" },
64 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5 , "armv5" },
65 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5e , "armv5e" },
66 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5t , "armv5t" },
67 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv6 , "armv6" },
68 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv6m , "armv6m" },
69 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7 , "armv7" },
70 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7f , "armv7f" },
71 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7s , "armv7s" },
72 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7k , "armv7k" },
73 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7m , "armv7m" },
74 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7em , "armv7em" },
75 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_xscale , "xscale" },
76 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumb , "thumb" },
77 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv4t , "thumbv4t" },
78 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv5 , "thumbv5" },
79 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv5e , "thumbv5e" },
80 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv6 , "thumbv6" },
81 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv6m , "thumbv6m" },
82 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7 , "thumbv7" },
83 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7f , "thumbv7f" },
84 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7s , "thumbv7s" },
85 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7k , "thumbv7k" },
86 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7m , "thumbv7m" },
87 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7em , "thumbv7em" },
88 { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_arm64 , "arm64" },
89 { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_armv8 , "armv8" },
90 { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_aarch64 , "aarch64" },
92 // mips32, mips32r2, mips32r3, mips32r5, mips32r6
93 { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32 , "mips" },
94 { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r2 , "mipsr2" },
95 { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r3 , "mipsr3" },
96 { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r5 , "mipsr5" },
97 { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r6 , "mipsr6" },
98 { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el , "mipsel" },
99 { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r2el , "mipsr2el" },
100 { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r3el , "mipsr3el" },
101 { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r5el , "mipsr5el" },
102 { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r6el , "mipsr6el" },
104 // mips64, mips64r2, mips64r3, mips64r5, mips64r6
105 { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64 , "mips64" },
106 { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r2 , "mips64r2" },
107 { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r3 , "mips64r3" },
108 { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r5 , "mips64r5" },
109 { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r6 , "mips64r6" },
110 { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64el , "mips64el" },
111 { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r2el , "mips64r2el" },
112 { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r3el , "mips64r3el" },
113 { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r5el , "mips64r5el" },
114 { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r6el , "mips64r6el" },
116 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_generic , "powerpc" },
117 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc601 , "ppc601" },
118 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc602 , "ppc602" },
119 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603 , "ppc603" },
120 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603e , "ppc603e" },
121 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603ev , "ppc603ev" },
122 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604 , "ppc604" },
123 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604e , "ppc604e" },
124 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc620 , "ppc620" },
125 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc750 , "ppc750" },
126 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7400 , "ppc7400" },
127 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7450 , "ppc7450" },
128 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc970 , "ppc970" },
130 { eByteOrderBig , 8, 4, 4, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_generic , "powerpc64" },
131 { eByteOrderBig , 8, 4, 4, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_ppc970_64 , "ppc970-64" },
133 { eByteOrderBig , 8, 2, 6, llvm::Triple::systemz, ArchSpec::eCore_s390x_generic , "s390x" },
135 { eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc , ArchSpec::eCore_sparc_generic , "sparc" },
136 { eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, ArchSpec::eCore_sparc9_generic , "sparcv9" },
138 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i386 , "i386" },
139 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486 , "i486" },
140 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486sx , "i486sx" },
141 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i686 , "i686" },
143 { eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64 , "x86_64" },
144 { eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64h , "x86_64h" },
145 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_generic, "hexagon" },
146 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4" },
147 { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5" },
149 { eByteOrderLittle, 4, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach32 , "unknown-mach-32" },
150 { eByteOrderLittle, 8, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach64 , "unknown-mach-64" },
152 { eByteOrderBig , 4, 1, 1 , llvm::Triple::kalimba , ArchSpec::eCore_kalimba3 , "kalimba3" },
153 { eByteOrderLittle, 4, 1, 1 , llvm::Triple::kalimba , ArchSpec::eCore_kalimba4 , "kalimba4" },
154 { eByteOrderLittle, 4, 1, 1 , llvm::Triple::kalimba , ArchSpec::eCore_kalimba5 , "kalimba5" }
157 // Ensure that we have an entry in the g_core_definitions for each core. If you comment out an entry above,
158 // you will need to comment out the corresponding ArchSpec::Core enumeration.
159 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == ArchSpec::kNumCores, "make sure we have one core definition for each core");
161 struct ArchDefinitionEntry
170 struct ArchDefinition
172 ArchitectureType type;
174 const ArchDefinitionEntry *entries;
179 ArchSpec::AutoComplete (const char *name, StringList &matches)
183 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
185 if (NameMatches(g_core_definitions[i].name, eNameMatchStartsWith, name))
186 matches.AppendString (g_core_definitions[i].name);
191 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
192 matches.AppendString (g_core_definitions[i].name);
194 return matches.GetSize();
197 #define CPU_ANY (UINT32_MAX)
199 //===----------------------------------------------------------------------===//
200 // A table that gets searched linearly for matches. This table is used to
201 // convert cpu type and subtypes to architecture names, and to convert
202 // architecture names to cpu types and subtypes. The ordering is important and
203 // allows the precedence to be set when the table is built.
204 #define SUBTYPE_MASK 0x00FFFFFFu
206 static const ArchDefinitionEntry g_macho_arch_entries[] =
208 { ArchSpec::eCore_arm_generic , llvm::MachO::CPU_TYPE_ARM , CPU_ANY, UINT32_MAX , UINT32_MAX },
209 { ArchSpec::eCore_arm_generic , llvm::MachO::CPU_TYPE_ARM , 0 , UINT32_MAX , SUBTYPE_MASK },
210 { ArchSpec::eCore_arm_armv4 , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
211 { ArchSpec::eCore_arm_armv4t , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
212 { ArchSpec::eCore_arm_armv6 , llvm::MachO::CPU_TYPE_ARM , 6 , UINT32_MAX , SUBTYPE_MASK },
213 { ArchSpec::eCore_arm_armv6m , llvm::MachO::CPU_TYPE_ARM , 14 , UINT32_MAX , SUBTYPE_MASK },
214 { ArchSpec::eCore_arm_armv5 , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
215 { ArchSpec::eCore_arm_armv5e , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
216 { ArchSpec::eCore_arm_armv5t , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
217 { ArchSpec::eCore_arm_xscale , llvm::MachO::CPU_TYPE_ARM , 8 , UINT32_MAX , SUBTYPE_MASK },
218 { ArchSpec::eCore_arm_armv7 , llvm::MachO::CPU_TYPE_ARM , 9 , UINT32_MAX , SUBTYPE_MASK },
219 { ArchSpec::eCore_arm_armv7f , llvm::MachO::CPU_TYPE_ARM , 10 , UINT32_MAX , SUBTYPE_MASK },
220 { ArchSpec::eCore_arm_armv7s , llvm::MachO::CPU_TYPE_ARM , 11 , UINT32_MAX , SUBTYPE_MASK },
221 { ArchSpec::eCore_arm_armv7k , llvm::MachO::CPU_TYPE_ARM , 12 , UINT32_MAX , SUBTYPE_MASK },
222 { ArchSpec::eCore_arm_armv7m , llvm::MachO::CPU_TYPE_ARM , 15 , UINT32_MAX , SUBTYPE_MASK },
223 { ArchSpec::eCore_arm_armv7em , llvm::MachO::CPU_TYPE_ARM , 16 , UINT32_MAX , SUBTYPE_MASK },
224 { ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 1 , UINT32_MAX , SUBTYPE_MASK },
225 { ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 0 , UINT32_MAX , SUBTYPE_MASK },
226 { ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 13 , UINT32_MAX , SUBTYPE_MASK },
227 { ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , CPU_ANY, UINT32_MAX , SUBTYPE_MASK },
228 { ArchSpec::eCore_thumb , llvm::MachO::CPU_TYPE_ARM , 0 , UINT32_MAX , SUBTYPE_MASK },
229 { ArchSpec::eCore_thumbv4t , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
230 { ArchSpec::eCore_thumbv5 , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
231 { ArchSpec::eCore_thumbv5e , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
232 { ArchSpec::eCore_thumbv6 , llvm::MachO::CPU_TYPE_ARM , 6 , UINT32_MAX , SUBTYPE_MASK },
233 { ArchSpec::eCore_thumbv6m , llvm::MachO::CPU_TYPE_ARM , 14 , UINT32_MAX , SUBTYPE_MASK },
234 { ArchSpec::eCore_thumbv7 , llvm::MachO::CPU_TYPE_ARM , 9 , UINT32_MAX , SUBTYPE_MASK },
235 { ArchSpec::eCore_thumbv7f , llvm::MachO::CPU_TYPE_ARM , 10 , UINT32_MAX , SUBTYPE_MASK },
236 { ArchSpec::eCore_thumbv7s , llvm::MachO::CPU_TYPE_ARM , 11 , UINT32_MAX , SUBTYPE_MASK },
237 { ArchSpec::eCore_thumbv7k , llvm::MachO::CPU_TYPE_ARM , 12 , UINT32_MAX , SUBTYPE_MASK },
238 { ArchSpec::eCore_thumbv7m , llvm::MachO::CPU_TYPE_ARM , 15 , UINT32_MAX , SUBTYPE_MASK },
239 { ArchSpec::eCore_thumbv7em , llvm::MachO::CPU_TYPE_ARM , 16 , UINT32_MAX , SUBTYPE_MASK },
240 { ArchSpec::eCore_ppc_generic , llvm::MachO::CPU_TYPE_POWERPC , CPU_ANY, UINT32_MAX , UINT32_MAX },
241 { ArchSpec::eCore_ppc_generic , llvm::MachO::CPU_TYPE_POWERPC , 0 , UINT32_MAX , SUBTYPE_MASK },
242 { ArchSpec::eCore_ppc_ppc601 , llvm::MachO::CPU_TYPE_POWERPC , 1 , UINT32_MAX , SUBTYPE_MASK },
243 { ArchSpec::eCore_ppc_ppc602 , llvm::MachO::CPU_TYPE_POWERPC , 2 , UINT32_MAX , SUBTYPE_MASK },
244 { ArchSpec::eCore_ppc_ppc603 , llvm::MachO::CPU_TYPE_POWERPC , 3 , UINT32_MAX , SUBTYPE_MASK },
245 { ArchSpec::eCore_ppc_ppc603e , llvm::MachO::CPU_TYPE_POWERPC , 4 , UINT32_MAX , SUBTYPE_MASK },
246 { ArchSpec::eCore_ppc_ppc603ev , llvm::MachO::CPU_TYPE_POWERPC , 5 , UINT32_MAX , SUBTYPE_MASK },
247 { ArchSpec::eCore_ppc_ppc604 , llvm::MachO::CPU_TYPE_POWERPC , 6 , UINT32_MAX , SUBTYPE_MASK },
248 { ArchSpec::eCore_ppc_ppc604e , llvm::MachO::CPU_TYPE_POWERPC , 7 , UINT32_MAX , SUBTYPE_MASK },
249 { ArchSpec::eCore_ppc_ppc620 , llvm::MachO::CPU_TYPE_POWERPC , 8 , UINT32_MAX , SUBTYPE_MASK },
250 { ArchSpec::eCore_ppc_ppc750 , llvm::MachO::CPU_TYPE_POWERPC , 9 , UINT32_MAX , SUBTYPE_MASK },
251 { ArchSpec::eCore_ppc_ppc7400 , llvm::MachO::CPU_TYPE_POWERPC , 10 , UINT32_MAX , SUBTYPE_MASK },
252 { ArchSpec::eCore_ppc_ppc7450 , llvm::MachO::CPU_TYPE_POWERPC , 11 , UINT32_MAX , SUBTYPE_MASK },
253 { ArchSpec::eCore_ppc_ppc970 , llvm::MachO::CPU_TYPE_POWERPC , 100 , UINT32_MAX , SUBTYPE_MASK },
254 { ArchSpec::eCore_ppc64_generic , llvm::MachO::CPU_TYPE_POWERPC64 , 0 , UINT32_MAX , SUBTYPE_MASK },
255 { ArchSpec::eCore_ppc64_ppc970_64 , llvm::MachO::CPU_TYPE_POWERPC64 , 100 , UINT32_MAX , SUBTYPE_MASK },
256 { ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPU_TYPE_I386 , 3 , UINT32_MAX , SUBTYPE_MASK },
257 { ArchSpec::eCore_x86_32_i486 , llvm::MachO::CPU_TYPE_I386 , 4 , UINT32_MAX , SUBTYPE_MASK },
258 { ArchSpec::eCore_x86_32_i486sx , llvm::MachO::CPU_TYPE_I386 , 0x84 , UINT32_MAX , SUBTYPE_MASK },
259 { ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPU_TYPE_I386 , CPU_ANY, UINT32_MAX , UINT32_MAX },
260 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , 3 , UINT32_MAX , SUBTYPE_MASK },
261 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , 4 , UINT32_MAX , SUBTYPE_MASK },
262 { ArchSpec::eCore_x86_64_x86_64h , llvm::MachO::CPU_TYPE_X86_64 , 8 , UINT32_MAX , SUBTYPE_MASK },
263 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , CPU_ANY, UINT32_MAX , UINT32_MAX },
264 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
265 { ArchSpec::eCore_uknownMach32 , 0 , 0 , 0xFF000000u, 0x00000000u },
266 { ArchSpec::eCore_uknownMach64 , llvm::MachO::CPU_ARCH_ABI64 , 0 , 0xFF000000u, 0x00000000u }
269 static const ArchDefinition g_macho_arch_def = {
271 llvm::array_lengthof(g_macho_arch_entries),
272 g_macho_arch_entries,
276 //===----------------------------------------------------------------------===//
277 // A table that gets searched linearly for matches. This table is used to
278 // convert cpu type and subtypes to architecture names, and to convert
279 // architecture names to cpu types and subtypes. The ordering is important and
280 // allows the precedence to be set when the table is built.
281 static const ArchDefinitionEntry g_elf_arch_entries[] =
283 { ArchSpec::eCore_sparc_generic , llvm::ELF::EM_SPARC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Sparc
284 { ArchSpec::eCore_x86_32_i386 , llvm::ELF::EM_386 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 80386
285 { ArchSpec::eCore_x86_32_i486 , llvm::ELF::EM_IAMCU , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel MCU // FIXME: is this correct?
286 { ArchSpec::eCore_ppc_generic , llvm::ELF::EM_PPC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC
287 { ArchSpec::eCore_ppc64_generic , llvm::ELF::EM_PPC64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC64
288 { ArchSpec::eCore_arm_generic , llvm::ELF::EM_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM
289 { ArchSpec::eCore_arm_aarch64 , llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM64
290 { ArchSpec::eCore_s390x_generic , llvm::ELF::EM_S390 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // SystemZ
291 { ArchSpec::eCore_sparc9_generic , llvm::ELF::EM_SPARCV9, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // SPARC V9
292 { ArchSpec::eCore_x86_64_x86_64 , llvm::ELF::EM_X86_64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // AMD64
293 { ArchSpec::eCore_mips32 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32
294 { ArchSpec::eCore_mips32r2 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32r2
295 { ArchSpec::eCore_mips32r6 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32r6
296 { ArchSpec::eCore_mips32el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32el
297 { ArchSpec::eCore_mips32r2el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32r2el
298 { ArchSpec::eCore_mips32r6el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips32r6el
299 { ArchSpec::eCore_mips64 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64
300 { ArchSpec::eCore_mips64r2 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64r2
301 { ArchSpec::eCore_mips64r6 , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64r6
302 { ArchSpec::eCore_mips64el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64el
303 { ArchSpec::eCore_mips64r2el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64r2el
304 { ArchSpec::eCore_mips64r6el , llvm::ELF::EM_MIPS , ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu }, // mips64r6el
305 { ArchSpec::eCore_hexagon_generic , llvm::ELF::EM_HEXAGON, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // HEXAGON
306 { ArchSpec::eCore_kalimba3 , llvm::ELF::EM_CSR_KALIMBA, llvm::Triple::KalimbaSubArch_v3, 0xFFFFFFFFu, 0xFFFFFFFFu }, // KALIMBA
307 { ArchSpec::eCore_kalimba4 , llvm::ELF::EM_CSR_KALIMBA, llvm::Triple::KalimbaSubArch_v4, 0xFFFFFFFFu, 0xFFFFFFFFu }, // KALIMBA
308 { ArchSpec::eCore_kalimba5 , llvm::ELF::EM_CSR_KALIMBA, llvm::Triple::KalimbaSubArch_v5, 0xFFFFFFFFu, 0xFFFFFFFFu } // KALIMBA
311 static const ArchDefinition g_elf_arch_def = {
313 llvm::array_lengthof(g_elf_arch_entries),
318 static const ArchDefinitionEntry g_coff_arch_entries[] =
320 { ArchSpec::eCore_x86_32_i386 , llvm::COFF::IMAGE_FILE_MACHINE_I386 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 80x86
321 { ArchSpec::eCore_ppc_generic , llvm::COFF::IMAGE_FILE_MACHINE_POWERPC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC
322 { ArchSpec::eCore_ppc_generic , llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC (with FPU)
323 { ArchSpec::eCore_arm_generic , llvm::COFF::IMAGE_FILE_MACHINE_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM
324 { ArchSpec::eCore_arm_armv7 , llvm::COFF::IMAGE_FILE_MACHINE_ARMNT , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARMv7
325 { ArchSpec::eCore_thumb , llvm::COFF::IMAGE_FILE_MACHINE_THUMB , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARMv7
326 { ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu } // AMD64
329 static const ArchDefinition g_coff_arch_def = {
331 llvm::array_lengthof(g_coff_arch_entries),
336 //===----------------------------------------------------------------------===//
337 // Table of all ArchDefinitions
338 static const ArchDefinition *g_arch_definitions[] = {
344 static const size_t k_num_arch_definitions = llvm::array_lengthof(g_arch_definitions);
346 //===----------------------------------------------------------------------===//
347 // Static helper functions.
349 // Get the architecture definition for a given object type.
350 static const ArchDefinition *
351 FindArchDefinition (ArchitectureType arch_type)
353 for (unsigned int i = 0; i < k_num_arch_definitions; ++i)
355 const ArchDefinition *def = g_arch_definitions[i];
356 if (def->type == arch_type)
362 // Get an architecture definition by name.
363 static const CoreDefinition *
364 FindCoreDefinition (llvm::StringRef name)
366 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i)
368 if (name.equals_lower(g_core_definitions[i].name))
369 return &g_core_definitions[i];
374 static inline const CoreDefinition *
375 FindCoreDefinition (ArchSpec::Core core)
377 if (core >= 0 && core < llvm::array_lengthof(g_core_definitions))
378 return &g_core_definitions[core];
382 // Get a definition entry by cpu type and subtype.
383 static const ArchDefinitionEntry *
384 FindArchDefinitionEntry (const ArchDefinition *def, uint32_t cpu, uint32_t sub)
389 const ArchDefinitionEntry *entries = def->entries;
390 for (size_t i = 0; i < def->num_entries; ++i)
392 if (entries[i].cpu == (cpu & entries[i].cpu_mask))
393 if (entries[i].sub == (sub & entries[i].sub_mask))
399 static const ArchDefinitionEntry *
400 FindArchDefinitionEntry (const ArchDefinition *def, ArchSpec::Core core)
405 const ArchDefinitionEntry *entries = def->entries;
406 for (size_t i = 0; i < def->num_entries; ++i)
408 if (entries[i].core == core)
414 //===----------------------------------------------------------------------===//
415 // Constructors and destructors.
417 ArchSpec::ArchSpec() :
419 m_core (kCore_invalid),
420 m_byte_order (eByteOrderInvalid),
426 ArchSpec::ArchSpec (const char *triple_cstr, Platform *platform) :
428 m_core (kCore_invalid),
429 m_byte_order (eByteOrderInvalid),
434 SetTriple(triple_cstr, platform);
438 ArchSpec::ArchSpec (const char *triple_cstr) :
440 m_core (kCore_invalid),
441 m_byte_order (eByteOrderInvalid),
446 SetTriple(triple_cstr);
449 ArchSpec::ArchSpec(const llvm::Triple &triple) :
451 m_core (kCore_invalid),
452 m_byte_order (eByteOrderInvalid),
459 ArchSpec::ArchSpec (ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) :
461 m_core (kCore_invalid),
462 m_byte_order (eByteOrderInvalid),
466 SetArchitecture (arch_type, cpu, subtype);
469 ArchSpec::~ArchSpec() = default;
471 //===----------------------------------------------------------------------===//
472 // Assignment and initialization.
475 ArchSpec::operator= (const ArchSpec& rhs)
479 m_triple = rhs.m_triple;
481 m_byte_order = rhs.m_byte_order;
482 m_distribution_id = rhs.m_distribution_id;
483 m_flags = rhs.m_flags;
491 m_triple = llvm::Triple();
492 m_core = kCore_invalid;
493 m_byte_order = eByteOrderInvalid;
494 m_distribution_id.Clear ();
498 //===----------------------------------------------------------------------===//
502 ArchSpec::GetArchitectureName () const
504 const CoreDefinition *core_def = FindCoreDefinition (m_core);
506 return core_def->name;
511 ArchSpec::IsMIPS() const
513 const llvm::Triple::ArchType machine = GetMachine();
514 if(machine == llvm::Triple::mips ||
515 machine == llvm::Triple::mipsel ||
516 machine == llvm::Triple::mips64 ||
517 machine == llvm::Triple::mips64el)
523 ArchSpec::GetClangTargetCPU ()
526 const llvm::Triple::ArchType machine = GetMachine();
528 if (machine == llvm::Triple::mips ||
529 machine == llvm::Triple::mipsel ||
530 machine == llvm::Triple::mips64 ||
531 machine == llvm::Triple::mips64el)
535 case ArchSpec::eCore_mips32:
536 case ArchSpec::eCore_mips32el:
537 cpu = "mips32"; break;
538 case ArchSpec::eCore_mips32r2:
539 case ArchSpec::eCore_mips32r2el:
540 cpu = "mips32r2"; break;
541 case ArchSpec::eCore_mips32r3:
542 case ArchSpec::eCore_mips32r3el:
543 cpu = "mips32r3"; break;
544 case ArchSpec::eCore_mips32r5:
545 case ArchSpec::eCore_mips32r5el:
546 cpu = "mips32r5"; break;
547 case ArchSpec::eCore_mips32r6:
548 case ArchSpec::eCore_mips32r6el:
549 cpu = "mips32r6"; break;
550 case ArchSpec::eCore_mips64:
551 case ArchSpec::eCore_mips64el:
552 cpu = "mips64"; break;
553 case ArchSpec::eCore_mips64r2:
554 case ArchSpec::eCore_mips64r2el:
555 cpu = "mips64r2"; break;
556 case ArchSpec::eCore_mips64r3:
557 case ArchSpec::eCore_mips64r3el:
558 cpu = "mips64r3"; break;
559 case ArchSpec::eCore_mips64r5:
560 case ArchSpec::eCore_mips64r5el:
561 cpu = "mips64r5"; break;
562 case ArchSpec::eCore_mips64r6:
563 case ArchSpec::eCore_mips64r6el:
564 cpu = "mips64r6"; break;
573 ArchSpec::GetMachOCPUType () const
575 const CoreDefinition *core_def = FindCoreDefinition (m_core);
578 const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core);
581 return arch_def->cpu;
584 return LLDB_INVALID_CPUTYPE;
588 ArchSpec::GetMachOCPUSubType () const
590 const CoreDefinition *core_def = FindCoreDefinition (m_core);
593 const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core);
596 return arch_def->sub;
599 return LLDB_INVALID_CPUTYPE;
603 ArchSpec::GetDataByteSize () const
620 ArchSpec::GetCodeByteSize () const
636 llvm::Triple::ArchType
637 ArchSpec::GetMachine () const
639 const CoreDefinition *core_def = FindCoreDefinition (m_core);
641 return core_def->machine;
643 return llvm::Triple::UnknownArch;
647 ArchSpec::GetDistributionId () const
649 return m_distribution_id;
653 ArchSpec::SetDistributionId (const char* distribution_id)
655 m_distribution_id.SetCString (distribution_id);
659 ArchSpec::GetAddressByteSize() const
661 const CoreDefinition *core_def = FindCoreDefinition (m_core);
664 if (core_def->machine == llvm::Triple::mips64 || core_def->machine == llvm::Triple::mips64el)
666 // For N32/O32 applications Address size is 4 bytes.
667 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32))
670 return core_def->addr_byte_size;
676 ArchSpec::GetDefaultEndian () const
678 const CoreDefinition *core_def = FindCoreDefinition (m_core);
680 return core_def->default_byte_order;
681 return eByteOrderInvalid;
685 ArchSpec::CharIsSignedByDefault () const
687 switch (m_triple.getArch()) {
691 case llvm::Triple::aarch64:
692 case llvm::Triple::aarch64_be:
693 case llvm::Triple::arm:
694 case llvm::Triple::armeb:
695 case llvm::Triple::thumb:
696 case llvm::Triple::thumbeb:
697 return m_triple.isOSDarwin() || m_triple.isOSWindows();
699 case llvm::Triple::ppc:
700 case llvm::Triple::ppc64:
701 return m_triple.isOSDarwin();
703 case llvm::Triple::ppc64le:
704 case llvm::Triple::systemz:
705 case llvm::Triple::xcore:
711 ArchSpec::GetByteOrder () const
713 if (m_byte_order == eByteOrderInvalid)
714 return GetDefaultEndian();
718 //===----------------------------------------------------------------------===//
722 ArchSpec::SetTriple (const llvm::Triple &triple)
726 llvm::StringRef arch_name (m_triple.getArchName());
727 const CoreDefinition *core_def = FindCoreDefinition (arch_name);
730 m_core = core_def->core;
731 // Set the byte order to the default byte order for an architecture.
732 // This can be modified if needed for cases when cores handle both
733 // big and little endian
734 m_byte_order = core_def->default_byte_order;
745 ParseMachCPUDashSubtypeTriple (const char *triple_cstr, ArchSpec &arch)
747 // Accept "12-10" or "12.10" as cpu type/subtype
748 if (isdigit(triple_cstr[0]))
752 uint32_t cpu = (uint32_t)::strtoul (triple_cstr, &end, 0);
753 if (errno == 0 && cpu != 0 && end && ((*end == '-') || (*end == '.')))
756 uint32_t sub = (uint32_t)::strtoul (end + 1, &end, 0);
757 if (errno == 0 && end && ((*end == '-') || (*end == '.') || (*end == '\0')))
759 if (arch.SetArchitecture (eArchTypeMachO, cpu, sub))
763 llvm::StringRef vendor_os (end + 1);
764 size_t dash_pos = vendor_os.find('-');
765 if (dash_pos != llvm::StringRef::npos)
767 llvm::StringRef vendor_str(vendor_os.substr(0, dash_pos));
768 arch.GetTriple().setVendorName(vendor_str);
769 const size_t vendor_start_pos = dash_pos+1;
770 dash_pos = vendor_os.find('-', vendor_start_pos);
771 if (dash_pos == llvm::StringRef::npos)
773 if (vendor_start_pos < vendor_os.size())
774 arch.GetTriple().setOSName(vendor_os.substr(vendor_start_pos));
778 arch.GetTriple().setOSName(vendor_os.substr(vendor_start_pos, dash_pos - vendor_start_pos));
791 ArchSpec::SetTriple (const char *triple_cstr)
793 if (triple_cstr && triple_cstr[0])
795 if (ParseMachCPUDashSubtypeTriple (triple_cstr, *this))
798 llvm::StringRef triple_stref (triple_cstr);
799 if (triple_stref.startswith (LLDB_ARCH_DEFAULT))
801 // Special case for the current host default architectures...
802 if (triple_stref.equals (LLDB_ARCH_DEFAULT_32BIT))
803 *this = HostInfo::GetArchitecture(HostInfo::eArchKind32);
804 else if (triple_stref.equals (LLDB_ARCH_DEFAULT_64BIT))
805 *this = HostInfo::GetArchitecture(HostInfo::eArchKind64);
806 else if (triple_stref.equals (LLDB_ARCH_DEFAULT))
807 *this = HostInfo::GetArchitecture(HostInfo::eArchKindDefault);
811 std::string normalized_triple_sstr (llvm::Triple::normalize(triple_stref));
812 triple_stref = normalized_triple_sstr;
813 SetTriple (llvm::Triple (triple_stref));
822 ArchSpec::SetTriple (const char *triple_cstr, Platform *platform)
824 if (triple_cstr && triple_cstr[0])
826 if (ParseMachCPUDashSubtypeTriple (triple_cstr, *this))
829 llvm::StringRef triple_stref (triple_cstr);
830 if (triple_stref.startswith (LLDB_ARCH_DEFAULT))
832 // Special case for the current host default architectures...
833 if (triple_stref.equals (LLDB_ARCH_DEFAULT_32BIT))
834 *this = HostInfo::GetArchitecture(HostInfo::eArchKind32);
835 else if (triple_stref.equals (LLDB_ARCH_DEFAULT_64BIT))
836 *this = HostInfo::GetArchitecture(HostInfo::eArchKind64);
837 else if (triple_stref.equals (LLDB_ARCH_DEFAULT))
838 *this = HostInfo::GetArchitecture(HostInfo::eArchKindDefault);
842 ArchSpec raw_arch (triple_cstr);
844 std::string normalized_triple_sstr (llvm::Triple::normalize(triple_stref));
845 triple_stref = normalized_triple_sstr;
846 llvm::Triple normalized_triple (triple_stref);
848 const bool os_specified = normalized_triple.getOSName().size() > 0;
849 const bool vendor_specified = normalized_triple.getVendorName().size() > 0;
850 const bool env_specified = normalized_triple.getEnvironmentName().size() > 0;
852 // If we got an arch only, then default the vendor, os, environment
853 // to match the platform if one is supplied
854 if (!(os_specified || vendor_specified || env_specified))
858 // If we were given a platform, use the platform's system
859 // architecture. If this is not available (might not be
860 // connected) use the first supported architecture.
861 ArchSpec compatible_arch;
862 if (platform->IsCompatibleArchitecture (raw_arch, false, &compatible_arch))
864 if (compatible_arch.IsValid())
866 const llvm::Triple &compatible_triple = compatible_arch.GetTriple();
867 if (!vendor_specified)
868 normalized_triple.setVendor(compatible_triple.getVendor());
870 normalized_triple.setOS(compatible_triple.getOS());
871 if (!env_specified && compatible_triple.getEnvironmentName().size())
872 normalized_triple.setEnvironment(compatible_triple.getEnvironment());
883 // No platform specified, fall back to the host system for
884 // the default vendor, os, and environment.
885 llvm::Triple host_triple(llvm::sys::getDefaultTargetTriple());
886 if (!vendor_specified)
887 normalized_triple.setVendor(host_triple.getVendor());
888 if (!vendor_specified)
889 normalized_triple.setOS(host_triple.getOS());
890 if (!env_specified && host_triple.getEnvironmentName().size())
891 normalized_triple.setEnvironment(host_triple.getEnvironment());
894 SetTriple (normalized_triple);
903 ArchSpec::MergeFrom(const ArchSpec &other)
905 if (TripleVendorIsUnspecifiedUnknown() && !other.TripleVendorIsUnspecifiedUnknown())
906 GetTriple().setVendor(other.GetTriple().getVendor());
907 if (TripleOSIsUnspecifiedUnknown() && !other.TripleOSIsUnspecifiedUnknown())
908 GetTriple().setOS(other.GetTriple().getOS());
909 if (GetTriple().getArch() == llvm::Triple::UnknownArch)
910 GetTriple().setArch(other.GetTriple().getArch());
911 if (GetTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && !TripleVendorWasSpecified())
913 if (other.TripleVendorWasSpecified())
914 GetTriple().setEnvironment(other.GetTriple().getEnvironment());
916 // If this and other are both arm ArchSpecs and this ArchSpec is a generic "some kind of arm"
917 // spec but the other ArchSpec is a specific arm core, adopt the specific arm core.
918 if (GetTriple().getArch() == llvm::Triple::arm
919 && other.GetTriple().getArch() == llvm::Triple::arm
920 && IsCompatibleMatch (other)
921 && GetCore() == ArchSpec::eCore_arm_generic
922 && other.GetCore() != ArchSpec::eCore_arm_generic)
924 m_core = other.GetCore();
930 ArchSpec::SetArchitecture (ArchitectureType arch_type, uint32_t cpu, uint32_t sub, uint32_t os)
932 m_core = kCore_invalid;
933 bool update_triple = true;
934 const ArchDefinition *arch_def = FindArchDefinition(arch_type);
937 const ArchDefinitionEntry *arch_def_entry = FindArchDefinitionEntry (arch_def, cpu, sub);
940 const CoreDefinition *core_def = FindCoreDefinition (arch_def_entry->core);
943 m_core = core_def->core;
944 update_triple = false;
945 // Always use the architecture name because it might be more descriptive
946 // than the architecture enum ("armv7" -> llvm::Triple::arm).
947 m_triple.setArchName(llvm::StringRef(core_def->name));
948 if (arch_type == eArchTypeMachO)
950 m_triple.setVendor (llvm::Triple::Apple);
952 // Don't set the OS. It could be simulator, macosx, ios, watchos, tvos. We could
953 // get close with the cpu type - but we can't get it right all of the time. Better
954 // to leave this unset so other sections of code will set it when they have more
956 // NB: don't call m_triple.setOS (llvm::Triple::UnknownOS). That sets the OSName to
957 // "unknown" and the ArchSpec::TripleVendorWasSpecified() method says that any
958 // OSName setting means it was specified.
960 else if (arch_type == eArchTypeELF)
964 case llvm::ELF::ELFOSABI_AIX: m_triple.setOS (llvm::Triple::OSType::AIX); break;
965 case llvm::ELF::ELFOSABI_FREEBSD: m_triple.setOS (llvm::Triple::OSType::FreeBSD); break;
966 case llvm::ELF::ELFOSABI_GNU: m_triple.setOS (llvm::Triple::OSType::Linux); break;
967 case llvm::ELF::ELFOSABI_NETBSD: m_triple.setOS (llvm::Triple::OSType::NetBSD); break;
968 case llvm::ELF::ELFOSABI_OPENBSD: m_triple.setOS (llvm::Triple::OSType::OpenBSD); break;
969 case llvm::ELF::ELFOSABI_SOLARIS: m_triple.setOS (llvm::Triple::OSType::Solaris); break;
974 m_triple.setVendor (llvm::Triple::UnknownVendor);
975 m_triple.setOS (llvm::Triple::UnknownOS);
977 // Fall back onto setting the machine type if the arch by name failed...
978 if (m_triple.getArch () == llvm::Triple::UnknownArch)
979 m_triple.setArch (core_def->machine);
983 CoreUpdated(update_triple);
988 ArchSpec::GetMinimumOpcodeByteSize() const
990 const CoreDefinition *core_def = FindCoreDefinition (m_core);
992 return core_def->min_opcode_byte_size;
997 ArchSpec::GetMaximumOpcodeByteSize() const
999 const CoreDefinition *core_def = FindCoreDefinition (m_core);
1001 return core_def->max_opcode_byte_size;
1006 ArchSpec::IsExactMatch (const ArchSpec& rhs) const
1008 return IsEqualTo (rhs, true);
1012 ArchSpec::IsCompatibleMatch (const ArchSpec& rhs) const
1014 return IsEqualTo (rhs, false);
1018 isCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, llvm::Triple::EnvironmentType rhs)
1023 // If any of the environment is unknown then they are compatible
1024 if (lhs == llvm::Triple::UnknownEnvironment || rhs == llvm::Triple::UnknownEnvironment)
1027 // If one of the environment is Android and the other one is EABI then they are considered to
1028 // be compatible. This is required as a workaround for shared libraries compiled for Android
1029 // without the NOTE section indicating that they are using the Android ABI.
1030 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) ||
1031 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) ||
1032 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) ||
1033 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) ||
1034 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) ||
1035 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF))
1042 ArchSpec::IsEqualTo (const ArchSpec& rhs, bool exact_match) const
1044 // explicitly ignoring m_distribution_id in this method.
1046 if (GetByteOrder() != rhs.GetByteOrder())
1049 const ArchSpec::Core lhs_core = GetCore ();
1050 const ArchSpec::Core rhs_core = rhs.GetCore ();
1052 const bool core_match = cores_match (lhs_core, rhs_core, true, exact_match);
1056 const llvm::Triple &lhs_triple = GetTriple();
1057 const llvm::Triple &rhs_triple = rhs.GetTriple();
1059 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor();
1060 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor();
1061 if (lhs_triple_vendor != rhs_triple_vendor)
1063 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified();
1064 const bool lhs_vendor_specified = TripleVendorWasSpecified();
1065 // Both architectures had the vendor specified, so if they aren't
1066 // equal then we return false
1067 if (rhs_vendor_specified && lhs_vendor_specified)
1070 // Only fail if both vendor types are not unknown
1071 if (lhs_triple_vendor != llvm::Triple::UnknownVendor &&
1072 rhs_triple_vendor != llvm::Triple::UnknownVendor)
1076 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS();
1077 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS();
1078 if (lhs_triple_os != rhs_triple_os)
1080 const bool rhs_os_specified = rhs.TripleOSWasSpecified();
1081 const bool lhs_os_specified = TripleOSWasSpecified();
1082 // Both architectures had the OS specified, so if they aren't
1083 // equal then we return false
1084 if (rhs_os_specified && lhs_os_specified)
1087 // Only fail if both os types are not unknown
1088 if (lhs_triple_os != llvm::Triple::UnknownOS &&
1089 rhs_triple_os != llvm::Triple::UnknownOS)
1093 const llvm::Triple::EnvironmentType lhs_triple_env = lhs_triple.getEnvironment();
1094 const llvm::Triple::EnvironmentType rhs_triple_env = rhs_triple.getEnvironment();
1096 if (!isCompatibleEnvironment(lhs_triple_env, rhs_triple_env))
1103 //===----------------------------------------------------------------------===//
1107 ArchSpec::CoreUpdated (bool update_triple)
1109 const CoreDefinition *core_def = FindCoreDefinition (m_core);
1113 m_triple = llvm::Triple(core_def->name, "unknown", "unknown");
1114 m_byte_order = core_def->default_byte_order;
1119 m_triple = llvm::Triple();
1120 m_byte_order = eByteOrderInvalid;
1124 //===----------------------------------------------------------------------===//
1128 cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match)
1135 case ArchSpec::kCore_any:
1138 case ArchSpec::eCore_arm_generic:
1139 if (enforce_exact_match)
1142 case ArchSpec::kCore_arm_any:
1143 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
1145 if (core2 >= ArchSpec::kCore_thumb_first && core2 <= ArchSpec::kCore_thumb_last)
1147 if (core2 == ArchSpec::kCore_arm_any)
1151 case ArchSpec::kCore_x86_32_any:
1152 if ((core2 >= ArchSpec::kCore_x86_32_first && core2 <= ArchSpec::kCore_x86_32_last) || (core2 == ArchSpec::kCore_x86_32_any))
1156 case ArchSpec::kCore_x86_64_any:
1157 if ((core2 >= ArchSpec::kCore_x86_64_first && core2 <= ArchSpec::kCore_x86_64_last) || (core2 == ArchSpec::kCore_x86_64_any))
1161 case ArchSpec::kCore_ppc_any:
1162 if ((core2 >= ArchSpec::kCore_ppc_first && core2 <= ArchSpec::kCore_ppc_last) || (core2 == ArchSpec::kCore_ppc_any))
1166 case ArchSpec::kCore_ppc64_any:
1167 if ((core2 >= ArchSpec::kCore_ppc64_first && core2 <= ArchSpec::kCore_ppc64_last) || (core2 == ArchSpec::kCore_ppc64_any))
1171 case ArchSpec::eCore_arm_armv6m:
1172 if (!enforce_exact_match)
1174 if (core2 == ArchSpec::eCore_arm_generic)
1176 try_inverse = false;
1177 if (core2 == ArchSpec::eCore_arm_armv7)
1179 if (core2 == ArchSpec::eCore_arm_armv6m)
1184 case ArchSpec::kCore_hexagon_any:
1185 if ((core2 >= ArchSpec::kCore_hexagon_first && core2 <= ArchSpec::kCore_hexagon_last) || (core2 == ArchSpec::kCore_hexagon_any))
1189 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1190 // Cortex-M0 - ARMv6-M - armv6m
1191 // Cortex-M3 - ARMv7-M - armv7m
1192 // Cortex-M4 - ARMv7E-M - armv7em
1193 case ArchSpec::eCore_arm_armv7em:
1194 if (!enforce_exact_match)
1196 if (core2 == ArchSpec::eCore_arm_generic)
1198 if (core2 == ArchSpec::eCore_arm_armv7m)
1200 if (core2 == ArchSpec::eCore_arm_armv6m)
1202 if (core2 == ArchSpec::eCore_arm_armv7)
1208 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1209 // Cortex-M0 - ARMv6-M - armv6m
1210 // Cortex-M3 - ARMv7-M - armv7m
1211 // Cortex-M4 - ARMv7E-M - armv7em
1212 case ArchSpec::eCore_arm_armv7m:
1213 if (!enforce_exact_match)
1215 if (core2 == ArchSpec::eCore_arm_generic)
1217 if (core2 == ArchSpec::eCore_arm_armv6m)
1219 if (core2 == ArchSpec::eCore_arm_armv7)
1221 if (core2 == ArchSpec::eCore_arm_armv7em)
1227 case ArchSpec::eCore_arm_armv7f:
1228 case ArchSpec::eCore_arm_armv7k:
1229 case ArchSpec::eCore_arm_armv7s:
1230 if (!enforce_exact_match)
1232 if (core2 == ArchSpec::eCore_arm_generic)
1234 if (core2 == ArchSpec::eCore_arm_armv7)
1236 try_inverse = false;
1240 case ArchSpec::eCore_x86_64_x86_64h:
1241 if (!enforce_exact_match)
1243 try_inverse = false;
1244 if (core2 == ArchSpec::eCore_x86_64_x86_64)
1249 case ArchSpec::eCore_arm_armv8:
1250 if (!enforce_exact_match)
1252 if (core2 == ArchSpec::eCore_arm_arm64)
1254 if (core2 == ArchSpec::eCore_arm_aarch64)
1256 try_inverse = false;
1260 case ArchSpec::eCore_arm_aarch64:
1261 if (!enforce_exact_match)
1263 if (core2 == ArchSpec::eCore_arm_arm64)
1265 if (core2 == ArchSpec::eCore_arm_armv8)
1267 try_inverse = false;
1271 case ArchSpec::eCore_arm_arm64:
1272 if (!enforce_exact_match)
1274 if (core2 == ArchSpec::eCore_arm_aarch64)
1276 if (core2 == ArchSpec::eCore_arm_armv8)
1278 try_inverse = false;
1282 case ArchSpec::eCore_mips32:
1283 if (!enforce_exact_match)
1285 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= ArchSpec::kCore_mips32_last)
1287 try_inverse = false;
1291 case ArchSpec::eCore_mips32el:
1292 if (!enforce_exact_match)
1294 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= ArchSpec::kCore_mips32el_last)
1296 try_inverse = false;
1300 case ArchSpec::eCore_mips64:
1301 if (!enforce_exact_match)
1303 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= ArchSpec::kCore_mips32_last)
1305 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= ArchSpec::kCore_mips64_last)
1307 try_inverse = false;
1311 case ArchSpec::eCore_mips64el:
1312 if (!enforce_exact_match)
1314 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= ArchSpec::kCore_mips32el_last)
1316 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= ArchSpec::kCore_mips64el_last)
1318 try_inverse = false;
1322 case ArchSpec::eCore_mips64r2:
1323 case ArchSpec::eCore_mips64r3:
1324 case ArchSpec::eCore_mips64r5:
1325 if (!enforce_exact_match)
1327 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10))
1329 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1))
1331 try_inverse = false;
1335 case ArchSpec::eCore_mips64r2el:
1336 case ArchSpec::eCore_mips64r3el:
1337 case ArchSpec::eCore_mips64r5el:
1338 if (!enforce_exact_match)
1340 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10))
1342 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1))
1344 try_inverse = false;
1348 case ArchSpec::eCore_mips32r2:
1349 case ArchSpec::eCore_mips32r3:
1350 case ArchSpec::eCore_mips32r5:
1351 if (!enforce_exact_match)
1353 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1)
1358 case ArchSpec::eCore_mips32r2el:
1359 case ArchSpec::eCore_mips32r3el:
1360 case ArchSpec::eCore_mips32r5el:
1361 if (!enforce_exact_match)
1363 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1)
1368 case ArchSpec::eCore_mips32r6:
1369 if (!enforce_exact_match)
1371 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1376 case ArchSpec::eCore_mips32r6el:
1377 if (!enforce_exact_match)
1379 if (core2 == ArchSpec::eCore_mips32el || core2 == ArchSpec::eCore_mips32r6el)
1384 case ArchSpec::eCore_mips64r6:
1385 if (!enforce_exact_match)
1387 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1389 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6)
1394 case ArchSpec::eCore_mips64r6el:
1395 if (!enforce_exact_match)
1397 if (core2 == ArchSpec::eCore_mips32el || core2 == ArchSpec::eCore_mips32r6el)
1399 if (core2 == ArchSpec::eCore_mips64el || core2 == ArchSpec::eCore_mips64r6el)
1408 return cores_match (core2, core1, false, enforce_exact_match);
1413 lldb_private::operator<(const ArchSpec& lhs, const ArchSpec& rhs)
1415 const ArchSpec::Core lhs_core = lhs.GetCore ();
1416 const ArchSpec::Core rhs_core = rhs.GetCore ();
1417 return lhs_core < rhs_core;
1421 StopInfoOverrideCallbackTypeARM(lldb_private::Thread &thread)
1423 // We need to check if we are stopped in Thumb mode in a IT instruction
1424 // and detect if the condition doesn't pass. If this is the case it means
1425 // we won't actually execute this instruction. If this happens we need to
1426 // clear the stop reason to no thread plans think we are stopped for a
1427 // reason and the plans should keep going.
1429 // We do this because when single stepping many ARM processes, debuggers
1430 // often use the BVR/BCR registers that says "stop when the PC is not
1431 // equal to its current value". This method of stepping means we can end
1432 // up stopping on instructions inside an if/then block that wouldn't get
1433 // executed. By fixing this we can stop the debugger from seeming like
1434 // you stepped through both the "if" _and_ the "else" clause when source
1435 // level stepping because the debugger stops regardless due to the BVR/BCR
1436 // triggering a stop.
1438 // It also means we can set breakpoints on instructions inside an an
1439 // if/then block and correctly skip them if we use the BKPT instruction.
1440 // The ARM and Thumb BKPT instructions are unconditional even when executed
1441 // in a Thumb IT block.
1443 // If your debugger inserts software traps in ARM/Thumb code, it will
1444 // need to use 16 and 32 bit instruction for 16 and 32 bit thumb
1445 // instructions respectively. If your debugger inserts a 16 bit thumb
1446 // trap on top of a 32 bit thumb instruction for an opcode that is inside
1447 // an if/then, it will change the it/then to conditionally execute your
1448 // 16 bit trap and then cause your program to crash if it executes the
1449 // trailing 16 bits (the second half of the 32 bit thumb instruction you
1450 // partially overwrote).
1452 RegisterContextSP reg_ctx_sp (thread.GetRegisterContext());
1455 const uint32_t cpsr = reg_ctx_sp->GetFlags(0);
1458 // Read the J and T bits to get the ISETSTATE
1459 const uint32_t J = Bit32(cpsr, 24);
1460 const uint32_t T = Bit32(cpsr, 5);
1461 const uint32_t ISETSTATE = J << 1 | T;
1464 // NOTE: I am pretty sure we want to enable the code below
1465 // that detects when we stop on an instruction in ARM mode
1466 // that is conditional and the condition doesn't pass. This
1467 // can happen if you set a breakpoint on an instruction that
1468 // is conditional. We currently will _always_ stop on the
1469 // instruction which is bad. You can also run into this while
1470 // single stepping and you could appear to run code in the "if"
1471 // and in the "else" clause because it would stop at all of the
1472 // conditional instructions in both.
1473 // In such cases, we really don't want to stop at this location.
1474 // I will check with the lldb-dev list first before I enable this.
1476 // ARM mode: check for condition on intsruction
1477 const addr_t pc = reg_ctx_sp->GetPC();
1479 // If we fail to read the opcode we will get UINT64_MAX as the
1480 // result in "opcode" which we can use to detect if we read a
1482 const uint64_t opcode = thread.GetProcess()->ReadUnsignedIntegerFromMemory(pc, 4, UINT64_MAX, error);
1483 if (opcode <= UINT32_MAX)
1485 const uint32_t condition = Bits32((uint32_t)opcode, 31, 28);
1486 if (!ARMConditionPassed(condition, cpsr))
1488 // We ARE stopped on an ARM instruction whose condition doesn't
1489 // pass so this instruction won't get executed.
1490 // Regardless of why it stopped, we need to clear the stop info
1491 thread.SetStopInfo (StopInfoSP());
1496 else if (ISETSTATE == 1)
1499 const uint32_t ITSTATE = Bits32 (cpsr, 15, 10) << 2 | Bits32 (cpsr, 26, 25);
1502 const uint32_t condition = Bits32(ITSTATE, 7, 4);
1503 if (!ARMConditionPassed(condition, cpsr))
1505 // We ARE stopped in a Thumb IT instruction on an instruction whose
1506 // condition doesn't pass so this instruction won't get executed.
1507 // Regardless of why it stopped, we need to clear the stop info
1508 thread.SetStopInfo (StopInfoSP());
1516 ArchSpec::StopInfoOverrideCallbackType
1517 ArchSpec::GetStopInfoOverrideCallback () const
1519 const llvm::Triple::ArchType machine = GetMachine();
1520 if (machine == llvm::Triple::arm)
1521 return StopInfoOverrideCallbackTypeARM;
1526 ArchSpec::IsFullySpecifiedTriple () const
1528 const auto& user_specified_triple = GetTriple();
1530 bool user_triple_fully_specified = false;
1532 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || TripleOSWasSpecified())
1534 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || TripleVendorWasSpecified())
1536 const unsigned unspecified = 0;
1537 if (user_specified_triple.getOSMajorVersion() != unspecified)
1539 user_triple_fully_specified = true;
1544 return user_triple_fully_specified;
1548 ArchSpec::PiecewiseTripleCompare (const ArchSpec &other,
1549 bool &arch_different,
1550 bool &vendor_different,
1552 bool &os_version_different,
1553 bool &env_different)
1555 const llvm::Triple &me(GetTriple());
1556 const llvm::Triple &them(other.GetTriple());
1558 arch_different = (me.getArch() != them.getArch());
1560 vendor_different = (me.getVendor() != them.getVendor());
1562 os_different = (me.getOS() != them.getOS());
1564 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion());
1566 env_different = (me.getEnvironment() != them.getEnvironment());
1570 ArchSpec::IsAlwaysThumbInstructions () const
1573 if (GetTriple().getArch() == llvm::Triple::arm || GetTriple().getArch() == llvm::Triple::thumb)
1575 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M
1577 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only
1578 // execute thumb instructions. We map the cores to arch names like this:
1580 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m
1581 // Cortex-M3: armv7m
1582 // Cortex-M4, Cortex-M7: armv7em
1584 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m
1585 || GetCore() == ArchSpec::Core::eCore_arm_armv7em
1586 || GetCore() == ArchSpec::Core::eCore_arm_armv6m)
1595 ArchSpec::DumpTriple(Stream &s) const
1597 const llvm::Triple &triple = GetTriple();
1598 llvm::StringRef arch_str = triple.getArchName();
1599 llvm::StringRef vendor_str = triple.getVendorName();
1600 llvm::StringRef os_str = triple.getOSName();
1601 llvm::StringRef environ_str = triple.getEnvironmentName();
1603 s.Printf("%s-%s-%s",
1604 arch_str.empty() ? "*" : arch_str.str().c_str(),
1605 vendor_str.empty() ? "*" : vendor_str.str().c_str(),
1606 os_str.empty() ? "*" : os_str.str().c_str()
1609 if (!environ_str.empty())
1610 s.Printf("-%s", environ_str.str().c_str());