1 //===-- NativeRegisterContextLinux_arm.cpp --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #if defined(__arm__) || defined(__arm64__) || defined(__aarch64__)
12 #include "NativeRegisterContextLinux_arm.h"
14 #include "lldb/Core/DataBufferHeap.h"
15 #include "lldb/Core/Error.h"
16 #include "lldb/Core/Log.h"
17 #include "lldb/Core/RegisterValue.h"
19 #include "Plugins/Process/Linux/Procfs.h"
20 #include "Plugins/Process/Utility/RegisterContextLinux_arm.h"
23 #include <sys/socket.h>
25 #define REG_CONTEXT_SIZE (GetGPRSize() + sizeof(m_fpr))
27 #ifndef PTRACE_GETVFPREGS
28 #define PTRACE_GETVFPREGS 27
29 #define PTRACE_SETVFPREGS 28
31 #ifndef PTRACE_GETHBPREGS
32 #define PTRACE_GETHBPREGS 29
33 #define PTRACE_SETHBPREGS 30
35 #if !defined(PTRACE_TYPE_ARG3)
36 #define PTRACE_TYPE_ARG3 void *
38 #if !defined(PTRACE_TYPE_ARG4)
39 #define PTRACE_TYPE_ARG4 void *
43 using namespace lldb_private;
44 using namespace lldb_private::process_linux;
46 // arm general purpose registers.
47 static const uint32_t g_gpr_regnums_arm[] = {
48 gpr_r0_arm, gpr_r1_arm, gpr_r2_arm, gpr_r3_arm, gpr_r4_arm,
49 gpr_r5_arm, gpr_r6_arm, gpr_r7_arm, gpr_r8_arm, gpr_r9_arm,
50 gpr_r10_arm, gpr_r11_arm, gpr_r12_arm, gpr_sp_arm, gpr_lr_arm,
51 gpr_pc_arm, gpr_cpsr_arm,
52 LLDB_INVALID_REGNUM // register sets need to end with this flag
54 static_assert(((sizeof g_gpr_regnums_arm / sizeof g_gpr_regnums_arm[0]) - 1) ==
55 k_num_gpr_registers_arm,
56 "g_gpr_regnums_arm has wrong number of register infos");
58 // arm floating point registers.
59 static const uint32_t g_fpu_regnums_arm[] = {
60 fpu_s0_arm, fpu_s1_arm, fpu_s2_arm, fpu_s3_arm, fpu_s4_arm,
61 fpu_s5_arm, fpu_s6_arm, fpu_s7_arm, fpu_s8_arm, fpu_s9_arm,
62 fpu_s10_arm, fpu_s11_arm, fpu_s12_arm, fpu_s13_arm, fpu_s14_arm,
63 fpu_s15_arm, fpu_s16_arm, fpu_s17_arm, fpu_s18_arm, fpu_s19_arm,
64 fpu_s20_arm, fpu_s21_arm, fpu_s22_arm, fpu_s23_arm, fpu_s24_arm,
65 fpu_s25_arm, fpu_s26_arm, fpu_s27_arm, fpu_s28_arm, fpu_s29_arm,
66 fpu_s30_arm, fpu_s31_arm, fpu_fpscr_arm, fpu_d0_arm, fpu_d1_arm,
67 fpu_d2_arm, fpu_d3_arm, fpu_d4_arm, fpu_d5_arm, fpu_d6_arm,
68 fpu_d7_arm, fpu_d8_arm, fpu_d9_arm, fpu_d10_arm, fpu_d11_arm,
69 fpu_d12_arm, fpu_d13_arm, fpu_d14_arm, fpu_d15_arm, fpu_d16_arm,
70 fpu_d17_arm, fpu_d18_arm, fpu_d19_arm, fpu_d20_arm, fpu_d21_arm,
71 fpu_d22_arm, fpu_d23_arm, fpu_d24_arm, fpu_d25_arm, fpu_d26_arm,
72 fpu_d27_arm, fpu_d28_arm, fpu_d29_arm, fpu_d30_arm, fpu_d31_arm,
73 fpu_q0_arm, fpu_q1_arm, fpu_q2_arm, fpu_q3_arm, fpu_q4_arm,
74 fpu_q5_arm, fpu_q6_arm, fpu_q7_arm, fpu_q8_arm, fpu_q9_arm,
75 fpu_q10_arm, fpu_q11_arm, fpu_q12_arm, fpu_q13_arm, fpu_q14_arm,
77 LLDB_INVALID_REGNUM // register sets need to end with this flag
79 static_assert(((sizeof g_fpu_regnums_arm / sizeof g_fpu_regnums_arm[0]) - 1) ==
80 k_num_fpr_registers_arm,
81 "g_fpu_regnums_arm has wrong number of register infos");
84 // Number of register sets provided by this context.
85 enum { k_num_register_sets = 2 };
88 // Register sets for arm.
89 static const RegisterSet g_reg_sets_arm[k_num_register_sets] = {
90 {"General Purpose Registers", "gpr", k_num_gpr_registers_arm,
92 {"Floating Point Registers", "fpu", k_num_fpr_registers_arm,
97 NativeRegisterContextLinux *
98 NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
99 const ArchSpec &target_arch, NativeThreadProtocol &native_thread,
100 uint32_t concrete_frame_idx) {
101 return new NativeRegisterContextLinux_arm(target_arch, native_thread,
105 #endif // defined(__arm__)
107 NativeRegisterContextLinux_arm::NativeRegisterContextLinux_arm(
108 const ArchSpec &target_arch, NativeThreadProtocol &native_thread,
109 uint32_t concrete_frame_idx)
110 : NativeRegisterContextLinux(native_thread, concrete_frame_idx,
111 new RegisterContextLinux_arm(target_arch)) {
112 switch (target_arch.GetMachine()) {
113 case llvm::Triple::arm:
114 m_reg_info.num_registers = k_num_registers_arm;
115 m_reg_info.num_gpr_registers = k_num_gpr_registers_arm;
116 m_reg_info.num_fpr_registers = k_num_fpr_registers_arm;
117 m_reg_info.last_gpr = k_last_gpr_arm;
118 m_reg_info.first_fpr = k_first_fpr_arm;
119 m_reg_info.last_fpr = k_last_fpr_arm;
120 m_reg_info.first_fpr_v = fpu_s0_arm;
121 m_reg_info.last_fpr_v = fpu_s31_arm;
122 m_reg_info.gpr_flags = gpr_cpsr_arm;
125 assert(false && "Unhandled target architecture.");
129 ::memset(&m_fpr, 0, sizeof(m_fpr));
130 ::memset(&m_gpr_arm, 0, sizeof(m_gpr_arm));
131 ::memset(&m_hwp_regs, 0, sizeof(m_hwp_regs));
133 // 16 is just a maximum value, query hardware for actual watchpoint count
134 m_max_hwp_supported = 16;
135 m_max_hbp_supported = 16;
136 m_refresh_hwdebug_info = true;
139 uint32_t NativeRegisterContextLinux_arm::GetRegisterSetCount() const {
140 return k_num_register_sets;
143 uint32_t NativeRegisterContextLinux_arm::GetUserRegisterCount() const {
145 for (uint32_t set_index = 0; set_index < k_num_register_sets; ++set_index)
146 count += g_reg_sets_arm[set_index].num_registers;
151 NativeRegisterContextLinux_arm::GetRegisterSet(uint32_t set_index) const {
152 if (set_index < k_num_register_sets)
153 return &g_reg_sets_arm[set_index];
158 Error NativeRegisterContextLinux_arm::ReadRegister(const RegisterInfo *reg_info,
159 RegisterValue ®_value) {
163 error.SetErrorString("reg_info NULL");
167 const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
174 uint32_t full_reg = reg;
175 bool is_subreg = reg_info->invalidate_regs &&
176 (reg_info->invalidate_regs[0] != LLDB_INVALID_REGNUM);
179 // Read the full aligned 64-bit register.
180 full_reg = reg_info->invalidate_regs[0];
183 error = ReadRegisterRaw(full_reg, reg_value);
185 if (error.Success()) {
186 // If our read was not aligned (for ah,bh,ch,dh), shift our returned value
187 // one byte to the right.
188 if (is_subreg && (reg_info->byte_offset & 0x1))
189 reg_value.SetUInt64(reg_value.GetAsUInt64() >> 8);
191 // If our return byte size was greater than the return value reg size,
193 // use the type specified by reg_info rather than the uint64_t default
194 if (reg_value.GetByteSize() > reg_info->byte_size)
195 reg_value.SetType(reg_info);
200 // Get pointer to m_fpr variable and set the data from it.
201 uint32_t fpr_offset = CalculateFprOffset(reg_info);
202 assert(fpr_offset < sizeof m_fpr);
203 uint8_t *src = (uint8_t *)&m_fpr + fpr_offset;
204 switch (reg_info->byte_size) {
206 reg_value.SetUInt16(*(uint16_t *)src);
209 reg_value.SetUInt32(*(uint32_t *)src);
212 reg_value.SetUInt64(*(uint64_t *)src);
215 reg_value.SetBytes(src, 16, GetByteOrder());
218 assert(false && "Unhandled data size.");
219 error.SetErrorStringWithFormat("unhandled byte size: %" PRIu32,
220 reg_info->byte_size);
227 Error NativeRegisterContextLinux_arm::WriteRegister(
228 const RegisterInfo *reg_info, const RegisterValue ®_value) {
230 return Error("reg_info NULL");
232 const uint32_t reg_index = reg_info->kinds[lldb::eRegisterKindLLDB];
233 if (reg_index == LLDB_INVALID_REGNUM)
234 return Error("no lldb regnum for %s", reg_info && reg_info->name
236 : "<unknown register>");
238 if (IsGPR(reg_index))
239 return WriteRegisterRaw(reg_index, reg_value);
241 if (IsFPR(reg_index)) {
242 // Get pointer to m_fpr variable and set the data to it.
243 uint32_t fpr_offset = CalculateFprOffset(reg_info);
244 assert(fpr_offset < sizeof m_fpr);
245 uint8_t *dst = (uint8_t *)&m_fpr + fpr_offset;
246 switch (reg_info->byte_size) {
248 *(uint16_t *)dst = reg_value.GetAsUInt16();
251 *(uint32_t *)dst = reg_value.GetAsUInt32();
254 *(uint64_t *)dst = reg_value.GetAsUInt64();
257 assert(false && "Unhandled data size.");
258 return Error("unhandled register data size %" PRIu32,
259 reg_info->byte_size);
262 Error error = WriteFPR();
269 return Error("failed - register wasn't recognized to be a GPR or an FPR, "
270 "write strategy unknown");
273 Error NativeRegisterContextLinux_arm::ReadAllRegisterValues(
274 lldb::DataBufferSP &data_sp) {
277 data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0));
279 return Error("failed to allocate DataBufferHeap instance of size %" PRIu64,
280 (uint64_t)REG_CONTEXT_SIZE);
290 uint8_t *dst = data_sp->GetBytes();
291 if (dst == nullptr) {
292 error.SetErrorStringWithFormat("DataBufferHeap instance of size %" PRIu64
293 " returned a null pointer",
294 (uint64_t)REG_CONTEXT_SIZE);
298 ::memcpy(dst, &m_gpr_arm, GetGPRSize());
300 ::memcpy(dst, &m_fpr, sizeof(m_fpr));
305 Error NativeRegisterContextLinux_arm::WriteAllRegisterValues(
306 const lldb::DataBufferSP &data_sp) {
310 error.SetErrorStringWithFormat(
311 "NativeRegisterContextLinux_x86_64::%s invalid data_sp provided",
316 if (data_sp->GetByteSize() != REG_CONTEXT_SIZE) {
317 error.SetErrorStringWithFormat(
318 "NativeRegisterContextLinux_x86_64::%s data_sp contained mismatched "
319 "data size, expected %" PRIu64 ", actual %" PRIu64,
320 __FUNCTION__, (uint64_t)REG_CONTEXT_SIZE, data_sp->GetByteSize());
324 uint8_t *src = data_sp->GetBytes();
325 if (src == nullptr) {
326 error.SetErrorStringWithFormat("NativeRegisterContextLinux_x86_64::%s "
327 "DataBuffer::GetBytes() returned a null "
332 ::memcpy(&m_gpr_arm, src, GetRegisterInfoInterface().GetGPRSize());
338 src += GetRegisterInfoInterface().GetGPRSize();
339 ::memcpy(&m_fpr, src, sizeof(m_fpr));
348 bool NativeRegisterContextLinux_arm::IsGPR(unsigned reg) const {
349 return reg <= m_reg_info.last_gpr; // GPR's come first.
352 bool NativeRegisterContextLinux_arm::IsFPR(unsigned reg) const {
353 return (m_reg_info.first_fpr <= reg && reg <= m_reg_info.last_fpr);
357 NativeRegisterContextLinux_arm::SetHardwareBreakpoint(lldb::addr_t addr,
359 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS));
362 log->Printf("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
366 // Read hardware breakpoint and watchpoint information.
367 error = ReadHardwareDebugInfo();
370 return LLDB_INVALID_INDEX32;
372 uint32_t control_value = 0, bp_index = 0;
374 // Check if size has a valid hardware breakpoint length.
375 // Thumb instructions are 2-bytes but we have no way here to determine
376 // if target address is a thumb or arm instruction.
377 // TODO: Add support for setting thumb mode hardware breakpoints
378 if (size != 4 && size != 2)
379 return LLDB_INVALID_INDEX32;
381 // Setup control value
382 // Make the byte_mask into a valid Byte Address Select mask
383 control_value = 0xfu << 5;
385 // Enable this breakpoint and make it stop in privileged or user mode;
388 // Make sure bits 1:0 are clear in our address
389 // This should be different once we support thumb here.
390 addr &= ~((lldb::addr_t)3);
392 // Iterate over stored hardware breakpoints
393 // Find a free bp_index or update reference count if duplicate.
394 bp_index = LLDB_INVALID_INDEX32;
396 for (uint32_t i = 0; i < m_max_hbp_supported; i++) {
397 if ((m_hbr_regs[i].control & 1) == 0) {
398 bp_index = i; // Mark last free slot
399 } else if (m_hbr_regs[i].address == addr &&
400 m_hbr_regs[i].control == control_value) {
401 bp_index = i; // Mark duplicate index
402 break; // Stop searching here
406 if (bp_index == LLDB_INVALID_INDEX32)
407 return LLDB_INVALID_INDEX32;
409 // Add new or update existing breakpoint
410 if ((m_hbr_regs[bp_index].control & 1) == 0) {
411 m_hbr_regs[bp_index].address = addr;
412 m_hbr_regs[bp_index].control = control_value;
413 m_hbr_regs[bp_index].refcount = 1;
415 // PTRACE call to set corresponding hardware breakpoint register.
416 error = WriteHardwareDebugRegs(eDREGTypeBREAK, bp_index);
419 m_hbr_regs[bp_index].address = 0;
420 m_hbr_regs[bp_index].control &= ~1;
421 m_hbr_regs[bp_index].refcount = 0;
423 return LLDB_INVALID_INDEX32;
426 m_hbr_regs[bp_index].refcount++;
431 bool NativeRegisterContextLinux_arm::ClearHardwareBreakpoint(uint32_t hw_idx) {
432 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS));
435 log->Printf("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
439 // Read hardware breakpoint and watchpoint information.
440 error = ReadHardwareDebugInfo();
445 if (hw_idx >= m_max_hbp_supported)
448 // Update reference count if multiple references.
449 if (m_hbr_regs[hw_idx].refcount > 1) {
450 m_hbr_regs[hw_idx].refcount--;
452 } else if (m_hbr_regs[hw_idx].refcount == 1) {
453 // Create a backup we can revert to in case of failure.
454 lldb::addr_t tempAddr = m_hbr_regs[hw_idx].address;
455 uint32_t tempControl = m_hbr_regs[hw_idx].control;
456 uint32_t tempRefCount = m_hbr_regs[hw_idx].refcount;
458 m_hbr_regs[hw_idx].control &= ~1;
459 m_hbr_regs[hw_idx].address = 0;
460 m_hbr_regs[hw_idx].refcount = 0;
462 // PTRACE call to clear corresponding hardware breakpoint register.
463 WriteHardwareDebugRegs(eDREGTypeBREAK, hw_idx);
466 m_hbr_regs[hw_idx].control = tempControl;
467 m_hbr_regs[hw_idx].address = tempAddr;
468 m_hbr_regs[hw_idx].refcount = tempRefCount;
479 uint32_t NativeRegisterContextLinux_arm::NumSupportedHardwareWatchpoints() {
480 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS));
483 log->Printf("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
487 // Read hardware breakpoint and watchpoint information.
488 error = ReadHardwareDebugInfo();
493 return m_max_hwp_supported;
496 uint32_t NativeRegisterContextLinux_arm::SetHardwareWatchpoint(
497 lldb::addr_t addr, size_t size, uint32_t watch_flags) {
498 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS));
501 log->Printf("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
505 // Read hardware breakpoint and watchpoint information.
506 error = ReadHardwareDebugInfo();
509 return LLDB_INVALID_INDEX32;
511 uint32_t control_value = 0, wp_index = 0, addr_word_offset = 0, byte_mask = 0;
512 lldb::addr_t real_addr = addr;
514 // Check if we are setting watchpoint other than read/write/access
515 // Also update watchpoint flag to match Arm write-read bit configuration.
516 switch (watch_flags) {
526 return LLDB_INVALID_INDEX32;
529 // Can't watch zero bytes
530 // Can't watch more than 4 bytes per WVR/WCR pair
532 if (size == 0 || size > 4)
533 return LLDB_INVALID_INDEX32;
535 // Check 4-byte alignment for hardware watchpoint target address.
536 // Below is a hack to recalculate address and size in order to
537 // make sure we can watch non 4-byte alligned addresses as well.
539 uint8_t watch_mask = (addr & 0x03) + size;
541 if (watch_mask > 0x04)
542 return LLDB_INVALID_INDEX32;
543 else if (watch_mask <= 0x02)
545 else if (watch_mask <= 0x04)
548 addr = addr & (~0x03);
551 // We can only watch up to four bytes that follow a 4 byte aligned address
552 // per watchpoint register pair, so make sure we can properly encode this.
553 addr_word_offset = addr % 4;
554 byte_mask = ((1u << size) - 1u) << addr_word_offset;
556 // Check if we need multiple watchpoint register
557 if (byte_mask > 0xfu)
558 return LLDB_INVALID_INDEX32;
560 // Setup control value
561 // Make the byte_mask into a valid Byte Address Select mask
562 control_value = byte_mask << 5;
564 // Turn on appropriate watchpoint flags read or write
565 control_value |= (watch_flags << 3);
567 // Enable this watchpoint and make it stop in privileged or user mode;
570 // Make sure bits 1:0 are clear in our address
571 addr &= ~((lldb::addr_t)3);
573 // Iterate over stored watchpoints and find a free wp_index
574 wp_index = LLDB_INVALID_INDEX32;
575 for (uint32_t i = 0; i < m_max_hwp_supported; i++) {
576 if ((m_hwp_regs[i].control & 1) == 0) {
577 wp_index = i; // Mark last free slot
578 } else if (m_hwp_regs[i].address == addr) {
579 return LLDB_INVALID_INDEX32; // We do not support duplicate watchpoints.
583 if (wp_index == LLDB_INVALID_INDEX32)
584 return LLDB_INVALID_INDEX32;
586 // Update watchpoint in local cache
587 m_hwp_regs[wp_index].real_addr = real_addr;
588 m_hwp_regs[wp_index].address = addr;
589 m_hwp_regs[wp_index].control = control_value;
591 // PTRACE call to set corresponding watchpoint register.
592 error = WriteHardwareDebugRegs(eDREGTypeWATCH, wp_index);
595 m_hwp_regs[wp_index].address = 0;
596 m_hwp_regs[wp_index].control &= ~1;
598 return LLDB_INVALID_INDEX32;
604 bool NativeRegisterContextLinux_arm::ClearHardwareWatchpoint(
606 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS));
609 log->Printf("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
613 // Read hardware breakpoint and watchpoint information.
614 error = ReadHardwareDebugInfo();
619 if (wp_index >= m_max_hwp_supported)
622 // Create a backup we can revert to in case of failure.
623 lldb::addr_t tempAddr = m_hwp_regs[wp_index].address;
624 uint32_t tempControl = m_hwp_regs[wp_index].control;
626 // Update watchpoint in local cache
627 m_hwp_regs[wp_index].control &= ~1;
628 m_hwp_regs[wp_index].address = 0;
630 // Ptrace call to update hardware debug registers
631 error = WriteHardwareDebugRegs(eDREGTypeWATCH, wp_index);
634 m_hwp_regs[wp_index].control = tempControl;
635 m_hwp_regs[wp_index].address = tempAddr;
643 Error NativeRegisterContextLinux_arm::ClearAllHardwareWatchpoints() {
644 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS));
647 log->Printf("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
651 // Read hardware breakpoint and watchpoint information.
652 error = ReadHardwareDebugInfo();
657 lldb::addr_t tempAddr = 0;
658 uint32_t tempControl = 0;
660 for (uint32_t i = 0; i < m_max_hwp_supported; i++) {
661 if (m_hwp_regs[i].control & 0x01) {
662 // Create a backup we can revert to in case of failure.
663 tempAddr = m_hwp_regs[i].address;
664 tempControl = m_hwp_regs[i].control;
666 // Clear watchpoints in local cache
667 m_hwp_regs[i].control &= ~1;
668 m_hwp_regs[i].address = 0;
670 // Ptrace call to update hardware debug registers
671 error = WriteHardwareDebugRegs(eDREGTypeWATCH, i);
674 m_hwp_regs[i].control = tempControl;
675 m_hwp_regs[i].address = tempAddr;
685 uint32_t NativeRegisterContextLinux_arm::GetWatchpointSize(uint32_t wp_index) {
686 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS));
689 log->Printf("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
691 switch ((m_hwp_regs[wp_index].control >> 5) & 0x0f) {
704 bool NativeRegisterContextLinux_arm::WatchpointIsEnabled(uint32_t wp_index) {
705 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS));
708 log->Printf("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
710 if ((m_hwp_regs[wp_index].control & 0x1) == 0x1)
716 Error NativeRegisterContextLinux_arm::GetWatchpointHitIndex(
717 uint32_t &wp_index, lldb::addr_t trap_addr) {
718 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS));
721 log->Printf("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
724 lldb::addr_t watch_addr;
726 for (wp_index = 0; wp_index < m_max_hwp_supported; ++wp_index) {
727 watch_size = GetWatchpointSize(wp_index);
728 watch_addr = m_hwp_regs[wp_index].address;
730 if (WatchpointIsEnabled(wp_index) && trap_addr >= watch_addr &&
731 trap_addr < watch_addr + watch_size) {
732 m_hwp_regs[wp_index].hit_addr = trap_addr;
737 wp_index = LLDB_INVALID_INDEX32;
742 NativeRegisterContextLinux_arm::GetWatchpointAddress(uint32_t wp_index) {
743 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS));
746 log->Printf("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
748 if (wp_index >= m_max_hwp_supported)
749 return LLDB_INVALID_ADDRESS;
751 if (WatchpointIsEnabled(wp_index))
752 return m_hwp_regs[wp_index].real_addr;
754 return LLDB_INVALID_ADDRESS;
758 NativeRegisterContextLinux_arm::GetWatchpointHitAddress(uint32_t wp_index) {
759 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS));
762 log->Printf("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
764 if (wp_index >= m_max_hwp_supported)
765 return LLDB_INVALID_ADDRESS;
767 if (WatchpointIsEnabled(wp_index))
768 return m_hwp_regs[wp_index].hit_addr;
770 return LLDB_INVALID_ADDRESS;
773 Error NativeRegisterContextLinux_arm::ReadHardwareDebugInfo() {
776 if (!m_refresh_hwdebug_info) {
780 unsigned int cap_val;
782 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETHBPREGS, m_thread.GetID(),
784 sizeof(unsigned int));
789 m_max_hwp_supported = (cap_val >> 8) & 0xff;
790 m_max_hbp_supported = cap_val & 0xff;
791 m_refresh_hwdebug_info = false;
796 Error NativeRegisterContextLinux_arm::WriteHardwareDebugRegs(int hwbType,
800 lldb::addr_t *addr_buf;
803 if (hwbType == eDREGTypeWATCH) {
804 addr_buf = &m_hwp_regs[hwb_index].address;
805 ctrl_buf = &m_hwp_regs[hwb_index].control;
807 error = NativeProcessLinux::PtraceWrapper(
808 PTRACE_SETHBPREGS, m_thread.GetID(),
809 (PTRACE_TYPE_ARG3)(intptr_t) - ((hwb_index << 1) + 1), addr_buf,
810 sizeof(unsigned int));
815 error = NativeProcessLinux::PtraceWrapper(
816 PTRACE_SETHBPREGS, m_thread.GetID(),
817 (PTRACE_TYPE_ARG3)(intptr_t) - ((hwb_index << 1) + 2), ctrl_buf,
818 sizeof(unsigned int));
820 addr_buf = &m_hwp_regs[hwb_index].address;
821 ctrl_buf = &m_hwp_regs[hwb_index].control;
823 error = NativeProcessLinux::PtraceWrapper(
824 PTRACE_SETHBPREGS, m_thread.GetID(),
825 (PTRACE_TYPE_ARG3)(intptr_t)((hwb_index << 1) + 1), addr_buf,
826 sizeof(unsigned int));
831 error = NativeProcessLinux::PtraceWrapper(
832 PTRACE_SETHBPREGS, m_thread.GetID(),
833 (PTRACE_TYPE_ARG3)(intptr_t)((hwb_index << 1) + 2), ctrl_buf,
834 sizeof(unsigned int));
840 uint32_t NativeRegisterContextLinux_arm::CalculateFprOffset(
841 const RegisterInfo *reg_info) const {
842 return reg_info->byte_offset -
843 GetRegisterInfoAtIndex(m_reg_info.first_fpr)->byte_offset;
846 Error NativeRegisterContextLinux_arm::DoReadRegisterValue(
847 uint32_t offset, const char *reg_name, uint32_t size,
848 RegisterValue &value) {
849 // PTRACE_PEEKUSER don't work in the aarch64 linux kernel used on android
850 // devices (always return
851 // "Bad address"). To avoid using PTRACE_PEEKUSER we read out the full GPR
852 // register set instead.
853 // This approach is about 4 times slower but the performance overhead is
855 // comparision to processing time in lldb-server.
856 assert(offset % 4 == 0 && "Try to write a register with unaligned offset");
857 if (offset + sizeof(uint32_t) > sizeof(m_gpr_arm))
858 return Error("Register isn't fit into the size of the GPR area");
860 Error error = DoReadGPR(m_gpr_arm, sizeof(m_gpr_arm));
864 value.SetUInt32(m_gpr_arm[offset / sizeof(uint32_t)]);
868 Error NativeRegisterContextLinux_arm::DoWriteRegisterValue(
869 uint32_t offset, const char *reg_name, const RegisterValue &value) {
870 // PTRACE_POKEUSER don't work in the aarch64 linux kernel used on android
871 // devices (always return
872 // "Bad address"). To avoid using PTRACE_POKEUSER we read out the full GPR
873 // register set, modify
874 // the requested register and write it back. This approach is about 4 times
876 // performance overhead is negligible in comparision to processing time in
878 assert(offset % 4 == 0 && "Try to write a register with unaligned offset");
879 if (offset + sizeof(uint32_t) > sizeof(m_gpr_arm))
880 return Error("Register isn't fit into the size of the GPR area");
882 Error error = DoReadGPR(m_gpr_arm, sizeof(m_gpr_arm));
886 uint32_t reg_value = value.GetAsUInt32();
887 // As precaution for an undefined behavior encountered while setting PC we
888 // will clear thumb bit of new PC if we are already in thumb mode; that is
889 // CPSR thumb mode bit is set.
890 if (offset / sizeof(uint32_t) == gpr_pc_arm) {
891 // Check if we are already in thumb mode and
892 // thumb bit of current PC is read out to be zero and
893 // thumb bit of next PC is read out to be one.
894 if ((m_gpr_arm[gpr_cpsr_arm] & 0x20) && !(m_gpr_arm[gpr_pc_arm] & 0x01) &&
895 (value.GetAsUInt32() & 0x01)) {
896 reg_value &= (~1ull);
900 m_gpr_arm[offset / sizeof(uint32_t)] = reg_value;
901 return DoWriteGPR(m_gpr_arm, sizeof(m_gpr_arm));
904 Error NativeRegisterContextLinux_arm::DoReadGPR(void *buf, size_t buf_size) {
906 return NativeRegisterContextLinux::DoReadGPR(buf, buf_size);
909 ioVec.iov_base = buf;
910 ioVec.iov_len = buf_size;
912 return ReadRegisterSet(&ioVec, buf_size, NT_PRSTATUS);
916 Error NativeRegisterContextLinux_arm::DoWriteGPR(void *buf, size_t buf_size) {
918 return NativeRegisterContextLinux::DoWriteGPR(buf, buf_size);
921 ioVec.iov_base = buf;
922 ioVec.iov_len = buf_size;
924 return WriteRegisterSet(&ioVec, buf_size, NT_PRSTATUS);
928 Error NativeRegisterContextLinux_arm::DoReadFPR(void *buf, size_t buf_size) {
930 return NativeProcessLinux::PtraceWrapper(PTRACE_GETVFPREGS, m_thread.GetID(),
931 nullptr, buf, buf_size);
934 ioVec.iov_base = buf;
935 ioVec.iov_len = buf_size;
937 return ReadRegisterSet(&ioVec, buf_size, NT_ARM_VFP);
941 Error NativeRegisterContextLinux_arm::DoWriteFPR(void *buf, size_t buf_size) {
943 return NativeProcessLinux::PtraceWrapper(PTRACE_SETVFPREGS, m_thread.GetID(),
944 nullptr, buf, buf_size);
947 ioVec.iov_base = buf;
948 ioVec.iov_len = buf_size;
950 return WriteRegisterSet(&ioVec, buf_size, NT_ARM_VFP);
954 #endif // defined(__arm__) || defined(__arm64__) || defined(__aarch64__)