source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp

   1 //===-- RegisterContextPOSIX_arm64.cpp --------------------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #include <cstring>
  11 #include <errno.h>
  12 #include <stdint.h>
  13
  14 #include "lldb/Core/DataBufferHeap.h"
  15 #include "lldb/Core/DataExtractor.h"
  16 #include "lldb/Core/RegisterValue.h"
  17 #include "lldb/Core/Scalar.h"
  18 #include "lldb/Host/Endian.h"
  19 #include "lldb/Target/Target.h"
  20 #include "lldb/Target/Thread.h"
  21 #include "llvm/Support/Compiler.h"
  22
  23 #include "Plugins/Process/elf-core/ProcessElfCore.h"
  24 #include "RegisterContextPOSIX_arm64.h"
  25
  26 using namespace lldb;
  27 using namespace lldb_private;
  28
  29 // ARM64 general purpose registers.
  30 const uint32_t g_gpr_regnums_arm64[] = {
  31     gpr_x0_arm64,       gpr_x1_arm64,   gpr_x2_arm64,  gpr_x3_arm64,
  32     gpr_x4_arm64,       gpr_x5_arm64,   gpr_x6_arm64,  gpr_x7_arm64,
  33     gpr_x8_arm64,       gpr_x9_arm64,   gpr_x10_arm64, gpr_x11_arm64,
  34     gpr_x12_arm64,      gpr_x13_arm64,  gpr_x14_arm64, gpr_x15_arm64,
  35     gpr_x16_arm64,      gpr_x17_arm64,  gpr_x18_arm64, gpr_x19_arm64,
  36     gpr_x20_arm64,      gpr_x21_arm64,  gpr_x22_arm64, gpr_x23_arm64,
  37     gpr_x24_arm64,      gpr_x25_arm64,  gpr_x26_arm64, gpr_x27_arm64,
  38     gpr_x28_arm64,      gpr_fp_arm64,   gpr_lr_arm64,  gpr_sp_arm64,
  39     gpr_pc_arm64,       gpr_cpsr_arm64, gpr_w0_arm64,  gpr_w1_arm64,
  40     gpr_w2_arm64,       gpr_w3_arm64,   gpr_w4_arm64,  gpr_w5_arm64,
  41     gpr_w6_arm64,       gpr_w7_arm64,   gpr_w8_arm64,  gpr_w9_arm64,
  42     gpr_w10_arm64,      gpr_w11_arm64,  gpr_w12_arm64, gpr_w13_arm64,
  43     gpr_w14_arm64,      gpr_w15_arm64,  gpr_w16_arm64, gpr_w17_arm64,
  44     gpr_w18_arm64,      gpr_w19_arm64,  gpr_w20_arm64, gpr_w21_arm64,
  45     gpr_w22_arm64,      gpr_w23_arm64,  gpr_w24_arm64, gpr_w25_arm64,
  46     gpr_w26_arm64,      gpr_w27_arm64,  gpr_w28_arm64,
  47     LLDB_INVALID_REGNUM // register sets need to end with this flag
  48 };
  49 static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) -
  50                1) == k_num_gpr_registers_arm64,
  51               "g_gpr_regnums_arm64 has wrong number of register infos");
  52
  53 // ARM64 floating point registers.
  54 static const uint32_t g_fpu_regnums_arm64[] = {
  55     fpu_v0_arm64,       fpu_v1_arm64,   fpu_v2_arm64,  fpu_v3_arm64,
  56     fpu_v4_arm64,       fpu_v5_arm64,   fpu_v6_arm64,  fpu_v7_arm64,
  57     fpu_v8_arm64,       fpu_v9_arm64,   fpu_v10_arm64, fpu_v11_arm64,
  58     fpu_v12_arm64,      fpu_v13_arm64,  fpu_v14_arm64, fpu_v15_arm64,
  59     fpu_v16_arm64,      fpu_v17_arm64,  fpu_v18_arm64, fpu_v19_arm64,
  60     fpu_v20_arm64,      fpu_v21_arm64,  fpu_v22_arm64, fpu_v23_arm64,
  61     fpu_v24_arm64,      fpu_v25_arm64,  fpu_v26_arm64, fpu_v27_arm64,
  62     fpu_v28_arm64,      fpu_v29_arm64,  fpu_v30_arm64, fpu_v31_arm64,
  63     fpu_s0_arm64,       fpu_s1_arm64,   fpu_s2_arm64,  fpu_s3_arm64,
  64     fpu_s4_arm64,       fpu_s5_arm64,   fpu_s6_arm64,  fpu_s7_arm64,
  65     fpu_s8_arm64,       fpu_s9_arm64,   fpu_s10_arm64, fpu_s11_arm64,
  66     fpu_s12_arm64,      fpu_s13_arm64,  fpu_s14_arm64, fpu_s15_arm64,
  67     fpu_s16_arm64,      fpu_s17_arm64,  fpu_s18_arm64, fpu_s19_arm64,
  68     fpu_s20_arm64,      fpu_s21_arm64,  fpu_s22_arm64, fpu_s23_arm64,
  69     fpu_s24_arm64,      fpu_s25_arm64,  fpu_s26_arm64, fpu_s27_arm64,
  70     fpu_s28_arm64,      fpu_s29_arm64,  fpu_s30_arm64, fpu_s31_arm64,
  71
  72     fpu_d0_arm64,       fpu_d1_arm64,   fpu_d2_arm64,  fpu_d3_arm64,
  73     fpu_d4_arm64,       fpu_d5_arm64,   fpu_d6_arm64,  fpu_d7_arm64,
  74     fpu_d8_arm64,       fpu_d9_arm64,   fpu_d10_arm64, fpu_d11_arm64,
  75     fpu_d12_arm64,      fpu_d13_arm64,  fpu_d14_arm64, fpu_d15_arm64,
  76     fpu_d16_arm64,      fpu_d17_arm64,  fpu_d18_arm64, fpu_d19_arm64,
  77     fpu_d20_arm64,      fpu_d21_arm64,  fpu_d22_arm64, fpu_d23_arm64,
  78     fpu_d24_arm64,      fpu_d25_arm64,  fpu_d26_arm64, fpu_d27_arm64,
  79     fpu_d28_arm64,      fpu_d29_arm64,  fpu_d30_arm64, fpu_d31_arm64,
  80     fpu_fpsr_arm64,     fpu_fpcr_arm64,
  81     LLDB_INVALID_REGNUM // register sets need to end with this flag
  82 };
  83 static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) -
  84                1) == k_num_fpr_registers_arm64,
  85               "g_fpu_regnums_arm64 has wrong number of register infos");
  86
  87 // Number of register sets provided by this context.
  88 enum { k_num_register_sets = 2 };
  89
  90 // Register sets for ARM64.
  91 static const lldb_private::RegisterSet g_reg_sets_arm64[k_num_register_sets] = {
  92     {"General Purpose Registers", "gpr", k_num_gpr_registers_arm64,
  93      g_gpr_regnums_arm64},
  94     {"Floating Point Registers", "fpu", k_num_fpr_registers_arm64,
  95      g_fpu_regnums_arm64}};
  96
  97 bool RegisterContextPOSIX_arm64::IsGPR(unsigned reg) {
  98   return reg <= m_reg_info.last_gpr; // GPR's come first.
  99 }
 100
 101 bool RegisterContextPOSIX_arm64::IsFPR(unsigned reg) {
 102   return (m_reg_info.first_fpr <= reg && reg <= m_reg_info.last_fpr);
 103 }
 104
 105 RegisterContextPOSIX_arm64::RegisterContextPOSIX_arm64(
 106     lldb_private::Thread &thread, uint32_t concrete_frame_idx,
 107     lldb_private::RegisterInfoInterface *register_info)
 108     : lldb_private::RegisterContext(thread, concrete_frame_idx) {
 109   m_register_info_ap.reset(register_info);
 110
 111   switch (register_info->m_target_arch.GetMachine()) {
 112   case llvm::Triple::aarch64:
 113     m_reg_info.num_registers = k_num_registers_arm64;
 114     m_reg_info.num_gpr_registers = k_num_gpr_registers_arm64;
 115     m_reg_info.num_fpr_registers = k_num_fpr_registers_arm64;
 116     m_reg_info.last_gpr = k_last_gpr_arm64;
 117     m_reg_info.first_fpr = k_first_fpr_arm64;
 118     m_reg_info.last_fpr = k_last_fpr_arm64;
 119     m_reg_info.first_fpr_v = fpu_v0_arm64;
 120     m_reg_info.last_fpr_v = fpu_v31_arm64;
 121     m_reg_info.gpr_flags = gpr_cpsr_arm64;
 122     break;
 123   default:
 124     assert(false && "Unhandled target architecture.");
 125     break;
 126   }
 127
 128   ::memset(&m_fpr, 0, sizeof m_fpr);
 129
 130   // elf-core yet to support ReadFPR()
 131   lldb::ProcessSP base = CalculateProcess();
 132   if (base.get()->GetPluginName() == ProcessElfCore::GetPluginNameStatic())
 133     return;
 134 }
 135
 136 RegisterContextPOSIX_arm64::~RegisterContextPOSIX_arm64() {}
 137
 138 void RegisterContextPOSIX_arm64::Invalidate() {}
 139
 140 void RegisterContextPOSIX_arm64::InvalidateAllRegisters() {}
 141
 142 unsigned RegisterContextPOSIX_arm64::GetRegisterOffset(unsigned reg) {
 143   assert(reg < m_reg_info.num_registers && "Invalid register number.");
 144   return GetRegisterInfo()[reg].byte_offset;
 145 }
 146
 147 unsigned RegisterContextPOSIX_arm64::GetRegisterSize(unsigned reg) {
 148   assert(reg < m_reg_info.num_registers && "Invalid register number.");
 149   return GetRegisterInfo()[reg].byte_size;
 150 }
 151
 152 size_t RegisterContextPOSIX_arm64::GetRegisterCount() {
 153   size_t num_registers =
 154       m_reg_info.num_gpr_registers + m_reg_info.num_fpr_registers;
 155   return num_registers;
 156 }
 157
 158 size_t RegisterContextPOSIX_arm64::GetGPRSize() {
 159   return m_register_info_ap->GetGPRSize();
 160 }
 161
 162 const lldb_private::RegisterInfo *
 163 RegisterContextPOSIX_arm64::GetRegisterInfo() {
 164   // Commonly, this method is overridden and g_register_infos is copied and
 165   // specialized.
 166   // So, use GetRegisterInfo() rather than g_register_infos in this scope.
 167   return m_register_info_ap->GetRegisterInfo();
 168 }
 169
 170 const lldb_private::RegisterInfo *
 171 RegisterContextPOSIX_arm64::GetRegisterInfoAtIndex(size_t reg) {
 172   if (reg < m_reg_info.num_registers)
 173     return &GetRegisterInfo()[reg];
 174   else
 175     return NULL;
 176 }
 177
 178 size_t RegisterContextPOSIX_arm64::GetRegisterSetCount() {
 179   size_t sets = 0;
 180   for (size_t set = 0; set < k_num_register_sets; ++set) {
 181     if (IsRegisterSetAvailable(set))
 182       ++sets;
 183   }
 184
 185   return sets;
 186 }
 187
 188 const lldb_private::RegisterSet *
 189 RegisterContextPOSIX_arm64::GetRegisterSet(size_t set) {
 190   if (IsRegisterSetAvailable(set)) {
 191     switch (m_register_info_ap->m_target_arch.GetMachine()) {
 192     case llvm::Triple::aarch64:
 193       return &g_reg_sets_arm64[set];
 194     default:
 195       assert(false && "Unhandled target architecture.");
 196       return NULL;
 197     }
 198   }
 199   return NULL;
 200 }
 201
 202 const char *RegisterContextPOSIX_arm64::GetRegisterName(unsigned reg) {
 203   assert(reg < m_reg_info.num_registers && "Invalid register offset.");
 204   return GetRegisterInfo()[reg].name;
 205 }
 206
 207 lldb::ByteOrder RegisterContextPOSIX_arm64::GetByteOrder() {
 208   // Get the target process whose privileged thread was used for the register
 209   // read.
 210   lldb::ByteOrder byte_order = lldb::eByteOrderInvalid;
 211   lldb_private::Process *process = CalculateProcess().get();
 212
 213   if (process)
 214     byte_order = process->GetByteOrder();
 215   return byte_order;
 216 }
 217
 218 bool RegisterContextPOSIX_arm64::IsRegisterSetAvailable(size_t set_index) {
 219   return set_index < k_num_register_sets;
 220 }
 221
 222 // Used when parsing DWARF and EH frame information and any other
 223 // object file sections that contain register numbers in them.
 224 uint32_t RegisterContextPOSIX_arm64::ConvertRegisterKindToRegisterNumber(
 225     lldb::RegisterKind kind, uint32_t num) {
 226   const uint32_t num_regs = GetRegisterCount();
 227
 228   assert(kind < lldb::kNumRegisterKinds);
 229   for (uint32_t reg_idx = 0; reg_idx < num_regs; ++reg_idx) {
 230     const lldb_private::RegisterInfo *reg_info =
 231         GetRegisterInfoAtIndex(reg_idx);
 232
 233     if (reg_info->kinds[kind] == num)
 234       return reg_idx;
 235   }
 236
 237   return LLDB_INVALID_REGNUM;
 238 }